JPH02294121A - Transmission system for parallel/serial conversion coding information signal - Google Patents

Abstract

PURPOSE:To simplify the constitution of the entire coding information signal transmission system by eliminating unlocking of a clock phase caused at the time of decoding while the clock phase is shifted little by little till the rephasing comes to normal. CONSTITUTION:When a timing to read a time series coding signal inputted to a shift register (SR) 1 to an 8-bit D register group (R) 2 in parallel is deviated by one transmission clock, the transmission clock signal driving the input of the time series coding signal to the shift register (SR) 1 is stopped by one clock. Then the signal is read in parallel for a proper period from the succeeding clock timing. Thus, it is not required to add an excess signal for assuring the clock phase locking at the time of decoding to apply simple parallel serial conversion to the coding information signal and to form the transmission time series signal. Thus, the entire coding information signal system is simplified.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention transmits a time-series signal obtained by encoding an information signal such as a high-definition television signal into 8 bits, converting it from parallel to serial, and converting it from serial to parallel. This invention relates to a parallel-to-serial conversion encoded information signal transmission system in which decoding is performed using parallel-to-serial conversion, and in particular, by improving the decoder input interface, it is possible to easily transmit time-series encoded signals by this type of parallel-to-serial conversion.

(Summary of the Invention) The present invention provides a frame for ensuring phase lock during decoding when transmitting a time-series signal obtained by encoding an information signal such as a high-definition television signal into, for example, 8 bits and converting it from parallel to serial.゛The decoder operates normally and decoding is performed properly so that the time-series encoded signal can be simply parallel-serial converted and transmitted in time-series without the need to complicate the time-series encoded signal by adding synchronization etc. Until this happens, the clock phase for serial-to-parallel conversion is shifted by one bit at an appropriate period depending on the state of phase lock in the decoder.

(Prior Art) Generally, when high-definition television signals such as so-called FIUSE signals are encoded and transmitted in digital format, the clock frequency is usually 16.2 MHz, for example.
The sampled pixel signal is encoded into 8 bits and transmitted. If such 8-bit encoded signals are transmitted in parallel using 8 lines, no problem will arise regarding the clock phase, but if the 8 bits are serialized in time order,
When transmitting serially over a main line, that is, when transmitting by modulating the carrier wave, the 8 bits are simply time-series and a bit stream signal with a clock frequency of 16.2 x 8 = 129.6 MS/S is generated. If the data is simply converted into the format and then transmitted, the following problems will occur.

(1) Difficulty in extracting a transmission clock directly from a time-series transmission signal (2) The importance order of each bit in a time-series signal serialized into a series of time-series signals, that is, which bit is a unit such as a pixel signal Since the most significant bit of the 8 bits corresponding to the information signal, that is, the frame/word synchronization signal indicating whether it is the so-called MSB, is not added to the time series signal, it is divided into appropriate 8 bits. Difficulties in appropriately parallelizing and decoding time series signals Therefore, in the past, in order to eliminate the above-mentioned difficulties and eliminate the problem of parallel-serial conversion time series signal transmission, coded information signals When converting serially into a time series, an additional frame synchronization signal is inserted to facilitate appropriate 8-bit partitioning, and this problem occurs when encoding image signals with strong correlation between each pixel. In order to eliminate the difficulty of extracting a transmission clock from a time-series signal due to the easy succession of the same bits, the time-series signal is scrambled by intermittent inversion of the positive and negative bits.

(Problem to be Solved by the Invention) However, in order to add a frame synchronization signal to the time-series encoded information signal formed by parallel-to-serial conversion in order to ensure clock phase lock during decoding, it is necessary to complicate the transmission signal. In addition, the configuration of the encoding circuit on the transmitting side becomes significantly more complicated, and it is necessary to use a large-scale serial-to-parallel converter circuit for decoding on the receiving side. Therefore, it has been a challenge in the past to simplify the time-series encoded signal transmission system, which has become increasingly complex.

(Means for Solving the Problems) An object of the present invention is to solve the above-mentioned conventional problems, and to encode each unit of information into multiple bits when encoding and digitally transmitting an information signal such as a high-definition television signal. When parallel-serial converting the converted information signal into a time-series signal and digitally transmitting it, the transmission form of the transmitted time-series signal,
Therefore, we have developed a parallel-to-serial conversion encoded information signal transmission method that enables digital transmission of encoded information by simply performing parallel-to-serial conversion without complicating the configurations of the encoding and decoding circuits. It is about providing.

That is, the parallel-to-serial conversion encoded information signal transmission system of the present invention mechanically performs only simple parallel-to-serial conversion on an encoded information signal having a multi-bit configuration and then digitally transmits the signal. Until the decoding operation normalizes, the clock phase is gradually shifted to resolve the problem7, and time-series encoding is performed by parallel-to-serial conversion of an information signal encoded into multiple bits for each unit of information. When transmitting an information signal and serial-to-parallel converting the received time-series encoded information signal to decode the information signal for each unit of information, the plurality of serially-parallel converting the time-series encoded information signal. The present invention is characterized in that the phase of the bits is sequentially shifted by one bit at a predetermined period depending on the suitability of the result of decoding the information signal.

(Function) Therefore, according to the present invention, an encoded information signal can be simply parallel-serial converted without adding an extra signal to ensure clock phase lock during decoding in digital transmission of an encoded information signal. It is possible to form a time-series signal for transmission by using the method, and it becomes possible to simplify the entire encoded information signal transmission system. (Example) The present invention will be described in detail below with reference to the drawings.

When digitally transmitting, for example, a high-definition television image signal using the method of the present invention, it is possible to easily extract the transmission clock by avoiding consecutive identical bits based on the correlation in the digital transmission of encoded image signals, as described above. In order to do this, except for the most significant bit (κSB) and the fourth significant bit in the 8-bit pixel digit, all other bits are inverted and parallel-to-serial conversion is performed, and the transmission is based on the lowest significant bit (LSB). ).

FIG. 1 shows the basic configuration of a serial-to-parallel conversion circuit that restores a time-series encoded signal formed by parallel-to-serial conversion into a parallel encoded signal as described above. The figure shows a state in which time-series encoded signals are parallelized at the timing of appropriately partitioning 8 bits corresponding to unit information, and the 8-bit encoded information signal is sequentially processed from LSB to 129.6? At the timing input to shift register (SR) 1 using the IS/S transmission clock, each bit is read out in parallel, and the D-register group (R
)2 and 16.2 Mllz sample clocks to read parallel encoded information signals.

As mentioned above, if the timing of reading out the 8 bits of the time-series encoded signal input to the shift register (SR) 1 in parallel is not appropriate, a parallel code consisting of 8 bits in an incorrect arrangement will be generated, as shown in Figure 2. The converted signal will be read out. In the illustrated example, the timing at which 8 bits of the time-series encoded signal input to shift register (SR) 1 are read out in parallel is 1.
This is an example of a case where the transmission clock is shifted by one clock. In this case, the 129.6 MS/S transmission clock signal that drives the input of the time series encoded signal to shift register (SR) 1 is shifted by one clock. Once stopped, parallel reading will be performed in appropriate sections from the next clock timing. Furthermore, if the timing is off by 2 clocks, the transmission clock signal is stopped by 2 clocks, and the same procedure is repeated, so that the timing of parallel readout can be corrected no matter how much the timing is off. be able to.

Now, when serial-to-parallel conversion is performed as described above at the decoder input interface of the encoded signal transmission system, the frame pulse in the encoded image signal with all bits except the MSB and the 4th bit inverted as described above. And the high level and low level of the control code part, when expressed in hexadecimal code, are EF and 10, respectively, as shown in FIG. 3, but are 80, respectively.
and 7F.

As mentioned above, when performing serial-to-parallel conversion on a time-series encoded signal using the circuit configuration shown in the first diagram, the shift register (SR
) When the parallel reading from 1 is performed at the proper timing, a proper parallel encoded signal can be decoded, but when the parallel reading is not done at the proper timing, the MSB
An incorrectly arranged encoded signal will be read out from itself.

As mentioned above, if at least one of the high level and low level of the encoded image signal frame pulse, control code, etc. obtained from the serial-to-parallel conversion circuit in the decoder interface consists of 8 bits in an incorrect arrangement. In this case, the encoded image signal will not be decoded correctly, and at least a code error will occur in the control code signal, and the phase-locked loop (PLL)
The system will become unlocked.

Therefore, when an information signal such as a high-definition television image signal obtained from a decoder shows an error, the error is detected once every code frame, or once every several code frames.
At an appropriate period that varies depending on the configuration of the decoder, etc., the transmission clock signal that drives the shift register (SR) l in the configuration shown in FIG.
Shift the positional relationship of the 8 bits of the time-series encoded signal within 1 bit by 1 bit, read out the 8 bits of the appropriate section in parallel, and find the appropriate parallel readout timing that can restore a normal information signal. For example, even if a simple time-series encoded information signal is not added with a frame synchronization signal, a normal information signal can be restored by performing appropriate serial-to-parallel conversion.

Note that, for example, whether a high-definition television signal is correctly restored by a decoder is determined by the phase-locked loop (
It is possible to make an appropriate judgment based on whether or not the phase lock of the PLL system is released, or whether the control signal is properly reproduced.

Therefore, a specific configuration of a serial-to-parallel conversion circuit for restoring a time-series encoded information signal to a parallel encoded information signal according to the method of the present invention is shown in FIG. 4, for example.

The combination of shift register (SR) 1 and register (R) 2 in the illustrated configuration is exactly the same as the basic configuration shown in FIG. The decoded output information signal, such as a descendant-quality television image signal, is extracted by supplying the decoded signal and subjecting it to necessary decoding processing.

If a data error occurs in the decoded output information signal due to clock phase lock loss, the phase lock loss signal generated in response to error detection by the conventional error detection means provided in the decoder 3 and The code frame pulse is supplied to the controller 3, and the controller 3 sends out a clock stop command signal at a predetermined period of, for example, one frame or several frames, and controls the NA.
It is supplied to the ND circuit 6. The NAND circuit 6 receives the frame pulse FP from the decoder 3 and the frame pulse FP from the D-register, that is, the D-flip-flop 4.
A NAND circuit 6 of the frame pulse which is narrowed by the combination of the delayed inverted pulse which is guided to the Q output and which is obtained as its Q output, and the clock stop command signal described above.
In cooperation with each other, an inhibit signal "0" for stopping the supply of the clock signal for one clock period is generated and supplied to the AND circuit 7. The AND circuit 7 receives the frequency (16.2 x
8)=129.6 Mllz transmission clock signal is supplied, and via this AND circuit 7, the shift register (S
It is applied to the clock input terminal (CK) of R)1 to drive its shift register (SR)1. therefore,
When the inhibit signal "0" is supplied to the AND circuit 7, the application of the transmission clock signal that drives the shift register (SR) 1 is stopped for one clock period in accordance with the supply, and as a result, the shift register (SR) The parallel read clock phase from 1 is shifted by one clock, and the parallel read clock phase is corrected as described above.

In addition, in the serial-to-parallel converter circuit having the configuration shown in FIG.
The phase of the transmission clock signal of , the frequency included in the time-series encoded transmission signal (16.2X
4) = 62.8 MHz clock component is extracted by filter 10 and supplied to phase comparator (PD) 11, and frequency 129.6 from voltage controlled oscillator (VCO) 8 is extracted.
A switch (S
) 12 to control the voltage controlled oscillator (VCO) 8. In contrast, in a state where proper clock phase lock is performed for the decoding operation in the tecoder 3 and a normal decoding output is obtained, A sample clock signal with a frequency of 16.2 MHz generated within the tecoder 3 is supplied to another phase comparator (PD) 14, and a clock signal with a frequency of 129.6 MHz from a voltage controlled oscillator (VCO) 8 is supplied to the other phase comparator (PD) 14. The phase comparison output with the 178 frequency-divided component supplied via the frequency divider 13 is fed back to the voltage controlled oscillator (VCO) 8 via the changeover switch (S) 12 for control.

The reason why the phase of the transmission clock signal that drives the shift register (SR) 1 is controlled in two ways as described above is that the phase control using the clock component extracted from the time-series encoded transmission signal is Signals do not necessarily include
Since scrambling is not applied to facilitate the extraction of clock components, the accuracy of clock phase lock tends to be low, and in some cases, there is a risk that errors may occur in data acquisition. This is because in a state where phase lock is achieved, it is better to lock the phase to the clock signal generated within the decoder to ensure a higher accuracy. (Effects of the Invention) As is clear from the above description, according to the present invention, the encoded information signal can be transmitted without adding an extra signal for ensuring clock phase lock during decoding in digital transmission of the encoded information signal. can be simply parallel-serial converted to form a time-series signal for transmission, and the special effect of simplifying the configuration of the entire encoded information signal transmission system can be obtained.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the basic configuration of a serial-to-parallel conversion circuit, Fig. 2 is a diagram showing an example of suitability of serial-to-parallel conversion, and Fig. 3 is a diagram showing an example of bit inversion of an encoded signal. FIG. 4 is a block diagram showing an example of the configuration of a serial-to-parallel conversion circuit according to the present invention. 1... Shift register (SR) 2... Register (R") 3... Decoder 4... D-register 5... Controller 6... NAND circuit 7... AND circuit 8...・Voltage controlled oscillator (VCO) 9... 172 frequency divider 10... Filter 11. 14... Phase comparator (PD) 12... Changeover switch 13... 178 frequency divider.

Claims (1)

[Claims] 1. Transmitting a time-series encoded information signal formed by parallel-to-serial conversion of an information signal encoded into a plurality of bits for each unit of information, and directly converting the received time-series encoded information signal. In parallel converting and decoding the information signal for each unit of information,
The phase of the plurality of bits sequentially converted from serial to parallel in the time-series encoded information signal is sequentially shifted by one bit at a predetermined period depending on the suitability of the result of decoding the information signal. Parallel-to-serial conversion encoded information signal transmission system. 2. The parallel-to-serial conversion encoded information signal transmission system according to claim 1, wherein the predetermined period is an integral multiple of the encoded frame period, including equal times. 3. The clock signal for controlling the serial-to-parallel conversion is switched to a clock signal generated on the receiving side in synchronization with the time-series encoded information signal, depending on the optimization of the result of the information signal decoding. A parallel-to-serial conversion encoded information signal transmission system according to claim 1 or 2. 4. When the plurality of bits are 8 bits, the most significant bit and the 4th bit of the 8 bits or all bits except the most significant bit and the 4th significant bit are respectively inverted and the time series encoding is performed. A parallel-to-serial conversion encoded information signal transmission system according to claim 1, 2, or 3, characterized in that the information signal is configured as an information signal.