JPH02294272A - Rectifying circuit - Google Patents

Rectifying circuit

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Publication number
JPH02294272A
JPH02294272A JP11442389A JP11442389A JPH02294272A JP H02294272 A JPH02294272 A JP H02294272A JP 11442389 A JP11442389 A JP 11442389A JP 11442389 A JP11442389 A JP 11442389A JP H02294272 A JPH02294272 A JP H02294272A
Authority
JP
Japan
Prior art keywords
voltage
transistor
resistor
rectifier circuit
series
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11442389A
Other languages
Japanese (ja)
Inventor
Masaoki Sekine
正興 関根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Origin Electric Co Ltd
Original Assignee
Origin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Origin Electric Co Ltd filed Critical Origin Electric Co Ltd
Priority to JP11442389A priority Critical patent/JPH02294272A/en
Publication of JPH02294272A publication Critical patent/JPH02294272A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利川分野〕 本発明は.交流電圧を全波!i!流して直流電圧を得る
整流回路で,特に交流電圧が大きく変動する整流回路に
関する. 〔従来の技術〕 航空機内で使用される電気機器の電源は.エンジン発電
機が使用されるため人力電圧の瞬断があり,しかも瞬断
後の電圧が定當状態に達するまでに1秒程度の時間を要
する.この間,電気機器の動作を維持するためには,膨
大な容量のコンデンサや電池が必要となる.特に,航空
機の場合には,かなり低い温度条件で使用されるため.
通常の電池では動作不能となり.特殊な電池が必要とな
って,高価なものとなる.このため.瞬断補償川のコン
デンサ容量を低減させるために.発電機が動作し始めた
時点より機器を動作させる必要が生じる.しかし,発電
機の動作開始時の電圧は定當時の約172であり,この
電圧を機器の動作可能電圧としておくと,定常時は2倍
以上の電圧が発生することとなり好ましくない. 一方.単相商用交流電圧は世界各国により異なり100
ポルトより240ボルト迄広範囲に渡るため.これら電
圧を共通に使用できるように電気1i器の整流方式をl
OOポルトは倍電圧,200ボルトはブリッジ!i流と
する方法が公知の技術としてあり,発電機の出力電圧が
低い間は倍電圧整流.電圧が定常状態時はブリッジ整流
とする方法が考えられる. 従来の倍電圧一ブリッジ!i!流9り替え方法としては
第5図に示すものがあり.この図に従って説明する.同
図において.交流電allの電圧が低い時はスイッチ2
が閉じられ,コンデンサ3.4の両端には交流電圧のほ
ぼピーク電圧の2倍の電圧が発生する.また,交流11
!源lの電圧が高い時はスイッチ2が開かれ.通常の全
波ブリ,ジ整流となり,コンデンサ3,4の両端には交
流電圧のほぼピーク電圧が発生する.このようにスイッ
チ2を開閉することにより人力電圧が2倍変化しても整
流出力電圧の変化を少なくすることができる.尚.5〜
8はダイオードである. しかしながら.この方法ではスイッチ濠作を誤ると出力
に過大電圧を発生させてしまうという問題がある.そこ
で.゛第6図に示すような回路例が特開昭63−302
762号公報に開示されている.この方法はスイッチの
代わりにトライア7クを使用し.整流出力電圧をUJT
で検出し.トライアックのゲートを自動的にv4御する
もので,以下図を参照して説明する.!!流回路の直流
電圧を抵抗9,10. 11で分圧し,抵抗l1の電圧
をtJJT12のゲートに加え.7ノードは抵抗l3を
介してツェナダイオード14のカソ一ドに接続している
.このためUJT12のゲート電圧は直流出力電圧に比
例し.アノード電圧はツェナ電圧にクランプされる.交
流入力電圧が200ボルト系の場合.ツエナ電圧より抵
抗l1に発生する電圧が高くなるように抵抗9,10.
 11を設定しておくと,UJT12はオフし,トラン
ジスタl5は導通できず,トライアフクl6のゲートに
は電圧が印加されず.トライアフクl6はオフし.!!
!流回路はブリッジ整流となる.また,交流入力電圧が
100ボルト系の場合,ツエナ電圧より抵抗1lに発生
する電圧が低くなるように抵抗9. 10. 11を設
定しておくと,UJT12のゲートはトリガされて導通
し.抵抗l7の両端に電圧を発生させ.トランジスタ【
5を導通させてトライブックのゲートをトリガし.導通
させる.この結果.倍電圧整流回路となる.このように
.出力電圧を検出し自動的に切り替えるので.誤動作に
よる事故を防止することができる.尚.l8はコンデン
サ.19〜2lは抵抗である. 〔発明が解決しようとする課題〕 しかし,このような従来の整流回路にあっては.第5図
の例では誤動作.m6図の例では$I1御用の部品点数
が多く.また順方向電圧降下が大きいため低電圧出力で
は損失が大きいという欠点がある.しかも.従来の方法
はディジタル的な入力電圧の変化に対応しているので,
航空機のエンジン発電機のようにアナログ的に変化する
場合には適さない.91えば第6図の例ではUJTが一
旦オンすると自己保持してしまい,倍電圧整流のままと
なってしまう゜ので.入力電圧が低い値から緩やかに上
昇する場合,ブリッジ整流に切り替えて直流出力電圧を
下げることができな《なる.(課題を解決するための手
段) 本発明は以上の欠点を除去するために.交流電圧を全波
整流する整流ブリッジ回路の直流出力端子間に直列接続
された2111の平滑用コンデンサを接続した整流回路
において,ソースを共通接続点として逆方向に直列に接
続されたFETの直列接続体の一方のドレインと他方の
ドレインとを.夫々上記平滑用コンデンサの接続点と!
adブリツノ回路の交流入力端子の何れか一方とに接続
すると共に.上記FETの直列接続体の夫kのゲート・
ソース間が,上記直流出力端子間電圧が設定値以上の時
逆バイアスされ,設定値以下の時順バイアスされるよう
に接続されていることを特徴とする整流回路を提供する
ものである. {作用) 本発明は上記のような構成になっているので.交流入力
電圧がアナログ的に変化する場合にも倍電圧一ブリッジ
整流の相互切り替えをすることができる. 〔実施例〕 第1図は本発明の一実施例を示す図である.同図におい
て,交fL電源■をダイオード5〜8で構成されるブリ
ッジ整流回路の交流入力端子に接続し.替流回路の直流
出力に平滑用コンデンサ3.4の直列接続回路を接続し
ている.平滑用コンデンサ3.4の直列接続点と整流ブ
リッジの交流入力端子の一端をN ” F E T22
. 23をソースを共通接続点として逆方向に直列接続
した直列回路の各々のドレインに接続し.直流出力端子
間に抵抗24ツエナダイオード25,低抗26を接続し
.該抵抗26の両端にNPN トランジスタ27のペー
ス エミッタを接続し.トランジスタ27のコレクタと
直流出力の正側とを抵抗2日を介して接続し,トランジ
スタ27のコレクタはFET22.23のゲートへ接続
し.FET22.23のソースと直流出力の負側とを抵
抗29を介して接続している. 次に.この実yl例の勤作を説明する.先ず.直流出力
電圧が低くツェナダイオード25が導通できないと.ト
ランジスタ27のベース・エミッタ間に電圧が発生しな
いためトランジスタ27はオフしている.すると.FE
722.23のゲート・ソース間は低抗2B. 29を
介して順バイアスされるので.FE722. 23は導
通し,平滑コンデンサ3.4の接続点と整流ブリッジの
交流入力端子の一端とは接続され,倍電圧整流となり,
出力電圧は交流電圧のほぼピーク電圧の2倍となる.そ
して FET22. 23が導通するためソース電位は
平滑コンデンサ3.4の直列接続点となり,ゲート・ソ
ース間電圧は直流出力電圧の1/2となる.尚.FE”
rはドレイン・ソース間に双方向に電流を流すことがで
き,しかも電圧降下はオン抵抗で決定されるので.低電
圧出力のときはオン抵抗の小さい素子を使川することに
より,電圧降下をトライアフクより小さくすることがで
きる.次に.出力電圧が高《ツェナダイオード25が導
通すると,トランジスタ27のベースに電流が流れ込み
.トランジスタ27が導通し.FET22.23はゲー
ト・ソース間が抵抗29を介して短絡されてオフするの
で,平滑コンデンサ3,4の直列接続点と交流入力端子
の一端とは切り離されて,ブリッジ整流となり,直流出
力電圧はおよそピーク電圧となる. 第2図は本発明の41の一実施例を説明するための図で
ある.同図において,直流出力電圧が低い時は,ツェナ
ダイオード25がオフし,トランジスタ30がオフして
いる.この結果.トランジスタ3lにはベース電流が供
給されず.トランジスタ31はオフしており.トランジ
スタ27にもベース?lが供給されないので.トランジ
スタ27もオフしている.この結果.FE722.23
のゲートが抵抗2829で順バイアスされて導通し,平
滑コンデンサ34の直列接続点と交流入力端子の一端と
が接続され.倍電圧整流回路となる.次に.直流出力電
圧が上昇すると,ツヱナダイオード25が導通し.トラ
ンシスタ30にベース電流を供給してトランジスタ30
をオンさせる.すると,トランジスタ3lにベースil
lが流れるので.該トランジスタ31がオンし,トラン
ジスタ27にベース電流が供給されるので.該トランジ
スタ27がオンし,  FET22  23のゲートが
抵抗29を介して短絡されるので.該FET22. 2
3がオフし,ブリッジ!lfiにφり替わる.ここで,
トランジスタ3lが導通すると.抵抗32を介してトラ
ンジスタ30にベースfa流が流れ,正帰還がかかる.
すると.直流電圧が低下し,ツェナダイオード25がオ
フしても.抵抗32を介してトランジスタ30にベース
電流が供給されるので,トランジスタ30は導通したま
まとなり,FET22.23はオフしたままとなる.そ
して,直流出力電圧が大きく低下し.抵抗26への電圧
降下がトランジスタ30の導通を維持できなくなるまで
下がるとトランジスタ30がオフし.トランジスタ31
. 27がオフし,FET22,23は導通し.倍電圧
整流にφり替わる.また.抵抗24の抵抗値をRl. 
tlt抗26の抵抗値をR2.抵抗32の抵抗値をR3
とし,ツェナダイオード25の電圧をv4,トランジス
タ30が導通するためのベース・エミ7夕電圧をv5.
トランジスタ30がオン,オフする時の直流出力電圧を
夫々V6  V7とすると v6≧V4+ (R1+R2) V5/112v1;=
 (R2+R3)ν5/R2 となり,V6>2V7となるように抵抗値を選定するこ
とにより,交流入力電圧がアナログ的に変化しても,倍
電圧整流とブリッジ整流とのリリ替え時におけるチャタ
リングの発生がない.尚,33〜36は低抗である. 第3図は本発明の他の一実施例を示す閲てある.この実
施例は.第2図でN型FET22.23を用いていたの
に対して.P型FE737,38を用いるようにしたも
のであって,第2図の実施例で述べたのとほぼ同様であ
り,同様の効果が{″.Iられる.尚. 39. 40
は抵抗である. 第4図は,直流出力電圧が高<.FETのゲート・ソー
ス間の耐圧を超える場合,ゲート保護のため.ゲート・
フェス間にツェナダイオード4lを接続したものである
.この実施例においても,以上述べたのとほぼ同様であ
り,同様の効果が得られる. 〔発明の効果〕 以上説明してきたように,本発明によれば,交流入力電
圧がアナログ的に変化する場合にも.倍電圧一ブリッジ
整流の相互切り替えをすることができる.また,電圧降
下が減少すると共に駆動が単純化され.回路構成が油単
化して部品点数が減少する.更に.直流出力端子間電圧
の検出にヒステリシス特性を持たせることにより.交流
入力電圧がアナログ的に変化しても.倍電圧整流とブリ
ッジ整流との切り替え時におけるチヤタリングの発生が
なくなる.更に加えて,トライアックの場合,−55゜
Cのような低温になると.ゲート駆動ftIILが著し
く必要となるが.FETは絶縁駆動のため.駆動パワー
はトライアフクに比べ非常に少なくてすむという利点が
ある.
[Detailed Description of the Invention] [Industrial Icheon Field] The present invention... Full wave AC voltage! i! This is a rectifier circuit that obtains a DC voltage by flowing current, and is particularly concerned with rectifier circuits in which the AC voltage fluctuates greatly. [Prior Art] What is the power source for electrical equipment used in aircraft? Since an engine generator is used, there are momentary power interruptions in the human voltage, and it takes about one second for the voltage to reach a steady state after a momentary interruption. During this time, huge amounts of capacitors and batteries are required to maintain the operation of electrical equipment. Especially in the case of aircraft, this is because they are used under fairly low temperature conditions.
It cannot operate with normal batteries. This requires a special battery, which is expensive. For this reason. In order to reduce the capacitor capacity of the instantaneous interruption compensation river. It becomes necessary to start operating the equipment from the moment the generator starts operating. However, the voltage at the start of the generator's operation is approximately 172V at steady state, and if this voltage were used as the operating voltage of the equipment, the voltage would be more than twice as high during steady state, which is not desirable. on the other hand. Single-phase commercial AC voltage varies by country around the world.
Because it covers a wide range from Porto to 240 volts. In order to use these voltages in common, we changed the rectification method of the electric 1i converter.
OO port is a voltage doubler, 200 volts is a bridge! There is a method known in the art to use i-current, and while the output voltage of the generator is low, voltage doubler rectification is used. Bridge rectification can be considered when the voltage is in a steady state. Conventional voltage doubler bridge! i! There is a method for changing the flow as shown in Figure 5. Explain according to this diagram. In the same figure. When the voltage of AC power all is low, switch 2
is closed, and a voltage approximately twice the peak voltage of the AC voltage is generated across the capacitor 3.4. Also, AC 11
! When the voltage of source 1 is high, switch 2 is opened. This is normal full-wave rectification, and almost the peak voltage of the AC voltage is generated across capacitors 3 and 4. By opening and closing the switch 2 in this way, even if the human power voltage changes twice, the change in the rectified output voltage can be reduced. still. 5~
8 is a diode. however. This method has the problem that if the switch moat is made incorrectly, excessive voltage will be generated at the output. Therefore.゛An example of the circuit shown in Fig. 6 is published in Japanese Patent Application Laid-Open No. 63-302.
It is disclosed in Publication No. 762. This method uses triarchs instead of switches. UJT rectified output voltage
Detect it with . It automatically controls the triac gate using V4, and will be explained with reference to the diagram below. ! ! The DC voltage of the current circuit is connected to resistors 9, 10 . 11 and apply the voltage of resistor l1 to the gate of tJJT12. Node 7 is connected to the cathode of Zener diode 14 via resistor l3. Therefore, the gate voltage of UJT12 is proportional to the DC output voltage. The anode voltage is clamped to the Zener voltage. When the AC input voltage is 200 volts. The resistors 9, 10 .
If 11 is set, UJT12 is turned off, transistor l5 cannot conduct, and no voltage is applied to the gate of trifuku l6. Triafuku l6 is off. ! !
! The current circuit is bridge rectification. In addition, when the AC input voltage is 100 volts, the resistor 9. 10. 11, the gate of UJT12 is triggered and becomes conductive. A voltage is generated across the resistor l7. Transistor [
5 conducts to trigger the trybook gate. Make it conductive. As a result. It becomes a voltage doubler rectifier circuit. in this way. It detects the output voltage and switches automatically. Accidents due to malfunction can be prevented. still. l8 is a capacitor. 19~2l is the resistance. [Problems to be solved by the invention] However, with such conventional rectifier circuits. The example in Figure 5 is a malfunction. In the example of the m6 diagram, there are many parts for $I1. Also, because the forward voltage drop is large, there is a drawback that there is a large loss at low voltage output. Moreover. Conventional methods respond to changes in digital input voltage, so
It is not suitable for cases where changes occur analogously, such as in aircraft engine generators. 91 For example, in the example shown in Figure 6, once the UJT is turned on, it self-holds and remains in voltage double rectification mode. When the input voltage rises slowly from a low value, it becomes impossible to switch to bridge rectification and lower the DC output voltage. (Means for Solving the Problems) The present invention aims to eliminate the above drawbacks. In a rectifier circuit with a 2111 smoothing capacitor connected in series between the DC output terminals of a rectifier bridge circuit that full-wave rectifies an AC voltage, series connection of FETs connected in series in opposite directions with the source as a common connection point. The drain on one side of the body and the drain on the other side. The connection points of the smoothing capacitors above, respectively!
In addition to connecting to either one of the AC input terminals of the AD Britsuno circuit. The gate of the husband k of the series connection body of the above FETs.
The present invention provides a rectifier circuit characterized in that the sources are connected so that the voltage between the DC output terminals is reverse biased when it is above a set value, and is biased in time order when the voltage between the DC output terminals is below the set value. {Function) The present invention has the above structure. Even when the AC input voltage changes in an analog manner, it is possible to switch between voltage doubler and one-bridge rectification. [Example] Figure 1 is a diagram showing an example of the present invention. In the same figure, the AC fL power supply ■ is connected to the AC input terminal of a bridge rectifier circuit composed of diodes 5 to 8. A series connection circuit of 3.4 smoothing capacitors is connected to the DC output of the alternating current circuit. Connect the series connection point of smoothing capacitor 3.4 and one end of the AC input terminal of the rectifier bridge to N ” F E T22
.. 23 is connected to each drain of a series circuit connected in series in opposite directions with the source as a common connection point. Connect a resistor 24, a Zener diode 25, and a low resistor 26 between the DC output terminals. A pace emitter of an NPN transistor 27 is connected to both ends of the resistor 26. The collector of transistor 27 and the positive side of the DC output are connected through a resistor, and the collector of transistor 27 is connected to the gates of FETs 22 and 23. The sources of FETs 22 and 23 are connected to the negative side of the DC output via a resistor 29. next. Let us explain the work of this example. First of all. If the DC output voltage is low and the Zener diode 25 cannot conduct. Since no voltage is generated between the base and emitter of transistor 27, transistor 27 is off. Then... FE
722.23 has a low resistance of 2B between the gate and source. Since it is forward biased through 29. FE722. 23 is conductive, and the connection point of smoothing capacitor 3.4 is connected to one end of the AC input terminal of the rectifier bridge, resulting in voltage double rectification.
The output voltage is approximately twice the peak voltage of the AC voltage. And FET22. 23 is conductive, the source potential becomes the series connection point of smoothing capacitor 3.4, and the gate-source voltage becomes 1/2 of the DC output voltage. still. FE”
r allows current to flow in both directions between the drain and source, and the voltage drop is determined by the on-resistance. For low voltage output, by using elements with low on-resistance, the voltage drop can be made smaller than with a trifle. next. When the output voltage is high (when the Zener diode 25 becomes conductive, current flows into the base of the transistor 27). Transistor 27 becomes conductive. Since the gate and source of FETs 22 and 23 are short-circuited through the resistor 29 and turned off, the series connection point of the smoothing capacitors 3 and 4 and one end of the AC input terminal are disconnected, resulting in bridge rectification, and the DC output voltage is This is approximately the peak voltage. FIG. 2 is a diagram for explaining one embodiment of 41 of the present invention. In the figure, when the DC output voltage is low, the Zener diode 25 is turned off and the transistor 30 is turned off. As a result. No base current is supplied to transistor 3l. Transistor 31 is off. Is there a base for transistor 27 as well? Since l is not supplied. Transistor 27 is also off. As a result. FE722.23
The gate of is forward biased by the resistor 2829 and becomes conductive, and the series connection point of the smoothing capacitor 34 and one end of the AC input terminal are connected. It becomes a voltage doubler rectifier circuit. next. When the DC output voltage increases, the Tsuena diode 25 becomes conductive. By supplying base current to the transistor 30, the transistor 30
Turn on. Then, the base il is connected to the transistor 3l.
Because l flows. Since the transistor 31 is turned on and the base current is supplied to the transistor 27. The transistor 27 is turned on and the gates of the FETs 22 and 23 are short-circuited via the resistor 29. The FET22. 2
3 goes off, bridge! φ replaces lfi. here,
When the transistor 3l becomes conductive. The base fa current flows into the transistor 30 via the resistor 32, and positive feedback is applied.
Then... Even if the DC voltage drops and the Zener diode 25 turns off. Since base current is supplied to transistor 30 through resistor 32, transistor 30 remains conductive and FETs 22 and 23 remain off. Then, the DC output voltage drops significantly. When the voltage drop across resistor 26 drops to the point where transistor 30 can no longer remain conductive, transistor 30 turns off. transistor 31
.. 27 is turned off, and FETs 22 and 23 are conductive. φ is replaced by voltage doubler rectification. Also. The resistance value of the resistor 24 is Rl.
Set the resistance value of tlt resistor 26 to R2. The resistance value of resistor 32 is R3
Let the voltage of the Zener diode 25 be v4, and the base-to-emitter voltage for making the transistor 30 conductive be v5.
If the DC output voltages when the transistor 30 turns on and off are V6 and V7, respectively, v6≧V4+ (R1+R2) V5/112v1;=
(R2+R3)ν5/R2, and by selecting the resistance value so that V6>2V7, even if the AC input voltage changes in an analog manner, chattering will not occur when switching between voltage doubler rectification and bridge rectification. There is no. Note that 33 to 36 have low resistance. FIG. 3 shows another embodiment of the present invention. This example is. In contrast to Figure 2, where N-type FETs 22 and 23 were used. It uses P-type FE737 and 38, and is almost the same as that described in the embodiment shown in FIG. 2, and the same effect can be obtained. 39. 40
is resistance. Figure 4 shows that the DC output voltage is high <. To protect the gate if the breakdown voltage between the gate and source of the FET is exceeded. Gate·
A Zener diode (4l) is connected between the faces. This embodiment is also almost the same as described above, and the same effects can be obtained. [Effects of the Invention] As explained above, according to the present invention, even when the AC input voltage changes in an analog manner. It is possible to switch between voltage doubler and bridge rectification. In addition, the voltage drop is reduced and the drive is simplified. The circuit configuration becomes oil-only, reducing the number of parts. Furthermore. By providing hysteresis characteristics to the detection of the voltage between the DC output terminals. Even if the AC input voltage changes analogously. Eliminates chattering when switching between voltage doubler rectification and bridge rectification. In addition, in the case of triacs, when the temperature is as low as -55°C. However, a significant amount of gate drive ftIIL is required. FET is driven by insulation. It has the advantage of requiring much less driving power than the Triafuku.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を説明するための図,第2図
乃至第4図は夫々本発明の他の一実施例を説明するため
の図.第5図及び第6図は従来例を説明するための図で
ある. l・・・交流fa源     2・・・スイッチ3.4
・・・コンデンサ  5〜8・・・ダイオード9〜l1
・・・抵抗     l2・・・UJTl3・・・抵抗
       l4・・・ツエナダイオードl5・・・
トランジスタ 17・・・抵抗 19〜21・・・抵抗 24・・・抵抗 26・・・抵抗 28. 29・・・抵抗 32〜36・・・抵抗 39. 40・・・抵抗 l6・・・トライアフク l8・・・コンデンサ 22. 23・・・N型FET 25・・・ツェナダイオード 27・・・トランジスタ 30. 31・・・トランジスタ 37. 38・・・P型FET 41・・・ツェナダイオード
FIG. 1 is a diagram for explaining one embodiment of the present invention, and FIGS. 2 to 4 are diagrams for explaining other embodiments of the present invention, respectively. Figures 5 and 6 are diagrams for explaining conventional examples. l...AC fa source 2...switch 3.4
...Capacitor 5-8...Diode 9-l1
...Resistor l2...UJTl3...Resistor l4...Zena diode l5...
Transistor 17... Resistor 19-21... Resistor 24... Resistor 26... Resistor 28. 29...Resistance 32-36...Resistance 39. 40...Resistor l6...Triafuku l8...Capacitor 22. 23... N-type FET 25... Zener diode 27... Transistor 30. 31...Transistor 37. 38...P-type FET 41...Zena diode

Claims (3)

【特許請求の範囲】[Claims] (1)交流電圧を全波整流する整流ブリッジ回路の直流
出力端子間に直列接続された2個の平滑用コンデンサを
接続した整流回路において、 ソースを共通接続点として逆方向に直列に接続されたF
ETの直列接続体の一方のドレインと他方のドレインと
を、夫々上記平滑用コンデンサの接続点と整流ブリッジ
回路の交流入力端子の何れか一方とに接続すると共に、 上記FETの直列接続体の夫々のゲート・ソース間が、
上記直流出力端子間電圧が設定値以上の時逆バイアスさ
れ、設定値以下の時順バイアスされるように接続されて
いることを特徴とする整流回路。
(1) In a rectifier circuit in which two smoothing capacitors are connected in series between the DC output terminals of a rectifier bridge circuit that full-wave rectifies an AC voltage, the two smoothing capacitors are connected in series in opposite directions with the source as a common connection point. F
Connecting one drain and the other drain of the series-connected ET to the connection point of the smoothing capacitor and either one of the AC input terminals of the rectifying bridge circuit, respectively, and connecting each of the series-connected FETs between the gate and source of
A rectifier circuit, characterized in that the rectifier circuit is connected so that it is reverse biased when the voltage between the DC output terminals is above a set value, and is sequentially biased when it is below the set value.
(2)交流電圧を全波整流する整流ブリッジ回路の直流
出力端子間に直列接続された2個の平滑用コンデンサを
接続した整流回路において、 上記直流出力端子間電圧の検出にヒステリシス特性を持
たせたことを特徴とする整流回路。
(2) In a rectifier circuit in which two smoothing capacitors are connected in series between the DC output terminals of a rectifier bridge circuit that full-wave rectifies an AC voltage, a hysteresis characteristic is provided to the detection of the voltage between the DC output terminals. A rectifier circuit characterized by:
(3)請求項第1項記載の整流回路において、上記FE
Tのゲート・ソース間にツェナダイオードを接続したこ
とを特徴とする整流回路。
(3) In the rectifier circuit according to claim 1, the FE
A rectifier circuit characterized in that a Zener diode is connected between the gate and source of a T.
JP11442389A 1989-05-08 1989-05-08 Rectifying circuit Pending JPH02294272A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11442389A JPH02294272A (en) 1989-05-08 1989-05-08 Rectifying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11442389A JPH02294272A (en) 1989-05-08 1989-05-08 Rectifying circuit

Publications (1)

Publication Number Publication Date
JPH02294272A true JPH02294272A (en) 1990-12-05

Family

ID=14637343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11442389A Pending JPH02294272A (en) 1989-05-08 1989-05-08 Rectifying circuit

Country Status (1)

Country Link
JP (1) JPH02294272A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04124890U (en) * 1991-04-30 1992-11-13 新電元工業株式会社 power circuit
JP2002533044A (en) * 1998-12-08 2002-10-02 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Extended input voltage range of switching mode power supply in broadband network

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04124890U (en) * 1991-04-30 1992-11-13 新電元工業株式会社 power circuit
JP2002533044A (en) * 1998-12-08 2002-10-02 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Extended input voltage range of switching mode power supply in broadband network

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