JPH02296409A - Automatic equalizer - Google Patents

Abstract

PURPOSE:To reduce the processing quantity for tap gain operation largely by providing a control means selecting sequentially a tap processing circuit of a group synchronously with a data reception period and adjusting a tap gain of a multiplier. CONSTITUTION:Outputs of an even number tap and an odd number tap are added separately by adders 301, 302 and switches 303a, 303b are selected depending which of the processing systems of the even number tap and the odd number tap is to be used. Outputs of the adders 301, 302 are added by an adder 311 and the result is inputted to a decision device 101. The changeover of the switches 303a, 303b is controlled by a selector 312. The selector 312 is controlled by the result of count of a counter 310. A selector 312 selects w ether an odd or an even number tap circuit via the switches 303a, 303b depending whether a module of 2 of the count of the counter 31 is '0' or '1'.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an automatic equalizer, particularly an automatic equalizer, which has a plurality of delay elements connected in series, and which is connected to each output knob of each delay element and multiplied by a 2-tap gain. The present invention relates to an automatic equalizer having a plurality of tap processing circuits each including a plurality of multipliers that add the outputs of the multipliers and an adder that adds the outputs of the multipliers.

[Prior Art] When high-speed data transmission is performed via an analog communication line (telephone network, etc.), such as in G3 facsimile or computer communication, received data is subject to various deterioration factors of the line5, such as attenuation distortion, delay distortion, etc. be influenced by. Therefore, in order to faithfully reproduce the signal transmitted by the receiver,
It is necessary to correct the above-mentioned distortions. To correct this distortion, equalizers have conventionally been used.

Furthermore, since line distortion is not always constant but varies over time, the equalizer must also follow this.

An equalizer that automatically adjusts the equalization characteristics in accordance with variations in line characteristics is generally called an automatic equalizer (1) and typically uses an adaptive filter.

FIG. 3 shows the configuration of an equalization/judgment section using a conventionally used transversal filter.

In the figure, reference numeral 100 is a transversal filter equalizer,
8-tap delay elements 100a connected in series (the delay time is 1° corresponding to the data baud period); a multiplier 10 that multiplies the tap output of this delay element by a tap gain;
0b, tap gain C-n-CO~ of each multiplier toob
A register 100c that stores Cn (C-4 to CD-C4 in this case), and an adder 2 that adds the outputs of each multiplier.
01.

On the other hand, reference numeral 101 indicates the output ak of the 0 determiner 101, which is a determiner for determining the data transmission point from the equalized output Zk, and the equalized output Zk are input to the subtraction 'l@l01a, and the error signal Ek (equal specification The difference between the output and the determination data point) is formed, and the tap gain of the register 100c is determined based on this error signal Thk.

In addition, in FIG. 3, members indicated by reference numerals 200, 202 and 203 are provided, which will be described later.

Tap gain correction using error signal Ek is generally performed using MSE
It is called the (mean square error) method, and the following formula is used.

α(Yu−A1)2 C(j”=C1a. Bow...+13 is involved, and generally the larger α is, the faster the equalization speed is, but 1
Equalization accuracy decreases.

Expanding the above equation (1) results in the following equation, and FIG. 3 shows a processing system using this equation (2).

Note that such signals are often treated as complex numbers,
All the signals in FIG. 3 are also treated as complex number data.

That is, in FIG. 3, reference numeral 200 is a conjugator that converts the received data of each tap into a complex number, and the conjugated data is multiplied by a convergence coefficient a in a multiplier 202, and then converted into a judgment value in a multiplier 203. It is multiplied by the error signal Ek (Ek=yk-k>) calculated based on Ak, thereby calculating 1a-R'''□(·E) in equation (2).

Furthermore, although detailed illustration is omitted, the tap coefficients C-4 to C-4 of each register lOOc are determined by the output of the multiplier 203.
When controlling C4, the previous tap coefficients C-4 to C
The output of multiplier 203 is subtracted from 4 and the result is stored in each register l00c. As a result, (2) above
The next tap coefficient is determined based on the calculation of the formula.

Through such processing, the equalizer 100 removes the distortion of Daikai No. 8 (performs automatic equalization).

When transmitting data using such an automatic equalizer, so-called training is performed in which both the transmitting and receiving sides transmit known signals for a certain period of time in order to determine equalization characteristics prior to data transmission. During this training period, the isolator is initialized. However, if initialization fails due to poor line conditions, the data transmission speed is reduced (for example, from 9600bps to 7200bps).
S) Retry.

Figures 4 (A) and (B) show the tap gain values at the end of training, respectively. Figure 5 (A) shows the case where the transmission path is an ideal line without fluctuations such as distortion, It has only one peak value, and the others are δ functions (in the figure, the solid line shows the real part of the signal, and the FM line shows the imaginary part).

FIG. 5(B) shows a case where there is distortion in the transmission characteristics of the line, which has a certain peak value, and values that are the opposite characteristics of the line spread to the left and right.

[Problems to be Solved by the Invention] The performance of the automatic equalizer as described above depends on the magnitude of the residual error after complete equalization. The above-mentioned convergence coefficient α is also involved in this, but the number of taps of the isolator is equally involved. This is because the larger the number of taps, the more accurately the inverse characteristic of transmission line distortion can be reproduced. Conversely, if the number of taps is small, it is difficult to reproduce the inverse characteristic, and in the worst case, equalization may become impossible. Therefore, normally, the number of taps of the equalizer is required to be at least 30 to 40 taps.

As mentioned above, the computation of the isolator is very complicated, and the main process 41A of the modem can be said to be the above-mentioned tap gain determination process.

Recently, with the development of LSI technology, modems have also become DS
In many cases, the above processing is executed by software processing using P (digital signal processor).

However, the time for one instruction cycle of a DSP is about 100 ns, so there is a natural limit to the throughput. Therefore, if the number of taps of the equalizer is increased in order to improve the equalization accuracy, the amount of equalization calculation becomes enormous. This necessitates, for example, multiprocessorization, resulting in a problem of increased complexity and size of the device, and increased costs.

An object of the present invention is to solve the above problems and provide an automatic equalizer that can be constructed simply and inexpensively without reducing equalization performance, equalization speed, etc.

[Means for Solving the Problems] In order to solve the above problems, the present invention includes a plurality of delay elements connected in series, and a delay element connected to each tap output of each delay element to multiply the tap gain. In an automatic equalizer having a plurality of tap processing circuits consisting of a plurality of multipliers and an adder that adds the outputs of each multiplier, the plurality of tap processing circuits are divided into a plurality of groups and synchronized with the pig reception cycle. A configuration is adopted in which control means is provided for sequentially selecting tap processing circuits of any of the groups and adjusting the multiplier Φ tap gain.

[Function 1] According to the above configuration, the tap processing circuit of the equalizer is divided into multiple groups, and these are sequentially selected and used in synchronization with data reception. The amount of processing can be greatly reduced.

[Example] Hereinafter, the present invention will be described in detail based on the example shown in the drawings.

FIG. 1 shows the structure of an automatic equalization system employing the present invention. The illustrated configuration is provided within a modem of a data communication device, such as a G3 facsimile. In addition, the first
In the drawings, the same reference numerals are given to the same or corresponding members as in the conventional example, and detailed explanation thereof will be omitted.

In FIG. 1, the symbol to0.101 indicates an equalizer and a determiner having the same configuration as the conventional example shown in FIG. However, in this embodiment, the outputs of the processing systems for even-numbered taps and odd-numbered taps can be added separately by adders 301 and 302 as shown.

Further, a switch 303a determines whether to use the even-numbered tap or odd-numbered tap processing system.

303b allows selection. adder 30
The outputs of 1,302 are added by an adder 311 and then input manually to the determiner 101.

Switching of the switches 303a and 303b is controlled by a selector 312. The selector 312 is controlled by the count result of the counter 310. Specifically, the selector 312 determines whether the modulo of 2 of the count value of the counter 310 is O or 1.
Depending on the configuration, one of the circuits with an even number of taps or a group of taps is selected via the switches 303a and 303b.

The counter 310 has a baud period frequency sporadic: tE ”I'1
The output of 309 is manually generated. Baud periodic frequency generator 30
9 generates a pulse signal in synchronization with the baud of received data.

The above configuration can generally be configured using DSP (digital signal processor) hardware and software. The control and processing described below shall be configured by DSP software unless otherwise specified.

Next, the operation of the above configuration will be explained with reference to the flowchart shown in FIG.

When the received signal Rk arrives in step 51 of FIG. 2, the received data is manually input to the high-quality product 100 in step S2.

At this time, both switches 303a and 303b are activated, and in step S3, the equalized output Yk is obtained by convolution processing similar to the conventional method. In this case, the outputs of even and odd taps are output from adders 301, 302, and 31.
1 and manually inputted to the determiner 101.

In step 84, the equalization result is determined by the determiner lot, and in step S5, the equalized output Yk is input to the determiner lot, and an error signal Ek is output from the 1 determination value Ak.

Next, in step S.6, the output signal of the baud period frequency generator 309 that generates a period corresponding to the baud of the received data is counted by the counter 310.
Determine whether the modulo of 2 in the karantoi direct is 0.

If this step is affirmed, the process proceeds to step S7, and if this step is negative, the process proceeds to step S8.

In step S7, the selector 312 selects an even-numbered tap processing circuit, and in step S8, an odd-numbered tap processing circuit is selected.

After steps S7 to S8, the tap data in the register 100c is updated in step S9 based on the calculations in steps 83 to S4, and then the process moves to step SIO.

In step SlO, it is determined whether or not the received data has been completed, and if the reception has not been completed, the process from step St is repeated.

As described above, during data reception after training, when updating l taps, the tap gain is updated for either even or odd numbers, and this switching between even and odd is performed alternately in synchronization with data reception. .

According to this kind of control, the taps of good quality are divided into two groups of even numbers and odd numbers, and these are used alternately during data reception, so the amount of calculation for updating the tap gain during data reception is reduced. It is 1/2 that of the conventional one, and the burden on the DSP can be reduced.

Therefore, the configuration of the modem in which the automatic modem is adopted does not have to be complicated, and very high-speed hardware is not required, so that the configuration of the device can be made simple and inexpensive. Further, the reduced burden on the DSP can be allocated to other processes such as decoding and error correction, making it possible to provide necessary additional functions.

For example, when the transmission path is a telephone line, the distortion does not vary that much (and the convergence coefficient a normally used in such a transmission path is very small (0).
, 0005), the tap coefficients are also large (in many cases, they do not change). Therefore, sufficient equalization is possible just by alternately updating the even and odd taps as described above.

In the above, the taps of excellent quality are divided into two groups of even numbers and odd numbers, and these are used alternately while receiving data. It is also possible to divide the signal into groups of 3 or 4 or more, and switch the groups used at 3 to 4 or more baud periods.

In addition, in the above embodiment, the delay time T of the unit delay device corresponds to the baud period, but it is also possible to use a superior product such as double sampling that uses a different delay period (Communications Society Communication System Research Material C.
314-23, 1974-05, etc., similar tap group control is possible.

Of course, since the present invention does not restrict the equalization algorithm itself, it can be similarly implemented even when using an equalization algorithm other than the MSE method (such as the ZF method). Moreover, the number of taps is of course not limited to nine taps as shown.

[Effect of the Invention 1 As is clear from the above, the present invention includes a plurality of delay elements connected in series, a plurality of multipliers connected to each tap output of each of the delay elements, and multiplying the tap gain. In an automatic equalizer having a plurality of tap processing circuits consisting of adders that add the outputs of each multiplier, the plurality of tap processing circuits are divided into a plurality of groups, and one of the above-mentioned tap processing circuits is divided into a plurality of groups in synchronization with the data reception cycle. Since the configuration includes a control means that sequentially selects the tap processing circuits of the groups and adjusts the tap gain of the multiplier, it is possible to synchronize the plurality of groups of tap processing circuits of the equalizer with data reception. By selecting and using them sequentially, the processing amount for tap gain calculation can be greatly reduced, and the excellent advantage is that the device can be configured at low cost without reducing equalization performance, equalization speed, etc. be.

[Brief Description of the Drawings] Fig. 1 is a block diagram of the equalizer according to the present invention, Fig. 2 is a flowchart showing the equalization control procedure in the configuration of Fig. 1, and Fig. 3 is a conventional automatic equalizer. The block diagram of the device, FIGS. 4(A) and 4(B) are diagrams showing the tap coefficients of the isostatic device after isostatic death. 100...-Equistop Iota...-Delay element 10
0b--Multiplier 100c...Register 301.
302.311... Adder lot --- Determiner 303a, 303 b --- Switch 309 --- Baud cycle frequency generator 310 --- Counter 12 --- Selector>7←'r--Large/input 〉Sentence 7＼

Claims (1)

[Claims] 1) A plurality of delay elements connected in series, a plurality of multipliers that are connected to each tap output of each delay element and multiply the tap gain, and an addition that adds the outputs of each multiplier. In an automatic equalizer having a plurality of tap processing circuits consisting of a plurality of tap processing circuits, the plurality of tap processing circuits are divided into a plurality of groups, and the tap processing circuits of any of the groups are sequentially selected in synchronization with a data reception cycle. An automatic equalizer comprising control means for adjusting the tap gain of the multiplier.