JPH0229716Y2 - - Google Patents
Info
- Publication number
- JPH0229716Y2 JPH0229716Y2 JP1982053406U JP5340682U JPH0229716Y2 JP H0229716 Y2 JPH0229716 Y2 JP H0229716Y2 JP 1982053406 U JP1982053406 U JP 1982053406U JP 5340682 U JP5340682 U JP 5340682U JP H0229716 Y2 JPH0229716 Y2 JP H0229716Y2
- Authority
- JP
- Japan
- Prior art keywords
- pin
- hole
- capacitor
- pins
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【考案の詳細な説明】
〈産業上の利用分野〉
この考案は、フイルタ機能を備えたピンコネク
ターとして使用する積層貫通型コンデンサに関す
るものである。[Detailed Description of the Invention] <Industrial Application Field> This invention relates to a multilayer capacitor used as a pin connector with a filter function.
〈従来の技術〉
各種電気回路の接続に使用されるピンコネクタ
ーは、ピンの一方端部に入力側端子を、他方に中
継端子を各々接続するものであるが、ピン部分の
シールドが充分でないと、出力側にノイズが発生
することになる。<Prior art> Pin connectors used to connect various electrical circuits connect an input terminal to one end of the pin and a relay terminal to the other end, but if the pin part is not sufficiently shielded, , noise will be generated on the output side.
このため、従来のピンコネクターには、第1図
に示すように、パイプ状のコンデンサ1を用いて
ピン2に外嵌挿し、コンデンサ1の一方の容量電
極3をピン2と、外面に施した他方の容量電極で
あるアース電極4を外装ケース等を利用したアー
ス5と各々接続し、、ピン2に生じた高周波をア
ース5に流してノイズの発生を防止するようにし
た貫通型コンデンサが使用されている。 For this reason, in conventional pin connectors, as shown in Fig. 1, a pipe-shaped capacitor 1 is used, the capacitor 1 is fitted onto the pin 2, and one capacitor electrode 3 of the capacitor 1 is attached to the pin 2, and the capacitor 1 is attached to the outside of the pin 2. A feed-through capacitor is used in which the ground electrode 4, which is the other capacitive electrode, is connected to the ground 5 using an external case, etc., and the high frequency generated at pin 2 is passed to the ground 5 to prevent the generation of noise. has been done.
ところで、上記のような円筒形の貫通コンデン
サを、多数本のピンを備えたコネクターに使用し
た場合、ピンの本数に応じたコンデンサが必要に
なり、各ピンに対して個々に取付けを行なわなけ
ればならないため、組立工程が煩雑になると共
に、多数のコンデンサを集合させるために、コネ
クタの寸法および重量が大きくなり、加えて製作
コストも高くなるという問題がある。 By the way, when a cylindrical feed-through capacitor like the one above is used in a connector with many pins, capacitors corresponding to the number of pins are required, and they must be attached to each pin individually. As a result, the assembly process becomes complicated, and since a large number of capacitors are assembled, the size and weight of the connector become large, and in addition, the manufacturing cost becomes high.
〈考案が解決しようとする課題〉
この考案は上記のような問題点を解決するため
になされたものであり、多数のピンを備えたコネ
クタの組立工程を簡略化し、小型で安価なコネク
タを構成できる積層貫通型コンデンサブロツクを
提供することを目的とする。<Problems to be solved by the invention> This invention was made to solve the problems mentioned above. It simplifies the assembly process of a connector with a large number of pins, and constructs a small and inexpensive connector. The purpose of the present invention is to provide a through-layer capacitor block that can be used.
〈課題を解決するための手段〉
この考案の構成は、ピンの貫通孔を設けた積層
基板の内部にアース電極を貫通孔と接触しないよ
うに上下に設け、積層基板の対向する両表面に前
記アース電極との間で容量を形成するための容量
電極を設けてピンと短絡させ、多数本のピンを一
体に接続できるようにしたものである。<Means for Solving the Problems> The configuration of this invention is that ground electrodes are provided above and below the inside of a laminated substrate provided with pin through holes so as not to come into contact with the through holes, and the ground electrodes are provided on both opposing surfaces of the laminated substrate. A capacitive electrode is provided to form a capacitance with the ground electrode and short-circuited with the pin, allowing multiple pins to be connected together.
〈実施例〉
以下、この考案の一実施例を添付図面の第2図
乃至第5図にもとづいて説明する。<Embodiment> Hereinafter, an embodiment of this invention will be described based on FIGS. 2 to 5 of the accompanying drawings.
図示のように、積層基板11は、各種誘電体、
例えばセラミツクを積層して長方形のブロツク状
に形成され、その長手方向に沿う両側の部分に、
多数のピン貫通孔12が各々一定の間隔で並べて
設けられている。 As illustrated, the laminated substrate 11 includes various dielectric materials,
For example, a rectangular block is formed by laminating ceramics, and on both sides along the longitudinal direction,
A large number of pin through holes 12 are arranged side by side at regular intervals.
上記積層基板11の内部で長手方向に沿う両側
の位置に、ピン貫通孔12の並列方向に沿つて連
続するアース電極A,Bが適宜手段を用いて埋設
されている。 Ground electrodes A and B, which are continuous along the parallel direction of the pin through holes 12, are buried at positions on both sides along the longitudinal direction inside the laminated substrate 11 using appropriate means.
このアース電極A,Bは第3図のように貫通孔
12に臨む内側の端縁が貫通孔12と適当な距離
を保ち、貫通孔12と接触しないようにすると共
に、外側の端縁は積層基板11の外周面に達する
ように形成され、積層基板11の外周部には、ア
ース電極A,Bと接続した外部端子C,Cが設け
られている。 As shown in FIG. 3, the ground electrodes A and B are made such that the inner edges facing the through hole 12 maintain an appropriate distance from the through hole 12 and do not come into contact with the through hole 12, and the outer edges are laminated. External terminals C and C are formed so as to reach the outer circumferential surface of the substrate 11, and are connected to the ground electrodes A and B on the outer circumferential portion of the laminated substrate 11.
上記積層基板11の上下表面で各貫通孔12を
設けた位置にそれぞれ短冊状の容量電極D,Eが
積層基板11の一部を挟んでアース電極A,Bと
対向するように設けられている。 At the positions where each through hole 12 is provided on the upper and lower surfaces of the laminated substrate 11, strip-shaped capacitive electrodes D and E are provided so as to face the ground electrodes A and B with a part of the laminated substrate 11 sandwiched therebetween. .
図示の場合容量電極D,Eは一方の端部を貫通
孔12の端部に臨ませるようにしたが、例えば貫
通孔12よりも広幅に形成し、貫通孔12の端部
を囲むようにしても良い。 In the illustrated case, the capacitor electrodes D and E have one end facing the end of the through hole 12, but they may be formed wider than the through hole 12 and surround the end of the through hole 12, for example. .
前記積層基板11の各貫通孔12に接続用のピ
ン13が挿入されると、ピン13は上下の表面に
設けられた容量電極D,Eと半田付等の手段で接
続され、短絡される。 When the connecting pins 13 are inserted into each through hole 12 of the laminated substrate 11, the pins 13 are connected to the capacitive electrodes D and E provided on the upper and lower surfaces by means such as soldering, and are short-circuited.
図示の場合、ピンの取付け数は積層基板11の
両側で5本づつ計十本を取付ける例を示したが、
ピンの本数は図示に限定されるものではなく、必
要に応じて本数を自由に増減すればよく、基板1
1の形状も矩形に限定されるものではない。 In the case shown in the figure, the number of pins attached is five on each side of the laminated board 11, for a total of ten pins.
The number of pins is not limited to what is shown in the diagram, and can be freely increased or decreased as necessary.
The shape of 1 is not limited to a rectangle either.
上記実施例のコンデンサブロツクは、内部にア
ース電極A,Bと表面に容量電極D,Eが設けら
れた積層基板11にピン13の貫通孔12を形成
し、積層基板11の外周にアース電極A,Bと導
通する外部電極Cを設けることにより、第2図に
示すようなコンデンサブロツクができ上がる。 In the capacitor block of the above embodiment, a through hole 12 for a pin 13 is formed in a laminated substrate 11 provided with ground electrodes A and B inside and capacitive electrodes D and E on the surface, and a through hole 12 for a pin 13 is formed on the outer periphery of the laminated substrate 11. , B is provided, thereby creating a capacitor block as shown in FIG.
このコンデンサブロツクの各貫通孔12にピン
13を挿通し、ピン13と容量電極D,Eを半田
付等によつて導通短絡させれば、第5図に示す回
路のような多ピンコネクタが構成される。 By inserting pins 13 into each through hole 12 of this capacitor block and short-circuiting pins 13 and capacitor electrodes D and E by soldering or the like, a multi-pin connector as shown in the circuit shown in FIG. 5 is constructed. be done.
第5図に示す回路図は、コンデンサブロツクの
第4図の断面の等価回路であり、容量電極D1,
D2,D3,D4,D5,E1,E2,E3,E4,E5,は同一
積層基板11内にあり、それぞれの組合わせD1
とE1,D2とE2,D3とE3,D4とE4,D5とE5は互に
各々のピン13を介して導通状態にあり、各容量
電極D1乃至D5,E1乃至E5は、それぞれ共通のア
ース電極A,Bとの間にコンデンサを形成する。 The circuit diagram shown in FIG. 5 is an equivalent circuit of the cross section of the capacitor block shown in FIG .
D 2 , D 3 , D 4 , D 5 , E 1 , E 2 , E 3 , E 4 , E 5 , are in the same multilayer substrate 11, and the respective combinations D 1
and E 1 , D 2 and E 2 , D 3 and E 3 , D 4 and E 4 , and D 5 and E 5 are in a conductive state with each other through their respective pins 13, and each capacitor electrode D 1 to D 5 , E 1 to E 5 form a capacitor between the common ground electrodes A and B, respectively.
〈考案の効果〉
以上のように、この考案によると、ピンの貫通
孔が設けられた積層基板の内部にアース電極を貫
通孔と接触しないように設け、積層基板の表面に
貫通孔へ挿通したピンと短絡させる容量電極を設
け、さらにアース電極が積層基板の中で上下に設
けられているため、π型の回路を形成しているの
で、多数本ピンコネクタ用のコンデンサを一つの
積層基板にまとめることができ、しかも、貫通孔
にピンを挿入するだけでピンコネクタを構成で
き、組立工程が簡略化し、全体の寸法および重量
を小さくすることができると共に、組立および材
料コストの低減を図ることができる。<Effects of the invention> As described above, according to this invention, the ground electrode is provided inside the laminated board in which the pin through-hole is provided so as not to come into contact with the through-hole, and the earth electrode is inserted into the through-hole on the surface of the laminated board. Capacitive electrodes are provided to short-circuit with the pins, and ground electrodes are provided above and below the multilayer board, forming a π-shaped circuit, so capacitors for multiple pin connectors can be combined into one multilayer board. Moreover, a pin connector can be constructed by simply inserting a pin into a through hole, which simplifies the assembly process, reduces overall size and weight, and reduces assembly and material costs. can.
さらに、π型回路構成により、通常の貫通型コ
ンデンサよりもノイズ除去効果を向上させた貫通
コンデンサを構成することができる。 Furthermore, the π-type circuit configuration makes it possible to configure a feedthrough capacitor that has a better noise removal effect than a normal feedthrough capacitor.
また、積層基板の形状に制約がなく、必要に応
じ種々の形状に仕上げることができる。 Further, there are no restrictions on the shape of the laminated substrate, and it can be finished into various shapes as necessary.
ちなみに、この考案のコンデンサブロツクの取
得静電容量は、サイズ、定格電圧により変わる
が、10pFから1NFのものが取得可能である。 By the way, the capacitance of the capacitor block of this invention varies depending on the size and rated voltage, but it is possible to obtain a capacitance of 10pF to 1NF.
第1図は従来のコンデンサブロツクを示す縦断
面図、第2図はこの考案に係るコンデンサブロツ
クの斜視図、第3図は同平面図、第4図は同上の
縦断面図、第5図は同上の等価回路図である。
11……基板、12……貫通孔、13……ピ
ン、A,B……アース電極、C……外部電極、
D,E……容量電極。
Fig. 1 is a longitudinal sectional view showing a conventional capacitor block, Fig. 2 is a perspective view of the capacitor block according to this invention, Fig. 3 is a plan view of the same, Fig. 4 is a longitudinal sectional view of the same, and Fig. 5 is a longitudinal sectional view of the same. It is an equivalent circuit diagram same as the above. 11...Substrate, 12...Through hole, 13...Pin, A, B...Earth electrode, C...External electrode,
D, E...capacitive electrodes.
Claims (1)
にアース電極を孔と接触しないように上下に設
け、この積層基板の対向する両表面にアース電極
との間で容量を構成する複数の容量電極を設け、
孔を貫通するピンと容量電極を短絡させることが
できるようにしたことを特徴とする積層貫通型コ
ンデンサブロツク。 Ground electrodes are provided above and below the inside of a laminated board in which a hole through which a pin is formed so as not to come into contact with the hole, and a plurality of capacitive electrodes forming a capacitance with the ground electrode are provided on both opposing surfaces of this laminated board. established,
A through-layer capacitor block characterized in that a pin passing through a hole and a capacitor electrode can be short-circuited.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5340682U JPS58155826U (en) | 1982-04-12 | 1982-04-12 | Through-layer capacitor block |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5340682U JPS58155826U (en) | 1982-04-12 | 1982-04-12 | Through-layer capacitor block |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58155826U JPS58155826U (en) | 1983-10-18 |
| JPH0229716Y2 true JPH0229716Y2 (en) | 1990-08-09 |
Family
ID=30064073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5340682U Granted JPS58155826U (en) | 1982-04-12 | 1982-04-12 | Through-layer capacitor block |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58155826U (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5325175U (en) * | 1976-08-10 | 1978-03-03 |
-
1982
- 1982-04-12 JP JP5340682U patent/JPS58155826U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58155826U (en) | 1983-10-18 |
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