JPH0229729Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a shot barrier semiconductor device with high breakdown voltage and high reliability.

Schottky barrier semiconductor devices have low forward voltage;
Although it had the feature of low power loss in the forward direction, it had the drawback of low breakdown voltage in the reverse direction.
Therefore, attempts have been made to increase the breakdown voltage by creating a guard ring structure, a field plate structure, or the like. However, the guard ring structure only reduces the reverse current at the periphery of the metal-semiconductor contact, but cannot reduce the reverse current at the center of the metal-semiconductor contact. The field plate structure also improves the characteristics of the periphery of the metal-semiconductor contact. Therefore, in either structure, it was not possible to significantly increase the breakdown voltage of the shot barrier semiconductor device.

In order to solve the above-mentioned drawbacks, the applicant of the present application proposed in Japanese Patent Application No. 50-100896 (Japanese Unexamined Patent Publication No. 52-24465) that the reverse current is reduced by a space charge region based on the reverse bias of the pn junction. We proposed a shot barrier semiconductor device with high voltage resistance. However, a method for further increasing the voltage resistance and reliability is not disclosed.

Therefore, an object of the present invention is to provide a shot barrier semiconductor device that can further improve reverse breakdown voltage, reliability, and forward characteristics by utilizing the invention of Japanese Patent Application No. 100896/1982. .

The present invention for achieving the above object includes: a first semiconductor layer having a first conductivity type of n-type or p-type and having a high impurity concentration; a second semiconductor layer formed on the first semiconductor layer having an impurity concentration lower than that of the semiconductor layer; and an impurity of the second semiconductor layer having the first conductivity type. a third semiconductor layer having an impurity concentration lower than that of the second semiconductor layer and having an upper surface exposed to the surface of the semiconductor substrate; The semiconductor layer is exposed, a lower surface thereof is adjacent to the second semiconductor layer, a side surface thereof is adjacent to the third semiconductor layer, and the semiconductor layer is formed deeper than the third semiconductor layer; a fourth semiconductor layer having a second conductivity type opposite to the first conductivity type and in contact with the third semiconductor layer to form a shot barrier and with respect to the fourth semiconductor layer; and a metal layer in contact with the semiconductor substrate so as to form an ohmic contact, and the shot barrier and the ohmic contact are arranged alternately on a straight line in a specific direction on the surface of the semiconductor substrate. The present invention relates to a shot barrier semiconductor device characterized in that a fourth semiconductor layer is arranged.

According to the above idea, since the third semiconductor layer is provided to lower the impurity concentration directly under the shottock barrier, the space charge region spreading from the fourth semiconductor layer can easily spread to the bottom of the shottock barrier, and the fourth semiconductor layer is provided. As a result, the effect of improving reverse characteristics (reduction in reverse current, higher breakdown voltage) becomes even more remarkable. In particular, since the third semiconductor layer is formed shallower than the fourth semiconductor layer, the space charge region spreading from the fourth semiconductor layer tends to spread to the bottom of the shot barrier, but the space charge region spreads from the fourth semiconductor layer to the bottom of the fourth semiconductor layer. It is more difficult to spread than this. Therefore, the reverse voltage value at which the space charge region spreading from the fourth semiconductor layer reaches the first semiconductor layer and causes reach-through breakdown is lower than the third semiconductor layer.
This does not occur due to the provision of the semiconductor layer. In other words, it is not necessary to make the second semiconductor layer thicker in order to prevent a decrease in breakdown voltage due to a decrease in reverse voltage value that causes reach-through breakdown, and by making the second semiconductor layer thicker, the series resistance increases and the The disadvantage of increased voltage does not occur. Moreover, since the third semiconductor layer, which is the region with the highest resistance, is formed to be relatively shallow, the structure is reasonable in this respect as well to suppress an increase in forward voltage.

Next, a shot barrier semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

The shot barrier semiconductor device shown in FIG.
A second semiconductor layer 2 made of an n ^- type silicon epitaxial layer is formed on a first semiconductor layer 1 made of an n + type (first conductivity type) silicon substrate,
Furthermore, impurity compensation can be achieved by implanting B ⁺ ions at 3×10 ¹¹ /cm ² from the surface of the second semiconductor layer 2.
Forming an n ^- type third semiconductor layer 3, and then
A p ⁺ type (second conductivity type) fourth semiconductor layer 4 is formed in a striped pattern, and Cr is used to obtain a shot barrier.
The metal layer 5 was formed by vapor-depositing the metal to a thickness of about 2000 Å, and then the metal layer 5 was formed by successively vapor-depositing Ag and Ni, and the lower electrode metal layer 6 was also formed. In addition, 7 is approximately
7000 Å SiO ₂ layer, 8 is a p ⁺ type guard ring semiconductor layer.

Showing the impurity concentration of each layer, the first semiconductor layer 1
is approximately 5×10 ¹⁹ /cm ³ , and the second semiconductor layer 2 is approximately 4×
10 ¹⁵ /cm ³ , the third semiconductor layer 3 has an impurity concentration of 1×10 ¹⁵ /cm ³ (after compensation), and the fourth semiconductor layer 4 has an impurity concentration of about 6×10 ¹⁸ /cm ³ . Also, the depth from the top surface of the semiconductor (electrode surface) to the bottom end of the second semiconductor layer 2 is approximately
10μ, the depth of the p ⁺ type fourth semiconductor layer 4 is approximately 2μ, and the depth of the third semiconductor layer 3 is approximately 2μ.
It is formed even more shallowly than the Further, the width of the p ⁺ type fourth semiconductor layer 4 is approximately 6μ, and the width of the n ⁻ type third semiconductor layer 3 between the fourth semiconductor layers 4 is approximately
It is 10μ.

When a positive voltage is applied to the upper electrode metal layer 5 of the shot barrier semiconductor device configured as shown in FIG. 1 to create a forward bias state, the metal layer 5, the third semiconductor layer 3, and the second semiconductor layer 2 , a forward current flows through the path between the first semiconductor layer 1 and the lower metal layer 6.
On the other hand, if, for example, -30V is applied to the upper metal layer 5 to create a reverse bias state, the state between the p ⁺ type fourth semiconductor layer 4 and the n ^- type third semiconductor layer 3 is reverse biased. Therefore, the space charge region, that is, the depletion layer is n ^- with a width of about 5.1 μ from the p ⁺ type fourth semiconductor layer 4.
spreads into the third semiconductor layer 3 of the mold. Since depletion layers extend from both sides of the n ^- type third semiconductor layer 3, the surface of the n ^- type third semiconductor layer 3 is eventually filled with the depletion layer due to the -30V reverse voltage. . As a result, the reverse current flowing through the metal layer 5 and the n ^- type third semiconductor layer 3 is significantly restricted.
The depletion layer extending to the n-type second semiconductor layer 2 directly under the p ⁺ -type fourth semiconductor layer 4 is smaller than the spread width of the third semiconductor layer 3 due to the difference in impurity concentration, causing reach-through breakdown. There is still plenty of room left. We have just described the case where the n ^- type third semiconductor layer 3 is filled with a depletion layer with a reverse bias of -30V.
In the case of a low reverse voltage, the third semiconductor layer 3 is not filled with a depletion layer. However, since it is difficult for reverse current to flow in the region where the depletion layer is formed, the reverse current is suppressed by the amount of the depletion layer. Furthermore, since the area of the shot barrier in the reverse direction is reduced by the extent to which the depletion layer is expanded, the probability of the existence of factors such as crystal defects that deteriorate the reverse direction characteristics is lowered, and reliability is improved. The area ratio of the depletion layer on the surface of the n ^- type third semiconductor layer 3 is preferably 50% or more, and more preferably 80% or more.

As is clear from the above, according to this example,
Since the n ^- type third semiconductor layer 3 is provided, the depletion layer expands in the lateral direction. Therefore, p ⁺
It becomes possible to increase the mutual spacing between the n ^- type fourth semiconductor layers 4, that is, the width of the n-type third semiconductor layer 3, and as a result of this type of shot barrier semiconductor device, the area of the shot barrier portion becomes larger and the current flow increases. Large capacity can be obtained. In other words, a desired current capacity can be obtained with a small semiconductor chip. Therefore, it is possible to provide a shot barrier semiconductor device with good characteristics in both the reverse direction and the forward direction.

Furthermore, since the third semiconductor layer 3 is formed by ion implantation, it is possible to form it extremely shallowly. Therefore, the forward current can be reduced while maintaining good forward characteristics.

Although the embodiments of the present invention have been described above, the present invention is not limited thereto and can be further modified. For example, the third semiconductor layer 3 may be formed of an n ^- type epitaxial growth layer. Also,
The planar shapes of the third and fourth semiconductor layers 3 and 4 are
It may be modified as shown in the figure or FIG.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a part of a shot barrier semiconductor device according to an embodiment of the present invention, and FIG. 2 is a plan view showing the surface of the semiconductor portion of the device shown in FIG. 3 and 4 are plan views showing a shot barrier semiconductor device according to a modified example of the present invention. In the symbols used in the drawings, 1 is the first semiconductor layer, 2 is the second semiconductor layer, 3 is the third semiconductor layer, 4 is the fourth semiconductor layer, and 5 is the metal layer. .

Claims (1)

[Claims for Utility Model Registration] A first semiconductor layer having a first conductivity type of n-type or p-type and having a high impurity concentration; a second semiconductor layer formed on the first semiconductor layer having an impurity concentration lower than the impurity concentration; and a second semiconductor layer having the first conductivity type and having an impurity concentration lower than the impurity concentration of the second semiconductor layer. a third semiconductor layer having a low impurity concentration and formed on the second semiconductor layer, the upper surface of which is exposed to the surface of the semiconductor substrate; the upper surface of which is exposed to the surface of the semiconductor substrate; The lower surface is adjacent to the second semiconductor layer, the third semiconductor layer is adjacent to the side surface thereof, and is formed deeper than the third semiconductor layer, and the first conductive layer is formed deeper than the third semiconductor layer. a fourth semiconductor layer having a second conductivity type opposite to that of the semiconductor layer; and a fourth semiconductor layer in contact with the third semiconductor layer to form a shot barrier and in ohmic contact with the fourth semiconductor layer. and a metal layer in contact to form a contact, and the third and fourth contacts are arranged such that the shot barrier and the ohmic contact are alternately arranged on a straight line in a specific direction on the surface of the semiconductor substrate. A shot barrier semiconductor device characterized in that a semiconductor layer is arranged.