JPH02297653A - Information processor - Google Patents

Abstract

PURPOSE:To improve a speed for transferring data by separately providing a hardware to detect the write cycle of a processor and to count the write cycle when the data are transferred. CONSTITUTION:An OR circuit 105 to detect the write cycle from a processor 101, a counter 103 to inform the processor 101 that the write cycle is counted up to a set value, a counter enable register 104, an address decoder 102 to access the counter 103 and counter enable register 104 from the processor 101 are provided as a hardware circuit. Thus, since the write cycle is detected and counted by the hardware separate from the processor 101 when the data are transferred, the speed is improved for transferring the data.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is used for information processing. The present invention relates to speeding up data transfer by a processor or the like involved in information processing.

〔overview〕

In an information processing device equipped with a processor that performs data transfer processing, the present invention is capable of speeding up data transfer by separately providing hardware that detects write cycles of the processor during data transfer and counts the write cycles. This is what I did.

[Conventional technology]

In information processing, data transfer is frequently performed, and speeding up data transfer leads to improved information processing performance.

Conventionally, data transfer by a processor or the like has been performed using a processing procedure as shown in Figure 3. The purpose of this processing procedure is to transfer count data from the address pointed to by address register Am to the address pointed to by address register An. First, the contents of the address pointed to by Am are transferred to the address pointed to by An. Transfer the data to the pointed address, then increment the value of Am and the value of An (step 201), and then reduce the count by 1 (step 201). If the count is not 0, return to step 201, and the count is If it is O, the data transfer has been completed, so the process ends (step 203).

(+ in (Am)+ in FIG. 4 means post-increment).

Generally, the data transfer unit is 1 byte, 2 bytes, or 4 bytes, and the incremented value differs depending on the transfer unit. That is, if it is 1 byte, the incremented value is 1, and if it is 2 bytes, it is 2.4 bytes, it is 4.

Figure 4 conceptually shows this process, showing the memory space, starting from the address pointed to by Am and counting
This indicates that t worth of data is to be transferred to the address pointed to by An.

[Problem that the invention seeks to solve]

The above-described conventional data transfer has the disadvantage that data transfer cannot be made faster because the count is decremented by 1 each time data is transferred to determine the termination condition.

The present invention aims to eliminate such drawbacks and to provide a device that can speed up data transfer.

[Means for solving problems]

The present invention provides an information processing device equipped with a processor that executes data transfer processing, a means for detecting write cycles from the processor, and a timer for counting the write cycles detected by the detecting means up to a set value. A counter that notifies the processor, a counter enable register that enables the counter, and an address decoder that makes the counter and the counter enable register accessible from the processor are provided as hardware circuits separately from the processor. It is characterized by

[Effect]

In data transfer processing, a count number is set in the counter and 1 is written in the counter enable register to enable the counter. After that, each write cycle counts down by one. Next, data is transferred from the transfer source address to the transfer destination address, both address values are incremented, and this process is repeated. After the necessary data transfer has been performed, when another data transfer is attempted, the counter underflows and outputs a bus error signal to the processor.

When a bus error signal is sent to the processor, data transfer is interrupted and bus error handling is performed.

In this bus error processing, it is determined whether it is a true bus error or a counter underflow. If it is a bus error, bus error processing is performed, and if it is a counter underflow, the counter enable register is cleared and data transfer is started. Return control to the processing that was being performed.

In this way, by detecting write cycles during data transfer using hardware separate from the processor and counting the write cycles, it is possible to speed up data transfer.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In the embodiment of the present invention, an information processing apparatus equipped with a processor 101 that executes data transfer processing includes an OR circuit 105 that detects a write cycle from the processor 101, and a write cycle detected and notified by the OR circuit 105. The processor 101 counts up to the set value.
a counter 103 that notifies the user; a counter enable register 104 that enables the counter 103;
Counter 101 and counter enable register 10
An address decoder 102 that allows the processor 101 to access the address decoder 102 is provided as a hardware circuit separately from the processor 101.

The counter 103 counts down every time a write cycle of the processor 101 occurs, and becomes disabled as a counter when it underflows.

The processor 101 is connected to an address strobe signal line 108 in which the address bus becomes valid when the address bus 106.7'-tabus 107.0 is active, a read/write signal line 109 that indicates 1 for read and 0 for write, and the processor 101. It is connected to a control line 110 including an acknowledge signal line for sending out an acknowledge signal.

7) The L/S decoder 102 is connected to the address bus 106, the address strobe signal line 108, and the control line 110, and is further connected to the counter enable register 104 via the register select signal line 111, which is enabled when the processor 101 accesses the counter enable register 104. The processor 101 is connected to the enable register 104 and the counter 10
It is connected to the counter 103 via a counter select signal line 112 that becomes valid when accessing the counter 3.

The counter 103 is connected to a data bus 107, a read/write signal line 109, and an enable signal line 11.
3 to the counter enable register 104, and is connected to the OR circuit 105 via a signal line 114 that becomes 0 during a write cycle of the processor and becomes 1 at other times to send a clock to the counter 103. When the count set by the processor 101 is exceeded (it actually underflows because it is assumed to be a down counter), data is transferred for the count, and is output to the bus error of the processor 101 to notify the end. The processor 1 is connected to the
Connected to 01.

The counter enable register 104 is connected to the data bus 107.
, and read/write signal line 109, and OR circuit 105 is connected to address strobe signal line 108 and read/write signal line 109.

Next, the operation of the embodiment of the present invention configured as described above will be explained. The operation is similar to the conventional example, as shown in FIG.
A process is performed to transfer the data for unt to the address pointed to by the address register An.

FIG. 2(a) is a flowchart showing the flow of data transfer processing according to the embodiment of the present invention. First, the J runt number is set in the counter 103, and 1 is written in the counter enable register 104 to enable the counter 103. Thereafter, the counter 103 counts down by one each time there is a write cycle (step 4G1).

Next, the contents of the address pointed to by address register Am are transferred to the address pointed to by address register An, and then the values of Am and An are incremented (step 402).

After that, this process is repeated.

In the conventional processing flowchart shown in FIG. 3, the software counts down and determines whether it is 0 before jumping, but in FIG. 2(a), the jump is made unconditionally at step 402. Instead, in order to count by hardware, a count number is set in the counter 103 in step 401, and the counter 103 is enabled.

Next, the operation of the hardware at step 402 will be explained. Since the counter 103 is enabled, it is counted down every time a write cycle occurs (every time the contents of the address pointed to by Am are transferred to the address pointed to by An), and this loop continues at step 402. When the necessary data transfer is performed in step 402 and another data transfer is attempted, the counter 103 underflows and outputs a bus error signal to the processor 101.

In other words, even if the necessary data transfer is completed, step 40
2 tries to transfer data further, so the counter 103 prevents it. At this time, the counter 103 remains underflow and is disabled.

FIG. 2 (5) shows that the signal 115 is sent to the processor 101 after the counted data has been transferred in the bus error processing routine.
3 is a flowchart showing the flow of processing performed when a bus error occurs. When a bus error enters processor 101,
The previous data transfer is interrupted and control of the processor 101 is transferred to the bus error handling routine.

At this time, the address of the instruction attempting to transfer data is saved on the stack as in normal processing.

In the bus error processing routine, it is first checked whether it is a real bus error or a counter underflow (step 403). If the counter underflows, it is a true bus error, so temporary bus error processing is performed (step 404). Here, description of step 404, which is normal bus error processing, will be omitted. If the counter underflows, the counter enable register 104 is cleared (step 405). This is done so that the counter can be enabled the next time the data is transferred.

The address of the instruction attempting to transfer data is saved on the stack. Since the necessary data has already been transferred, this command itself must not be executed.

Therefore, in order to return to the instruction next to this instruction, jump to the next address of the instruction (step 40).
6).

〔Effect of the invention〕

As described above, according to the present invention, by detecting write cycles during data transfer and counting the write cycles using hardware, it is possible to speed up data transfer with a slight increase in hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIGS. 2(a) and 2(a) are flowcharts showing the flow of data transfer in the embodiment of the present invention. FIG. 3 is a flowchart showing the flow of data transfer in a conventional example. FIG. 4 is a diagram showing the concept of an example of data transfer. 101... Processor, 102... Address decoder, 103... Counter, 104... Counter enable register, 105... OR circuit, 106...
・Address bus, 107...Data bus, 108...
・Address strobe signal line, 109...Read/write signal line, 110...Other control lines, 111...
- Register select signal line, 112... Counter select signal line, 113... Counter enable signal line,
114... Clock signal line to counter, 115...
・Signal line that notifies that the counted amount of data transfer has finished.

Claims (1)

[Scope of Claims] 1. In an information processing device equipped with a processor that executes data transfer processing, means for detecting write cycles from the processor, and counting the write cycles detected by the detecting means up to a set value. A counter that notifies the processor when the counter is activated, a counter enable register that enables the counter, and an address decoder that makes the counter and the counter enable register accessible from the processor as hardware circuits separate from the processor. An information processing device characterized by: