JPH02298036A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02298036A JPH02298036A JP11980389A JP11980389A JPH02298036A JP H02298036 A JPH02298036 A JP H02298036A JP 11980389 A JP11980389 A JP 11980389A JP 11980389 A JP11980389 A JP 11980389A JP H02298036 A JPH02298036 A JP H02298036A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- plating
- resin
- resin film
- grinding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000007747 plating Methods 0.000 claims abstract description 23
- 239000011347 resin Substances 0.000 claims abstract description 20
- 229920005989 resin Polymers 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 19
- 230000002093 peripheral effect Effects 0.000 claims abstract description 6
- 210000000078 claw Anatomy 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 238000010894 electron beam technology Methods 0.000 abstract description 2
- 239000007788 liquid Substances 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 36
- 238000005336 cracking Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に半導体ウェ
ーハにバンプを形成し、かつ裏面の研削を行なう工程を
有する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that includes a step of forming bumps on a semiconductor wafer and grinding the back surface.
従来よりLSIの実装密度を上げる方法としてTAB
(テープ・オートメーテツド・ボンディング)方式が有
り、半導体ウェーハ(以下単につ工−ハという)にバン
プを形成する工程と、裏面を研削する工程を有している
。TAB is a method to increase the packaging density of LSI than before.
There is a (tape automated bonding) method, which includes a step of forming bumps on a semiconductor wafer (hereinafter simply referred to as a wafer) and a step of grinding the back surface.
従来の半導体装置の製造方法において、バンプの形成の
ためのめつき工程でウェーハの裏面周辺に金や銅の電極
金属がまわり込んで付いてしまい、刃物等で削っても柔
かい為完全には除去できず後工程の裏面研削にて、残っ
ている金属により研削ブレードが目詰りしウェーハの割
れる事故が時折発生していた。又裏面を削る量の多いも
の(ウェーハ径や研削量の大きいもの)程割れの発生率
が高くなっていた。第1図に研削量と割れ発生率の関係
をO印で示す。In conventional semiconductor device manufacturing methods, gold and copper electrode metals wrap around the backside of the wafer during the plating process to form bumps, and are difficult to completely remove because they are soft even when scraped with a knife. However, during back grinding in the subsequent process, the grinding blade would become clogged with the remaining metal, resulting in occasional accidents resulting in cracked wafers. In addition, the more the back surface was ground (the larger the wafer diameter and the larger the amount of grinding), the higher the incidence of cracking was. In Figure 1, the relationship between the amount of grinding and the crack occurrence rate is shown by O.
(課題を解決するための手段〕
本発明の半導体装置の製造方法は、半導体ウェーハの表
面にバンプを形成するためのめっき用のマスクを設ける
工程と、前記マスク形成の前又は後に前記半導体ウェー
ハの周辺部に樹脂を塗布したのちにめっき法によりバン
プを形成する工程と、前記半導体ウェーハの裏面を研削
する工程とを含むというものである。(Means for Solving the Problems) A method for manufacturing a semiconductor device of the present invention includes a step of providing a plating mask for forming bumps on the surface of a semiconductor wafer, and a step of providing a plating mask for forming bumps on the surface of a semiconductor wafer, and a step of providing a plating mask for forming bumps on a surface of a semiconductor wafer. The method includes the steps of forming bumps by plating after applying resin to the peripheral portion, and grinding the back surface of the semiconductor wafer.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
半導体素子の活性領域を作り込んだウェーハの表面にホ
トレジストを塗布し、所定パターンを露光し、現像する
ことによりバンプを形成するためのマスクを形成する。A mask for forming bumps is formed by applying photoresist to the surface of a wafer in which active regions of semiconductor elements have been formed, exposing it to light in a predetermined pattern, and developing it.
次に、第2図(a)に示すように、直径5インチのウェ
ーハ1をスピンナ2に吸着させて回転させ、ウェーハ1
の側面からホトレジストや電子ビーム用1/リストなど
の樹脂を浸出させるはけ4によりウェーハ周辺部約5龍
に塗布し、厚さ5〜6μmの樹脂膜3′を形成する。あ
るいは、第2図(b)に示すように、ウェーハ1を真空
吸着したスピンナ2をウェーハ1が垂直になる様90°
回転させた後樹脂3を溜めた皿5にウェーハ1.を周辺
部が約5市浸かる様にして、スピンナ2を回転させて塗
布してもよい。Next, as shown in FIG. 2(a), the wafer 1 with a diameter of 5 inches is attracted to the spinner 2 and rotated.
A resin such as photoresist or electron beam resin is applied from the side surface of the wafer by a brush 4 that exudes it to about 5 cm around the wafer to form a resin film 3' having a thickness of 5 to 6 μm. Alternatively, as shown in FIG. 2(b), move the spinner 2 holding the wafer 1 under vacuum at an angle of 90° so that the wafer 1 is vertical.
After rotation, the wafer 1 is placed in a tray 5 containing resin 3. It may be applied by rotating the spinner 2 so that the peripheral area is submerged by about 5 cm.
後工程において、第3図(a)に示すように、噴流式め
っき法によりバンプを形成する。筒6の先端の爪7にウ
ェーハ1を表面を下にして置き、下方からめっき液8が
吹き出しウェーハ1.の表面にかかる様にするがウェー
ハ1の周辺部に形成した樹脂膜3′によりウェーハ1の
裏面及び側面にめっき液8のかかるのが防止される。あ
るいは、第3図(b)に示すように、ディップ式めっき
法によってもよい、吸着板9にウェーハ1を真空吸着し
めっき液8の中に浸漬するが、樹脂膜3′により吸着板
9にウェーハ1が密着している為、ウェーハ1の裏面及
び側面にめっきはされない。In the post-process, bumps are formed by a jet plating method, as shown in FIG. 3(a). The wafer 1 is placed face down on the claw 7 at the tip of the tube 6, and the plating solution 8 is blown out from below and the wafer 1. However, the resin film 3' formed around the periphery of the wafer 1 prevents the plating solution 8 from splashing onto the back and side surfaces of the wafer 1. Alternatively, as shown in FIG. 3(b), a dip plating method may be used, in which the wafer 1 is vacuum-adsorbed on a suction plate 9 and immersed in the plating solution 8. Since the wafer 1 is in close contact with the wafer 1, the back and side surfaces of the wafer 1 are not plated.
次に、ウェーハの裏面研削く研削量は400μm)を行
なう、ウェーハの裏面にはめっきされないので研削ブレ
ードの目詰りもなく、第1図にX印で示したように、ウ
ェーハ割れ発生率は著しく少なくなる。Next, the back side of the wafer is ground (the amount of grinding is 400 μm). Since the back side of the wafer is not plated, there is no clogging of the grinding blade, and as shown by the X mark in Figure 1, the incidence of wafer cracking is significantly reduced. It becomes less.
なお、めっき用マスク形成のりソゲラフイエ程の前に、
先づ裏面全面に樹脂をスピンコードし、次に表面のみを
スピンナ上で溶剤で洗浄を行なって裏面をマスクしても
よい。そうすると、ウェーハの側面だけでなく、裏面全
体も樹脂膜におおわれる為、めっき防止が簡単であり又
、既存設備でできるという利点がある。In addition, before applying the plating mask forming glue,
First, the entire back surface may be spin-coded with resin, and then only the front surface may be cleaned with a solvent on a spinner to mask the back surface. In this case, not only the side surfaces but also the entire back surface of the wafer are covered with the resin film, which has the advantage that it is easy to prevent plating and can be done using existing equipment.
以上説明した様に、本発明はバンプ形成時のめっきを行
う前に、ウェーハ周辺部に樹脂膜を形成する事によりウ
ェーハ裏面にめっきされる事を防止し、裏面研削工程の
割れを防止できる効果がある。As explained above, the present invention has the effect of preventing plating on the back side of the wafer by forming a resin film around the wafer before plating when forming bumps, and preventing cracking during the back grinding process. There is.
図面の簡単な説明
第1図はウェーハ割れ発生率と研削量の関係を示す特性
図であり○印で従来の結果を、X印で本発明の結果を示
す。第2図(a)はウェーハを水平に保持して樹脂を塗
布する状態を示す図、第2図(b)はウェーハを縦に保
持して樹脂を塗布する状態を示す図、第3図(a)は噴
流式めっき法を説明するための図、第3図(b)はディ
ップ式めっき法を説明するための図である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a characteristic diagram showing the relationship between the wafer cracking rate and the amount of grinding. The circles indicate the conventional results and the X's indicate the results of the present invention. Fig. 2(a) shows a state in which the wafer is held horizontally and the resin is applied, Fig. 2(b) shows the state in which the wafer is held vertically and the resin is applied, and Fig. 3(a) shows the state in which the wafer is held vertically and the resin is applied. 3(a) is a diagram for explaining the jet plating method, and FIG. 3(b) is a diagram for explaining the dip plating method.
1・・・ウェーハ、2・・・スピンナ、3・・・樹脂、
3′・・・樹脂膜、4・・・はけ、5・・・皿、6・・
・筒、7・・・爪、8・・・めっき液。1... Wafer, 2... Spinner, 3... Resin,
3'...Resin film, 4...Brush, 5...Dish, 6...
・Cylinder, 7...Claw, 8...Plating solution.
Claims (1)
き用のマスクを設ける工程と、前記マスク形成の前又は
後に前記半導体ウェーハの周辺部に樹脂を塗布したのち
にめっき法によりバンプを形成する工程と、前記半導体
ウェーハの裏面を研削する工程とを含むことを特徴とす
る半導体装置の製造方法。a step of providing a plating mask for forming bumps on the surface of a semiconductor wafer; a step of applying a resin to a peripheral portion of the semiconductor wafer before or after forming the mask, and then forming bumps by a plating method; A method for manufacturing a semiconductor device, comprising the step of grinding a back surface of the semiconductor wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11980389A JPH02298036A (en) | 1989-05-12 | 1989-05-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11980389A JPH02298036A (en) | 1989-05-12 | 1989-05-12 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02298036A true JPH02298036A (en) | 1990-12-10 |
Family
ID=14770612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11980389A Pending JPH02298036A (en) | 1989-05-12 | 1989-05-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02298036A (en) |
-
1989
- 1989-05-12 JP JP11980389A patent/JPH02298036A/en active Pending
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