JPH02298037A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a capacitance between a base and a collector by reducing an area of a base region and to improve a high-frequency characteristic by a method wherein outer base regions at both ends of an intrinsic base region are connected by a P-type diffusion layer under an insulator layer. CONSTITUTION:An N-type buried diffusion layer 2 and a P-type buried diffusion layer 3 are formed selectively on a P-type singlecrystal silicon substrate 1. In addition, an N-type epitaxial layer 4 is formed on them. In addition, a P-type insulating isolation diffusion layer 5 is formed by a selective diffusion operation from the surface of the N-type epitaxial layer 4; the P-type buried diffusion layer 3 and element regions such as transistors, resistances and the like are insulated and separated. In addition, the surface of the layer 4 is oxidized selectively; thereby, an insulator layer 6 composed of silicon dioxide is formed. During this process, a P-type diffusion layer 20 is formed selectively in one part under the insulator layer 6 so as to be aligned with the insulator layer 6. In addition, a P-type intrinsic base region 7 and P-type outer base regions 8, 8' are formed in the element regions decided by the insulator layer 6. When this P-type diffusion layer 20 is formed, it is not required to form a contact hole to be connected to an outer metal wiring part with reference to the second P-type outer base region; an area can be reduced by this elimination.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a bipolar semiconductor device with improved high frequency characteristics.

[Conventional technology]

Conventionally, there are the following configuration techniques for this type of semiconductor device.

FIGS. 4(A) and 4(B) are a pattern diagram and a vertical cross-sectional view of a semiconductor chip showing a conventional semiconductor device.

This conventional example will be explained along the manufacturing process. An N-type buried diffusion layer 2 and a P-type buried diffusion layer 3 are provided on a P-type semiconductor substrate 1 made of single crystal silicon, and an N-type epitaxial layer 4 is provided thereon. Further, a P-type insulating isolation diffusion layer 5 is provided that reaches from the surface of the N-type epitaxial layer 4 to the P-type buried diffusion layer 3, and the P-type buried diffusion layer 3 and the P-type insulating isolation diffusion layer 5 surround the transistor forming region. Provide insulation separation between the parts. Furthermore, an insulator layer 6 such as silicon dioxide is selectively provided on the surface of the N-type epitaxial layer 4 to provide isolation between elements at the surface portion.

Furthermore, by selective diffusion from the surface of the N-type epitaxial layer 4, P-type intrinsic base region 7, P-type extrinsic base region 8, N
A mold collector extraction region 9 is provided, and a polycrystalline silicon layer 1 is formed.
An N-type emitter region 11 is provided by introducing N-type impurities through 0. Furthermore, an external metal wiring 14 such as aluminum is connected through the opening provided in the glabella insulator layer 12.13.
It is formed by connecting to.

5(A) and 5(B) are a plan view and a vertical cross-sectional view showing a structure with improved high frequency characteristics compared to the above-described semiconductor device, which is a so-called double base structure. It is called. That is, with respect to the above-described configuration, the first . A second P-type external base region 8, 8' is provided, and a first P-type external base region 8, 8' is provided.
It has a structure in which second P-type external base regions 8 and 8' are connected. In this improved structure, the base is represented by the resistance component of the P-type intrinsic base region 7 in the path from the P-type external base region 7 immediately below the N-type emitter region 11 to the P-type external base regions 8, 8'. Compared to the previous example, the resistance path changes from one place to two places (parallel),
It can be reduced to about half.

[Problem to be solved by the invention]

In the conventional double base structure semiconductor device described above, it is possible to reduce the base resistance, but on the other hand, the area required to form the base region consisting of the intrinsic base region 7 and the extrinsic base region 8.8' is is approximately 1 of the former conventional example.
．． Since it is 5 times larger, the capacitance between the base and the collector increases, and there is a drawback that the overall improvement in high frequency characteristics becomes relatively small. Furthermore, since the element area of the transistor is also increased, there is a drawback that the degree of integration is reduced.

[Means to solve the problem]

The semiconductor device of the present invention includes an N (or P) type buried diffusion layer selectively provided on a P (or N) type semiconductor substrate, and an N (or P) type buried diffusion layer formed on the N (or P) type buried diffusion layer. (or P
) type epitaxial layer, an insulating layer selectively provided on the N (or P) type epitaxial layer and separating transistor regions, and an N (or P) type epitaxial layer in the transistor region.
A P (or N) type intrinsic base region formed in a type epitaxial layer, and first and second P (or N) type extrinsic base regions formed at both ends of the P (or N> type base region). , N formed in the P (or N) type intrinsic base region
(or P) type emitter region, the P (or N) type intrinsic base region and the first . In a semiconductor device comprising a second P (or N) type external base region and an N (or P) type collector extraction region formed in isolation, P (or N> type diffusion layer is formed, and the first and second P (or N) type diffusion layers are formed by the P type diffusion layer.
) type external base area is connected.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1(A) is a pattern diagram showing the first embodiment of the present invention, and FIG. 1(B) and (C) are respectively I of FIG. 1(A).
FIG. 2 is a longitudinal cross-sectional view of the semiconductor chip taken along a line corresponding to the -I' line and the nn' line.

This embodiment will be explained along with its manufacturing process.

A P-type wheel crystal silicon substrate 1 having a specific resistance of about 5 to 30 Ωcm is prepared, and an N-type buried diffusion layer 2 and a P-type buried diffusion layer 3 are selectively provided thereon by ion implantation or impurity diffusion. The N-type buried diffusion layer 2 and the P-type buried diffusion layer 3 have a resistance of, for example, 15 to 40Ω/hole and 80Ω/hole, respectively.
It is configured to have a resistance of ~300Ω/mouth. Furthermore, on top of that, the resistivity is 0.3~2.0ΩCm and the thickness is 1.5~
A 4.0 μm N-type epitaxial layer 4 is provided. Furthermore,
A P-type insulating isolation diffusion layer 5 is provided by selective diffusion from the surface of the N-type epitaxial layer 4, and, together with the P-type buried diffusion layer 3, insulates and isolates element regions such as transistors and resistors. The P-type insulating isolation diffusion layer 5 has an energy of 100 to 150 keV, for example, 5, OXl 0"-3, OXl 014cm-
Boron ion implantation at 2 doses and 980°C to 10°C
This is achieved by heat treatment at 00°C in a nitrogen atmosphere.

Furthermore, by selectively oxidizing the surface of the N-type epitaxial layer 4, an insulating layer 6 made of silicon dioxide having a thickness of 0.6 to 1.2 μm is provided. At this time, a P-type diffusion layer 20 is selectively provided under a portion of the insulator layer 6 in alignment with the insulator M6.

Furthermore, a P-type base region 7 and a first . A second P-type extrinsic base region 8.8' is provided. The P-type external base region 7 and the P-type external base region 8.8' are each
．． 0X1013~3.0X10"cm-2 and 2.0X
1015~1, Ox 1016cm-2cm dose I
The layer resistance and junction depth are 2-6 Ω/hole, 0.15-0.3 μm and 2
The resistance is about 0 to 70Ω/mouth and about 0.4 to 0.6 μm.

Similarly, phosphorus or arsenic ions were implanted into the N-type collector extraction region 9 (dose amount was 2.0×10 15 to 1. OXI
O”cm-2) in the N-type epitaxial layer 4.
It is provided separately from the moldable base region 7 and the P-type external base region 8.8'.

Furthermore, an emitter electrode 10 made of polycrystalline silicon is deposited on the P-type disposed base region 7 through an opening formed in an interlayer insulating layer 12 made of silicon dioxide formed by the C to 'D method, and the emitter electrode is Arsenic is introduced into the P-type dispersion base region through the wafer to form an N-type emitter region 11.

Further, an external metal wiring 14 made of aluminum or the like is provided in the P type external base region 8, the emitter electrode 10, and the N type collector extraction region 9 through an opening provided in the interlayer insulating film 13.

The method for forming the P-type diffusion layer 20 in this example is shown in FIG.
This will be explained using A) to (C). First, as shown in FIG. 2(A), a silicon dioxide film 32 with a thickness of 50 nm is deposited on a single crystal silicon substrate 31, and a silicon dioxide film 32 with a thickness of 100 to 13
A 0 nm silicon nitride film 33 is deposited. A photoresist layer 34 is selectively deposited by photolithography to define the device region, and then the silicon nitride film 33 is selectively removed using the photoresist layer 34. Next, as shown in FIG. 2B, a second photoresist layer 35 having a larger opening than the photoresist layer 34 is selectively deposited while the photoresist layer 34 remains. Next, using the photoresist layer 34 and the second photoresist N35 as masks, 1.0×
Boron ion implantation is performed at a dose of 10" to 3. OX 1013 cm-2. Next, as shown in FIG.
By oxidation treatment in an atmosphere of 60°C to 1050°C f) Hz 02, silicon dioxide [36] is formed, and
P-type diffusion layer 2 whose end is aligned with the silicon dioxide film 36
Get 0. Under the above conditions, the P-type diffusion layer has a resistance of 300Ω~
It has a layer resistance of 1.5 Ω/hole and a junction depth of 0.6 μm to 0.8 μm.

As shown in FIG. 1(A), the P type diffusion layer 20 includes the P type disposed base region 7 and the first . Second P-type extrinsic base region8.
8'. Therefore, the second P-type external base region 8' is connected to the first external base region 8 via the P-type diffusion layer 20, and a contact for connecting the second P-type external base region with external metal wiring is provided. The need for the hole 15 is eliminated, and the area can be reduced accordingly. Furthermore, since the P-type diffusion layer 20 can be provided at the end of the insulating layer that partitions the transistor formation region, the area will not increase.

In the inventor's experiment, the emitter area was 1.8 μm with the shape shown in the first embodiment and the width of the P-type diffusion layer 20 was 1.8 μm.
In a sample of 2 μm x 12 μm, it has been confirmed that the base-collector capacitance is reduced by 15% compared to the conventional double base structure. Further, from the viewpoint of reducing the base-collector capacitance, it is effective to set the width of the P-type spreading layer 20 to 2.5 μm or less, preferably 0.8 μm to 2.0 μm.

FIGS. 3(A) and 3(B) are a pattern diagram and a vertical cross-sectional view of a semiconductor chip showing a second embodiment of the present invention.

In the second embodiment, the P-device base region 7, the first and second P-type base regions 8,8', and the N-type collector extraction region 9 are each separated by an insulating layer 6, and
The P device base region 7 is directly connected to the first. It has a structure in which it does not come into contact with the second P-type external base regions 8, 8', but is connected to the entire periphery via the P-type diffusion layer 20 under the insulating layer 6.

In this example, the first. Second P-type extrinsic base region8.
8' can be formed aligned with the insulating layer 6, so that the distance between the N-type emitter region 11 and the P-type external base region 8.8', which causes a decrease in the emitter-base breakdown voltage, can be kept constant. This method has the advantage of reducing the influence of pattern alignment errors when forming the N-type emitter region and the P-type external base region. Furthermore, if the layer resistance of the P-type diffusion layer 20 can be set to a low value, there is an advantage that the second P-type external base region 8' can be omitted.

〔Effect of the invention〕

As explained above, the present invention provides the first . By connecting the second external base regions with the P-type diffusion layer under the insulating layer, there is no need to provide a contact hole with the metal wiring in the second external base region, and the area can be reduced, making it possible to reduce the area compared to the conventional double While having the same base resistance reduction effect as the base structure, it is possible to reduce the base-collector capacitance by reducing the area of the base region, and has the effect of improving high frequency characteristics.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1(A) is a pattern diagram showing a first embodiment of the present invention, and FIGS. 1(B) and (C) are line II' and n of FIG. 1(A). - A vertical cross-sectional view of the semiconductor chip cut at a portion corresponding to the n' line, and FIGS. 2(A) to (C) are vertical cross-sectional views of the semiconductor chip arranged in the order of steps for explaining the manufacturing method of the first embodiment. , FIGS. 3(A) and (B) are pattern diagrams and vertical cross-sectional views of semiconductor chips showing the second embodiment, and FIGS. 4 (A> and (B) are pattern diagrams and vertical cross-sectional views of semiconductor chips showing conventional examples. 5(A) and 5(B) are a pattern diagram and a longitudinal sectional view of a semiconductor chip showing another conventional example.

DESCRIPTION OF SYMBOLS 1...P type wheel crystal silicon substrate, 2...N type buried diffusion layer, 3...P type buried diffusion layer, 4...N type epitaxial layer, 5...P type insulating isolation diffusion layer , 6...
Insulator layer, 7... P-type concrete base region, 8... (first) P-type external base region, 8'... second P-type external base region, 9... Collector extraction Area, 10...
・Emitter electrode, 11... N-type emitter region, 12° 13... Interlayer insulating film, 14... External metal wiring, 15
... Contact hole, 20... P-type diffusion layer, 31...
・Single crystal silicon substrate, 32... silicon dioxide film,
33... Silicon nitride film, 34... Photoresist layer, 35... Second photoresist, 36... Silicon dioxide S.

Claims (1)

[Claims] N selectively provided on a P (or N) type semiconductor substrate
(or P) type buried diffusion layer, an N (or P) type epitaxial layer formed on the N (or P) type buried diffusion layer, and a selectively provided on the N (or P) type epitaxial layer. an insulating layer separating the transistor regions; a P (or N) type intrinsic base region formed in the N (or P) type epitaxial layer of the transistor region;
or first and second P (or N) type extrinsic base regions formed at both ends of the N) type base region, and an N (or P) type formed in the P (or N) type intrinsic base region. an emitter region, the P (or N) type intrinsic base region and a first;
In a semiconductor device comprising a second P (or N) type external base region and an N (or P) type collector extraction region formed in isolation, P A semiconductor device characterized in that a (or N) type diffusion layer is formed, and the first and second P (or N) type external base regions are connected by the P type diffusion layer.