JPH02299238A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make possible the formation of a high-integration, high-reliability and high- efficiency semiconductor integrated circuit by a method wherein a plurality of semiconductor layers, whose conductivity types or concentrations are different from one another, are connected to one another through an insulating film on the semiconductor layers or a conductive film almost buried in an aperture provided in the semiconductor layers. CONSTITUTION:In a semiconductor device in case the device has a plurality of semiconductor layers (impurity regions), whose conductivity types N-type and A P-type) are different from one another, or in case the device has a plurality of semiconductor layers (impurity regions), whose concentrations (a high concentration, a low concentration and the like) are different from one another, the connection between a plurality of the semiconductor layers is made through an insulating film 5 on the semiconductor layers or a conductive film 6 almost buried in an aperture provided in the semiconductor layers. Thereby, an increase in the integration of a semiconductor integrated circuit due to the fact that the two-dimensionally or three- dimensionally formed semiconductor layers, which respectively have a different conductivity type, can be finely connected to one another and an enhancement in the efficiency of the circuit due to the fact that the semiconductor layers, which respectively have a different concentration, can be connected to one another without changing their resistance values are made possible by the face that the connecting regions for the semiconductor layers can be flatly formed.

Description

[Detailed Description of the Invention] [Summary] In the case of having multiple semiconductor layers (impurity regions) with different conductivity types (n-type and p-type) or with multiple semiconductor layers with different concentrations (high concentration, low concentration, etc.) In the semiconductor device having an impurity region, the plurality of semiconductor layers are connected via an insulating film on the semiconductor layer or a conductive film substantially embedded in an opening provided in the semiconductor layer. Because it is formed into a structure, semiconductor layers of different conductivity types formed in two or three dimensions can be connected finely, resulting in high integration, and semiconductor layers with different concentrations can be connected without changing the resistance value, resulting in high performance. A semiconductor device that achieves high reliability by forming a flat connection area.

[Industrial Field of Application] The present invention relates to MIS and bipolar semiconductor devices, and particularly relates to a semiconductor device that enables the formation of fine connections between multiple semiconductor layers of different conductivity types or multiple semiconductor layers of different concentrations. 9 Conventionally, in connection between multiple semiconductor layers of different conductivity types, the connection was formed by forming separate holes in the insulating film on each semiconductor layer and providing a wiring body to connect these holes. It has the disadvantages that it is impossible to form a wiring body with good step coverage, and it is not possible to make fine connections between multiple semiconductor layers of the same conductivity type but with different concentrations because the double-headed regions are directly connected. However, there is a phenomenon in which the resistance value at low concentrations fluctuates and the characteristics deteriorate, and it also has the drawback that it is impossible to form fine connections that do not fluctuate in resistance value, which has become a major problem that hinders high integration. Therefore, there is a need for a means that has good step coverage, does not change the resistance value, and can form fine connections.

U Prior Art] FIG. 7 is a schematic side sectional view of a first embodiment of a conventional semiconductor device, in which 51 is a p-type silicon (Si) substrate;
2 is a field oxide film, 53 is an n+ type impurity region, 54
is a p-type impurity region, 55 is a blocking oxide film, 56 is a phosphosilicate glass (PSG) film, and 57 is an A1 wiring. Electrode contact windows are formed in the upper insulating films (phosphosilicate glass (PSG) film 56 and blocking oxide film 55), and an AI wiring 57 connecting these electrode contact windows is formed to connect the n+ type impurity region 53 and the p The structure is formed to accommodate the connection of the impurity region 54. Here, since electrode contact windows are formed separately on the n+ type impurity region 53 and the p+ type impurity region 54, the degree of integration is not increased. In addition, A1 has extremely poor lick step coverage, which accommodates direct connections through fine electrode contact windows.
Since the wiring 51 is formed, the life span is deteriorated due to electromigration, and high reliability is difficult.

FIG. 8 is a schematic side sectional view of a second embodiment of a conventional semiconductor device, in which 51, 52, 54 to 57 are the same as in FIG. 7, and 58 is a p-type impurity region.

In the figure, the p-type impurity region 54 and the p- type impurity region 58 are directly connected, and a fine connection is possible, but due to the high temperature heat treatment applied during the process,
The impurity in the p-type impurity region 54 is the p-type impurity region 5.
8, the high resistance value of the p-type impurity region 58 fluctuates and the characteristics deteriorate, resulting in a disadvantage that high performance cannot be ensured.9 [Problem to be solved by the invention 1 The present invention solves As shown in the above-mentioned two conventional examples, the problem to be solved is that, in connection of multiple semiconductor layers of different conductivity types or multiple semiconductor layers of different concentrations, step coverage is good, there is no variation in resistance value, and Another problem was that fine connections could not be formed.

[Means for Solving the Problems] The above problems are caused by a conductive structure in which a plurality of semiconductor layers having different conductivity types or concentrations are substantially embedded in an insulating film on the semiconductor layer or in an opening provided in the semiconductor layer. The problem is solved by a semiconductor device according to the invention which is connected via a membrane.

[Function] That is, in the semiconductor device of the present invention, different conductivity types (
In a semiconductor device having a plurality of semiconductor layers (n-type and p-type) or a plurality of semiconductor layers with different concentrations (high concentration, low concentration, etc.), the connection of the plurality of semiconductor layers is The structure is formed through a conductive film that is approximately buried in the opening provided in the upper insulating film or the semiconductor layer. Therefore, since a selective chemical vapor deposition film can be embedded and connected using self-line into finely formed openings between semiconductor layers of different conductivity types formed two-dimensionally or three-dimensionally, it is possible to form connections with high integration and good step coverage. It is possible. In addition, it is also possible to embed and connect a selective chemical vapor deposition film using a self-line in finely formed openings between semiconductor layers of the same conductivity type and different concentrations.
Since diffusion of impurities from the high concentration region can be prevented, it is also possible to form high-performance connections with no change in resistance value.

In other words, it is possible to obtain a semiconductor device that enables the formation of extremely highly integrated, highly reliable, and high-performance semiconductor integrated circuits.

[Example] The present invention will be specifically explained below with reference to illustrated embodiments.

FIG. 1 is a schematic side sectional view of a first embodiment of the semiconductor device of the present invention, and FIG. 2 is a schematic side sectional view of a second embodiment of the semiconductor device of the present invention.
FIG. 3 is a schematic side sectional view of a third embodiment of the semiconductor device of the present invention, and FIG. 4 is a schematic side sectional view of the fourth embodiment of the semiconductor device of the present invention. , FIG. 5 is a schematic side cross-sectional view of a fifth embodiment of the semiconductor device of the present invention, and FIGS. 6(a) to (C) are process cross-sectional views of an embodiment of the manufacturing method for the semiconductor device of the present invention. The same objects are indicated by the same reference numerals throughout all nine figures.

FIG. 1 is a schematic side sectional view of a first embodiment of a semiconductor device of the present invention using a p-type silicon (Si) substrate.
1 is a p-type silicon (Si) substrate of about 10I5C "3, 2 is the first insulating film (thermal oxide film) of about 30On+s,
3 is 1o20C "n-type impurity region of about 3, 4 is 10
p type impurity region of about 20C1l-3, 5 is 500-
6 indicates a second insulating film (chemical vapor deposition oxide film), and 6 indicates a buried conductive film (selective chemical vapor deposition tungsten film).

In the figure, an n+ type impurity region 3 is formed on a p- type silicon (Si) substrate 1 via a first insulating film (thermal oxide film) 2.
and a p+ type impurity region 4 are provided, and the n+ type impurity region 3 is formed in a second insulating film (chemical vapor deposition oxide film) provided on the n+ type impurity region 3 and the p+ type impurity region 4. An opening is formed to expose a part of the p-type impurity region 4, and this opening is filled with a selective chemical vapor deposition tungsten film 6 into the self-line, and an n+ type impurity is formed through the selective chemical vapor deposition tungsten film 6. A connection between impurity region 3 and p-type impurity region 4 is formed. Therefore, it is possible to form connections with high integration and good step coverage between impurity regions of different conductivity types. The film thickness of n+ type impurity region 4
It is formed to be slightly thinner than the selective chemical vapor deposition tungsten film 6 above. This is because the selective chemical vapor deposition conductive film generally grows at different rates on the n-type impurity region and on the p-type impurity region. -18260 may be used.9 Figure 2 is a schematic side sectional view of a second embodiment of the semiconductor device of the present invention, and 1 to 6 indicate the same elements as in Figure 19. In this method, an opening exposing the sidewalls of the n+ type impurity region 3 and p+ type impurity region 4 is provided in the polycrystalline silicon layer forming the n+ type impurity region 3 and the p+ type impurity region 4. is embedded in the self-line by lateral growth of a selective chemical vapor deposition tungsten film 6, and a connection between the n+ type impurity region 3 and the p+ type impurity region 4 is formed via this selective chemical vapor grown tungsten film 6. As in the first embodiment, it is possible to form connections with high integration and good step coverage.

FIG. 3 is a schematic side sectional view of a third embodiment of the semiconductor device of the present invention, and numerals 1 to 4.6 indicate the same elements as in FIG. 1.

In the figure, an n0-type impurity region 3 is formed in a p-type silicon (Si) substrate 1, and a p-type silicon (S
i) P on the substrate 1 via the first insulating film (thermal oxide film) 2
A ten-type impurity region 4 is formed, and an opening is provided in the first insulating film (thermal oxide film) under the p-type impurity region 4 to expose a part of the n-type impurity region 3. The openings are filled with a self-lined selective chemical vapor deposition tungsten film 6, and this selective chemical vapor deposition tungsten H
6 in the particle direction through n-type impurity region 3 and p
A connection between the ten-type impurity regions 4 is formed. Similar to the first embodiment, this also enables the formation of connections with high integration and good step coverage.9 FIG. 4 is a schematic side sectional view of the fourth embodiment of the semiconductor device of the present invention. .2.4 to 6 are the same as in Figure 1, 3
3b indicates a first n+ type impurity region, and 3b indicates a second n+ type impurity region.

In the figure, a first n0-type impurity region 3a is formed on a 9p-type silicon (Si) substrate 1 in which three conductive regions are simultaneously connected.
i) A polycrystalline silicon layer forming a second n+ type impurity region 3b and a p + type impurity region 4 is provided on the substrate 1 via the first insulating film (8 oxide film) 2, A second insulating film (thermal oxide film) 2 is applied to this polycrystalline silicon layer and the first insulating film (thermal oxide film) 2.
Openings are provided to expose the side walls of the n + -type impurity region 3b and the p 10 -type impurity region 4 and a part of the upper surface of the first n 1 -type impurity region 3a, and the openings are selectively used to form a selective chemical vapor deposition tungsten film. 6 is buried in the self-line by lateral and particle growth, and the first n-type impurity region 3a and the second n-type impurity region 3a are formed through this selective chemical vapor deposition tungsten film 6.
A connection between the ten type impurity region 3b and the p ten type impurity region 4 is formed. Similar to the first embodiment, this also enables the formation of connections with high integration and good step coverage.9 FIG.
In the schematic side sectional view of the embodiment, 1, 2.4 to 6 are the same as in FIG. 1, and 7 is a p-type impurity region. Openings are provided in the polycrystalline silicon layer forming the −-type impurity region 7 to expose the side walls of the p-type impurity region 4 and the p--type impurity region 7, and these openings are selected for f-type vapor phase growth tungsten. The p-type impurity region 4 is filled through the selective chemical vapor deposition tungsten film 6 by lateral growth of the film 6.
The interposition of this selective chemical vapor deposition tungsten film 6 prevents diffusion of impurities from the high concentration region, resulting in a high performance film with no change in resistance value. Furthermore, the same effects as in the first embodiment can also be obtained.

Next, an embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 6(a) to 6(C) and FIG. 1.

Figure 6(a) By applying conventional techniques, p-type silicon (S)
i) A first insulating film (thermal oxide film) 2, a polycrystalline silicon layer 8, and a second insulating film (chemical vapor deposition oxide film) 5 are sequentially grown on the substrate 1.

FIG. 6(b) Next, using a normal photolithography technique and using a resist (not shown) as a mask layer, arsenic is ion-implanted to form the n+ type impurity region 3, and boron is ion-implanted to form the p-type impurity region 3. A polycrystalline silicon layer 8 is selectively applied to each region 4.
to form.

FIG. 6(C) Next, using a normal photolithography technique and using a resist (not shown) as a mask layer, the second insulating film (chemical vapor deposition oxide film) 5 is selectively etched away, and n.
An opening exposing the vicinity of the boundary between the +-type impurity region 3 and the p-type impurity region 4 is formed (9).The opening is then filled with a selective chemical vapor deposition tungsten film 6 to form a self-alignment line. Next, the polycrystalline silicon layer 8 is patterned using a resist (not shown) as a mask layer using an ordinary photolithography technique.As shown in the above embodiments, according to the semiconductor device of the present invention, A selective chemical vapor deposition film can be embedded and connected to the self-line in fine openings formed between impurity regions of different conductivity types formed in two or three dimensions, making it possible to form connections with high integration and good step coverage. It is. Additionally, a selective chemical vapor deposition film can be embedded and connected using a self-line in finely formed openings between impurity regions of the same conductivity type and different concentrations, which prevents diffusion of impurities from high concentration regions. [Effects of the Invention] As explained above, according to the present invention, in MIS and bipolar semiconductor devices, it is possible to form a high-performance connection without a change in resistance value. Because the connection between the semiconductor layer or a plurality of semiconductor layers with different concentrations is formed through an insulating film on the semiconductor layer or a conductive film roughly embedded in an opening provided in the semiconductor layer. , high integration due to the ability to finely connect semiconductor layers of different conductivity types formed in two or three dimensions, and high performance f due to the ability to connect semiconductor layers of different concentrations without changing the resistance value. High reliability can be achieved by being able to form a flat surface. That is,
It is possible to obtain a semiconductor device that enables the formation of extremely highly integrated, high-performance semiconductor integrated circuits.

4 Brief Description of the Drawings FIG. 1 is a schematic side sectional view of the first embodiment of the semiconductor device of the present invention, FIG. 2 is a schematic side sectional view of the second embodiment of the semiconductor device of the present invention, and FIG. FIG. 4 is a schematic side sectional view of a fourth embodiment of the semiconductor device of the present invention. FIG. 5 is a schematic side sectional view of the fourth embodiment of the semiconductor device of the present invention. A schematic side sectional view of the fifth embodiment, FIGS. 6(a) to 6(C) are an example of the manufacturing method for the semiconductor device of the present invention (step sectional view of example i, and FIG. 7 is a process sectional view of the conventional semiconductor device). 9 is a schematic side sectional view of the first embodiment of the conventional semiconductor device, and FIG. 8 is a schematic side sectional view of the second embodiment of the conventional semiconductor device. 1st insulating film (thermal oxide film), 3.3a, 3h are n-type impurity regions, 4 is p-type impurity region, 5 is second insulating film (chemical vapor deposition oxide film), 6 is buried Conductive film (selective chemical vapor deposition tungsten film), 7 indicates p-type impurity region, 8 indicates polycrystalline silicon layer 9

Claims (2)

[Claims] (1) A plurality of semiconductor layers having different conductivity types or concentrations are connected via an insulating film on the semiconductor layer or a conductive film roughly embedded in an opening provided in the semiconductor layer. Semiconductor equipment. (2) The semiconductor device according to claim 1, wherein the conductive film is made of a selective chemical vapor deposition conductive film.