JPH02299323A - D/a conversion circuit - Google Patents

Abstract

PURPOSE:To attain D/A conversion with an object bit number by detecting a deficient bit of a DAC at LBS side by means of a shift register, weighting the detected bit and adding the result to an IV conversion circuit to employ a D/A converter with a fewer bit number. CONSTITUTION:A data from the MSB to the 18-th bit stored in a register of a D/A converter 3 is D/A-converted, and fed to an inverting terminal of an IV converter 4 as a current from an IOUT terminal. Moreover, since the LSB and the 19-th bit of a data are stored to D latch FFs 10, 9 through Q terminal of the FFs, the 2 high order bits are added to the output from the IOUT terminal of the converter 3. Thus, a 20-bit data being the sum of the data from the 18-bit converter 3 and the 2-bit data from the D latch FFs 9, 10 is outputted as a D/A-converted output voltage VOR.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a DA conversion circuit, and particularly to an A conversion circuit suitable for converting a number of bits greater than the constituent bits of a DA converter.

(B) Prior Art As a conventional DA conversion circuit, for example, one shown in FIG. 3 has been provided.

In the figure, 11 is a digital filter, 22 is a DA converter, 33 is an IV converter, and 44 is an L channel DA converter circuit.

As for the circuit configuration, the output data of the digital filter 11 is the OR (data R channel) of the digital filter 1.
It is output from the terminal and input to the DATA terminal of the DA converter 22.

Further, the bit clock signal Be, which is a timing signal, is supplied with DA from the BCK i4I child of the digital filter 11.
It is input to the BGK terminal of the converter 22.

Furthermore, the latch signal LE that latches the data R channel OR input to the DA converter 22 is input from the LH terminal of the digital filter 11 to the D
It is connected to the LE terminal of the A converter 22.

The output of the DA converter 22 is I. UT line terminal IV converter 3
It is input to the invert terminal of 3.

Further, the IV converter 33 is provided with a feedback circuit,
Output terminal ■ via feedback resistor Rr. Fl and the invert terminal are connected.

Further, the data signal OL signal for the L channel is applied from the digital filter 11 to the DA converter circuit 44 for the L channel, and the bit clock signal 80K and the latch signal LE are also connected to the DA converter circuit 44 for the L channel.

As for the operation of the circuit, the data R channel signal OR output from the digital filter 11 is applied to the DATA terminal of the DA converter 22 in a serial bit configuration, and is sequentially input from the MSB bit of the data R channel signal DR by the pit clock signal BCK. , 1- are stored in a register in the LDA converter 22.

For example, if the number of constituent bits of the data R channel signal DI+ is 20 bits, when the 20 bits from MSB to LSB are stored in the register of the DA converter 22, the latch signal LE is output, and the data R channel signal DR is output. The data is stored in the register of the DA converter 22 and a DA conversion operation is performed.

The output signal after DA conversion is converted into a current amount and sent to the DA converter 22.
I. The signal is output from the UT line terminal and added to the invert terminal of the IV converter 33.

In the IV converter 33, the I of the DA conversion 322. The output voltage is converted to a voltage value according to the amount of current from the LIT terminal. 8
Output as .

Therefore, the data R channel signal composed of 20 bits output from the digital filter 11 is transmitted to the rv converter 33.
The output voltage is V. 8 and can be output.

(c) Problems to be solved by the invention However, in the conventional DA conversion circuit described above, the third
As shown in the figure, it is equivalent to the configuration bits of the DA converter, or
DA conversion is performed by inputting the number of bits less than the number of constituent bits, and input data exceeding the number of constituent bits is converted to DA.
There was a drawback that it could not be converted.

This invention has been made in view of the above-mentioned points, and its purpose is to eliminate the drawbacks of the conventional example, and to reduce the number of bits of input data even if the input data exceeds the number of bits constituting the DA converter. An object of the present invention is to provide a DA converter circuit that can obtain an output equivalent to that of a DA converter having the same number of bits.

(d) Means for Solving the Problem The DA conversion circuit of the present invention includes a digital filter, a DAC (digital-to-analog converter) that inputs output data of this digital filter, and an IV
DA configured with an rv converter that converts (current-voltage conversion)
In the conversion circuit, if the number of bits of the DAC is smaller than the number of bits configuring the output data of the digital filter, the DA
A means for detecting missing bits on the LSB side of C using a shift register, a logic circuit configured to input predetermined data and a bit clock to a DAC, and an IV conversion circuit that weights the detection bits of the shift register. It is something like adding to.

(E) Effect According to the present invention, a shift register is provided between a digital filter composed of 20 bits and an 18-bit DAC, and output data of the digital filter is transferred to the shift register at the timing of the pit clock of the digital filter. Enter sequentially.

At the timing when the 18th bit signal of the output data of the digital filter is output to the Qc output terminal of the shift register, the LSB and LSB-1 bits from the QA and QB output terminals of the shift register are input to the digital filter by two D latch flip-flops. The data is stored at the timing of the latch signal H from .

The output-enabled outputs of these two D-latch flip-flops are added to the invert terminal of the IV converter, and the I of the DAC is input. U.T.
By adding it to the output signal from the line terminals, even if the 18-bit DAC has a bit configuration less than the 20 bits that make up the output data of the digital filter, the same number of bits as the 20 bits of the output data of the digital filter can be used as the DA conversion output. Obtainable.

(v) Embodiment An embodiment of the DA conversion circuit according to the present invention is shown in FIGS. 1 and 2.
This will be explained based on the diagram.

FIG. 1 is a circuit diagram of the present invention, and FIG. 2 is a timing chart.

In the figure, 1 is a digital filter, 2 is a shift register, and 3
is a DA converter, 4 is! ■Converter, 5 is L channel DA
Conversion circuit, 6.8 is an inverter circuit, 7 is a NOR circuit,
9.10 is a D-latch flip-flop circuit.

To explain the circuit configuration, the data R channel DR output from the digital filter 1 is transferred to the B of shift register 2.
It is connected to the input terminal, and the pit clock B (from the J terminal is connected to the input terminal of the clock C of the shift register 2. Also, from the LEi terminal of the digital filter 1, a latch signal is sent to the DA converter 3. Connected to latch input terminal LE.

Further, the latch signal is applied to the clock C61 of the D latch flip processor 1 circuit 9 and 10 via the inverter circuit 8, and furthermore, from the digital filter 1 to the data signal DL for the L channel and the pit clock signal BC. and latch signal], E are applied to the L channel DA conversion circuit 5.

As for the circuit operation, if the data output from the data R channel DR terminal of the digital filter 1 has a 20-bit configuration, for example, the waveform shown in timing chart 0 in FIG. 2 is applied to the input terminal of the shift register 2.

Furthermore, from the pit clock BCK terminal of the digital filter 1, the waveform shown by ■ in FIG. 2 is input to the clock input GK terminal of the shift register 2, and the pit clock Be shown by Output terminals QA, QR, and Qc have data R shown in FIG.
Channel data is output.

The signal output from the output terminal Qc of the shift register 2 is applied to the DATA terminal of the DA converter 3 as data from the MSB to the 18th bit.

Further, output signals from output terminals QA and QB are applied to D input terminals of D latch flip-flop circuits 10 and 9.

On the other hand, ■ output from the BC terminal of digital filter 1
The pit crotter signal shown by is smoothed by a diode D1 and a capacitor C1 and input to the inverter circuit 6. In addition, the output of the inverter circuit 6 is the NOR circuit 7
is applied to one gate of , and an undelayed bit clock signal is applied to the other gate.

Therefore, the output of the NOR circuit 7 is a clock signal having an opposite phase to the pit clock Be of the signal 2, as shown by .

The operation of shift register 2 is based on the BGK of digital filter 1.
B every time the pit clock signal from the terminal enters the GK line terminal
The data R channel signal input to the terminal is stored in the shift register, and one data is stored in the shift register 2 in response to 20 bit clock signals.

Therefore, when the 20th pit clock signal is input, the LSB of the data R channel signal is also input to the QA terminal of shift register 2, the 19-bit data is also input to the Qa terminal, and the 18-bit data is input to the QC terminal. This means that eye data is being output.

The data input timing of the DA converter 3 is such that the signal from the QC terminal of the shift register 2 is stored in the register in the DA converter 3 according to the bit clock signal output from the NOR circuit 7. When the input end of the inverter circuit 6 stops receiving the pit clock signal from the diode D1, the smoothing effect by the smoothing circuit capacitor C1 disappears, and the "H" level is maintained until indicated by d in ■. The gate of the NOR circuit 7 is set to "H" level, and the terminal of the DA converter 3 is set to "L".
″ level.

After the pit clock signal ends and before the next pit clock signal is input, the latch signal LE is output from the LE terminal of the digital filter 1, and this LE becomes "L" level and is added to the LEi terminal of the DA converter 3. The data stored in the register in the DA converter 3 is latched, and the C terminals of the D latch flip-flops 9 and 10 are connected to the inverter 8.
The output data of the Q^ and Q8 terminals of the shift register 2 is stored.

The data from the MSB to 18 bits stored in the register of the DA converter 3 is converted to I. The amount of current from the uT terminal is applied to the invert terminal of the IV converter 4.

Furthermore, since the LSB and 19th bit of the data are stored in the Q terminal of the D-latch flip-flop 10.9, by applying this data to the invert terminal of the IV converter 4 via resistors R3 and R2, the high-order bit is 2 bits are D
This means that it is added to the output from the i0UT terminal of A converter 3.

Therefore, the output terminal of the IV converter 4 has an 18-bit D
Data from A converter 3 and D latch flip-flop 9
．． The output voltage V is obtained by converting the 20-bit data obtained by adding the 2-bit data from 10 to DA. It can be output as R.

(G) Effects of the Invention According to the DA conversion circuit according to the present invention, a shift register and a D-latch flip-flop are provided between the digital filter and the DA converter, and the output data configuration bits of the digital filter are transferred to the DA converter. By dividing the number of constituent bits into the number of constituent bits and the number of bits of the difference between the output data constituent bits of the digital filter and the constituent bits of the DA converter, and weighting and adding the missing bits of the DA converter to the IV converter, D.A.
Convert data with the desired number of bits into D using a DA converter with a bit configuration smaller than the number of bits of the data to be converted.
It has the effect of allowing A conversion.

In addition, it has excellent features such as a simple structure, low cost, and easy implementation.

[Brief explanation of the drawing]

1 and 2 show an embodiment of the DA conversion circuit according to the present invention, with FIG. 1 being a circuit diagram and FIG. 2 being a timing chart. FIG. 3 is a circuit diagram of a conventional example. Explanation of the symbols of the main parts! Digital filter 2: Shift register 3: DA converter 4: IV converter 5: L channel DA converter circuit 6.8: Inverter circuit 7: NOR circuit 9.10: D latch flip-flop circuit Patent applicant
Kenwood Co., Ltd. Figure 3

Claims (1)

[Claims] A digital filter, a DAC (digital-to-analog converter) that inputs the output data of this digital filter, and an I/V converter that converts the output signal of this DAC into an IV (current-voltage conversion).
In a DA conversion circuit configured with a V converter, when the number of bits of the DAC is smaller than the number of bits constituting the output data of the digital filter, means for detecting missing bits on the LSB side of the DAC by a shift register;
1. A DA conversion circuit comprising: a logic circuit configured to input predetermined data and a bit clock; and a DA conversion circuit configured to weight detection bits of a shift register and add them to an IV conversion circuit.