JPH02299345A - Line address scanning circuit - Google Patents

Abstract

PURPOSE:To monitor the scanning of an effective line address only and to improve the line processing efficiency by providing a selector detecting a line address without interrupt mask command and a stack control circuit performing access control to a stack. CONSTITUTION:A selector 30 detects a line address without interrupt master command based on an output of a +1 counter 20 and the content of a flag register 10. A counter control circuit 52 of a stack control circuit 50 stores the line address without interrupt mask command in line addresses outputted by a counter 20 to a stack 40 based on the detection output of the selector 30. An adder 54 based on the content of the register 10 sums number of line addresses without the interrupt mask command. Then a comparator 55 resets a +1 counter 53 when the output of the counter 53 and the result of the sum of the adder 54 are coincident. Thus, the line processing efficiency is improved without scanning monitor of the line address not required for monitor subjected to interrupt masking.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a line address scanning circuit of a communication control device. In particular, it relates to a line address scanning circuit for monitoring multiple lines.

〔overview〕

The present invention stores the valid line addresses listed above in the stack when setting the mask flag for line interrupts in the line address scanning circuit. This is designed to improve processing efficiency.

[Conventional technology]

Conventionally, a line address scanning circuit has been comprised of a counter for scanning and monitoring all line addresses and means for masking interrupt signals for each line.

[Problem that the invention seeks to solve]

However, in such conventional line address scanning circuits,
All line addresses are scanned and monitored for interrupts from the line and interrupt mask instructions. therefore,
Since addresses of lines that do not need to be monitored and whose interrupts are masked are also scanned and monitored, there is a drawback that time is wasted in accepting interrupts from the lines.

The present invention solves the above-mentioned drawbacks, and aims to provide a line address scanning circuit that can improve line processing efficiency without scanning and monitoring line addresses that are masked for interrupts and do not need to be monitored.

[Means for solving problems]

The present invention includes a flag register in which interrupt mask information is set for each line according to instructions from a communication control device, and a counter that sequentially and periodically outputs line addresses based on write signals from the line control device. In the line address scanning circuit, a selector detects a line address without an interrupt mask instruction based on the contents of the flag register and the output of the counter, and stores a line address without an interrupt mask instruction among the outputs of the counter. a stack; and a stack control circuit for controlling access to the stack; the stack control circuit includes means for providing a write mode signal to the stack based on the write signal; and means for providing a write mode signal to the stack based on the output of the counter. a read/write control circuit including means for providing a read mode signal; and a read/write control circuit that provides a write control signal and a write address to the stack in synchronization with the counter based on the write mode signal and the detection output of the selector; counting means for periodically providing a read address based on the signal; an adder for adding up the number of line addresses for which no interrupt masking instruction is given based on the contents of the flag register; and an output of the counting means based on the read mode signal. It is characterized by including a comparator that resets the counting means when the addition result of the adder matches.

The present invention also includes a flag register in which interrupt mask information is set for each line according to instructions from a communication control device, and a counting means for sequentially and periodically outputting line addresses based on a write signal from the line control device. a selector for detecting a line address without an interrupt mask instruction based on the contents of the flag register and the output of the counter; and a selector for detecting a line address without an interrupt mask instruction among the outputs of the counter. The stack control circuit includes a stack that stores a line address and a stack control circuit that controls access to the stack, and the stack control circuit includes means for applying a write mode signal to the stack based on the write signal and an output of the counter. a read/write control circuit that provides a read mode signal to the stack based on the above; a counting means for periodically giving a read address based on the read mode signal; a maximum address holding register for holding the maximum value of the output of the counting means based on the write mode; and a maximum address holding register for holding the maximum value of the output of the counting means based on the read mode signal; A comparator may be included for resetting the counting means when the output matches the contents of the maximum address holding register.

[Effect]

The selector detects a line address without an interrupt mask instruction based on the contents of the flag register and the output of the counter. A read/write control circuit of the stack control circuit provides a write mode signal to the stack based on a write signal from the communication control device, and provides a read mode signal after one cycle of the counter. The counting means of the stack control circuit applies a write control signal and a write address to the stack in synchronization with the counter based on this write mode signal and the detection output of the selector, and selects the interrupt mask among the line addresses output by the counter. Store the missing line address on the stack.

Also, based on the read mode signal, a read address is periodically given to the stack to read its contents. The adder in the stack control circuit adds up the number of line addresses without interrupt mask instructions based on the contents of the flag register. The comparator of the stack control circuit resets the counting means when the output of the counting means and the addition result of the adder match based on the read mode signal. By the above-described operation, line processing efficiency can be improved without scanning and monitoring line addresses that are masked for interrupts and which do not require monitoring.

Furthermore, the present invention provides a maximum address holding register in the stack control circuit instead of the adder, holds the maximum value of the output of the counting means based on the write mode signal, and uses the comparator to hold the maximum value of the output of the counting means based on the read mode signal. When the output matches the contents of this maximum address holding register, the counting means can be reset.

[Example] An example of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of a line address scanning circuit according to an embodiment of the present invention. FIG. 2 is a block diagram of the stack control circuit of the line address scanning circuit of the present invention. In FIGS. 1 and 2, the line address scanning circuit writes interrupt mask information to signal line 32.1 by a write signal manually applied via signal line S1 for each line according to instructions from a communication control device. -3
21, and a +1 counter 20 as a counter for sequentially and periodically outputting line addresses based on a write signal input via signal line S1 of the line control device.

Here, the feature of the present invention is that the flag register 1
The contents of 0 are transferred to the signal line S3. -33. A selector 30 detects a line address without an interrupt mask instruction by manually inputting the output of the counter 20 via a signal line S4.
A stack control circuit 50 includes a stack 40 that stores a line address without an interrupt mask instruction among the outputs of the +1 counter 20 via a signal line S4, and a stack control circuit 50 that controls access to the stack 40. 50 is
Applying a write mode signal to the stack 50 via the signal line S7 based on the write signal input via the signal line s1,
+1 counter 20 based on the read/write control circuit 51 which gives a read mode signal after one cycle of the counter, this write mode No. 1 which is input manually via signal line S7, and the detection output of selector 30 which is input via signal line S5. A counter is used as a counting means to provide a write control signal and a write address to the stack 40 via signal lines S8 and S6, respectively, in synchronization with Control circuit 52 and +
1 counter 53, an adder 54 that adds up the number of line addresses without interrupt mask instructions input via signal lines 331 to S3h based on the contents of the flag register 10, and a +1 counter 53 based on the read mode signal. The comparator includes a comparator that resets the +1 counter 53 when the output matches the addition result of the adder.

The operation of the line address scanning circuit having such a configuration will be explained. FIG. 3 is a time chart of signals of various parts in the write mode of the line address scanning circuit of the present invention. FIG. 4 is a time chart of signals of various parts in the read mode of the line address scanning circuit of the present invention.

In FIGS. 1 and 2, the flag register 10 is
It has an n-bit flag for the number of lines n, and the signal line S1
The write signals from signal lines S2, to 32. Sets the interrupt mask flag given by .

The +l counter 20 is an n-ary counter, and is started from "0" by a write signal from the signal line S1. +1 counter 20
The selector 30 selects one bit of the interrupt mask flag according to the value of .

When a write signal is applied from the signal line S1, the stack control circuit 50 controls the stack 40 while the +1 counter 20 makes one round.
If the interrupt mask flag given by the selector 30 is logic "0", the write mode is entered into the stack 40.
1 Write the value of the counter 20, and do not write if it is logical "1".

After the +l counter 20 has completed one round, the stack control circuit 5
0 is the read mode, and the contents of the stack 40 are cyclically read out and given to the communication control device as a line address.

In FIG. 2, when the read/write control circuit 51 receives a write signal from the signal line S1, it outputs a write mode signal while the +1 counter 20 completes one revolution.

+1 counter 53 is synchronized with +1 counter 20,
Give the address of stack 40.

In the write mode, the counter control circuit 52 writes the value of the +1 counter 20 to the stack 40 if the interrupt mask flag is logic "0", updates the +1 counter 53 by "+1", and if the interrupt mask flag is logic "1" does nothing.

Moreover, if it is not the write mode, the +1 counter 53 is always incremented by "+1".

Adder 54 receives output 33 . of flag register 10 . ~33
, i.e., n(3++3□+
+3. , ) is calculated.

Comparator 55 compares the value of +1 counter 53 and the value of adder 54 when not in write mode, and resets +1 counter 53 if they match.

FIG. 3 is a time chart showing the operation in the write mode to the stack 40, where the number of lines is n and the line address is 0.2.
．． An example is shown in which the interrupt mask is set to 3.

An n-bit value with bits 0.2.3 set to logic "1" is given as an interrupt mask flag from the signal line S 2 +''=32-, and a write signal is given from the signal line S1. As a result, the value of the interrupt mask flag is held in the flag register 10, and the read/write control circuit 51 determines that the +1 counter 20 is 1.
During the rotation, a signal for setting the stack 40 in write mode is output to the signal line S7.

The signal line S4 is the output of the +1 counter 20 and serves as the selection power of the selector 30.

Signal line s3. -33. ．． Out of the signal! 1nIs41;
:The selected signal is output to the signal line S5.

If this value is logic “1” (interrupt mask instruction), +
The output signal of the 1 counter 53 is not changed, and if the logic is "0", a counter update signal is output to the signal line SIO, and the signal line S6 is updated by "+1". Therefore, m shown in the signal line S6 is m=n-3 in this case.

The signal line S8 is a write control signal to the stack 40, and if the signal line S5 is logic "0", the value of the signal line S6 is written to the stack 40.
Write to 0. The output value of the signal line S11 gives m=n-Σ3X x+1.

The signal on the signal line S12 is +1 counter 53 and the stack 40
It is output when the maximum address is reached, but it is not output in write mode.

FIG. 4 shows the operation in the read mode from the stack memory, and is an example showing the operation after writing under the same conditions as FIG. 3.

Signal line S7 indicates read mode.

A signal line S6 indicates the address of the staff register 40, and performs m-adic counting at a constant period.

The signal on the signal line 312 is output when the value of the adder 54 and the value of the +1 counter 53 match. Signal line S9 is the output of stack 40 and outputs the valid line address stored during write mode.

The block configuration diagrams shown in FIGS. 1 and 2 only illustrate features of the present invention, and there are actually circuits and connections that are not shown.

FIG. 5 is a block diagram of a stack control circuit of a line address scanning circuit according to an embodiment of the present invention.

Here, the block diagram of the line address scanning circuit of the other embodiment is the same as that in FIG.

In FIG. 5, 56 indicates a maximum address holding register. The maximum address holding register 56 is connected to the read/write control circuit 51 via a signal line S7, and to the counter control circuit 52 via a signal line SIO. Further, it is connected to a +1 counter 53 via a signal line S6. When the read/write control circuit 51 receives a write signal from the signal line S1, it outputs a write mode signal while the +1 counter 20 makes one revolution.

+1 counter 53 is synchronized with +1 counter 20,
Give the address of stack 40.

In the write mode, if the interrupt mask flag is logic "0", the counter control circuit 52 writes the value of the +1 counter 20 to the stack 40, stores the value of the +1 counter 53 in the maximum address holding register 56, and stores the value of the +1 counter 53 in the maximum address holding register 56. Counter 53 is
+1” is updated, and if the logic is “1”, nothing is done. Also,
If it is not the write mode, the +1 counter 53 is always set to “+1
"Update.

Comparator 55 compares the value of +1 counter 53 and the value of maximum address holding register 56 when not in write mode, and resets +1 counter 53 if they match.

FIG. 6 is a time chart showing the operation of the line address scanning circuit according to another embodiment of the present invention in the write mode to the stack memory. An example when set is shown below.

Signal line S2. From ~S20, an n-bit value with bits 0.2.3 set to logic "1" is given as an interrupt mask flag, and a write signal is given from the signal line S1. As a result, the value of the interrupt mask flag is held in the flag register 10, and the read/write control circuit 51 outputs a signal to the signal line S7 to set the stack memory in write mode while the +1 counter 20 completes one revolution. .

The signal line S4 is the output of the +1 counter 20 and serves as the selection power of the selector 30.

Signal lines S3+ to S3. , the signal selected by the signal line S4 is output to the signal line S5.

If this value is logic “1” (interrupt mask instruction), +
The signal line S6 for the output signal of the 1 counter 53 is not changed, and if the logic is "0", a counter update signal is output to the signal line S10, and the signal line S6 is updated by "+1". therefore,
In this case, m shown in the signal line S6 is m=n-3.

The signal line S8 is a write signal to the stack 40, and the signal line S5
If is logical "0", the value of the signal line S6 is written to the stack 40. Further, the value of the signal line S6 is held in the maximum address holding register 56 by the signal line 310, and outputted to the signal line 5llA as the maximum address of the stack 40. The output value of the signal line 311 is fixed at the end of the write mode.

The signal on the signal line S12 indicates that the +1 counter 53 is connected to the stack 4.
It is output when the maximum address of 0 is reached, but it is not output in write mode.

A time chart showing the operation of the line address scanning circuit according to another embodiment of the present invention in the read mode from the stack memory is the same as that shown in FIG.

Signal line S7 indicates read mode.

The signal line S6 indicates the address of the stack 40, and performs m-adic counting at a constant period.

The signal on the signal line S12 is transmitted to the maximum address holding register 56.
It is output when the value of +1 counter 53 matches the value of +1 counter 53. Signal line S9 is the output of stack 40 and outputs the valid line address stored during write mode.

The block configuration diagram shown in FIG. 5 only shows features of the present invention, and there are actually circuits and connections that are not shown.

〔Effect of the invention〕

As described above, the present invention has the excellent effect of scanning and monitoring only valid line addresses and improving line processing efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a line address scanning circuit according to an embodiment of the present invention. FIG. 2 is a block diagram of the stack control circuit of the line address scanning circuit of the present invention. FIG. 3 is a time chart of each signal during stack writing in the line address scanning circuit of the present invention. FIG. 4 is a time chart of each signal during stack readout of the line address scanning circuit of the present invention. FIG. 5 is a block diagram of a stack control circuit of a line address scanning circuit according to an embodiment of the present invention. FIG. 6 is a time chart of each signal during stack writing in the line address scanning circuit according to the embodiment of the present invention. lO...Flag register, 20.53...+1 counter, 30...Selector, 40...Stack, 50
Stack control circuit, 51 Read/write control circuit, 52 Counter control circuit, 54 Adder, 55 Comparator, 56 Maximum address holding register, 81 to S12 ···Signal line.

Claims (1)

[Claims] 1. A flag register in which interrupt mask information is set for each line according to instructions from a communication control device, and a counter that sequentially and periodically outputs line addresses based on write signals from the line control device. a selector for detecting a line address without an interrupt mask instruction based on the contents of the flag register and the output of the counter, and a line address without an interrupt mask instruction among the outputs of the counter; The stack control circuit includes a stack for storing addresses and a stack control circuit for controlling access to the stack, and the stack control circuit includes a means for applying a write mode signal to the stack based on the write signal and an output of the counter. a read/write control circuit including means for applying a read mode signal to the stack based on the write mode signal; and a read/write control circuit that applies a write control signal and a write address to the stack in synchronization with the counter based on the write mode signal and the detection output of the selector. , a counting means for periodically providing a read address based on the read mode signal, an adder for adding up the number of line addresses for which there is no interrupt mask instruction based on the contents of the flag register, and a count means for adding the number of line addresses for which there is no interrupt mask instruction based on the contents of the flag register; A line address scanning circuit characterized in that it includes a comparator that resets the counting means when the output of the means and the addition result of the adder match. 2. A line address that includes a flag register in which interrupt mask information is set for each line according to instructions from the communication control device, and a counter that sequentially and periodically outputs the line address based on the write signal of the line control device. The scanning circuit includes a selector that detects a line address without an interrupt mask instruction based on the contents of the flag register and the output of the counter, and a stack that stores the line address without an interrupt mask instruction among the outputs of the counter. , a stack control circuit for controlling access to the stack, the stack control circuit providing a write mode signal to the stack based on the write signal and a read mode signal to the stack based on the output of the counter. A read/write control circuit including means for providing a signal; and a read/write control circuit that provides a write control signal and a write address to the stack in synchronization with the counter based on the write mode signal and the detection output of the selector; a maximum address holding register that holds the maximum value of the output of the counting means based on the write mode; and a maximum address holding register that holds the maximum value of the output of the counting means based on the read mode signal; A line address scanning circuit comprising: a comparator that resets the counting means when the contents of the holding register match.