JPH0229994A - semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a semiconductor memory device equipped with a chip selection signal terminal, and more particularly to a semiconductor memory device that achieves faster access time from a chip selection signal.

[Conventional technology]

FIG. 6(a) is a block diagram of a conventional semiconductor memory device. FIG. 6(b) is a diagram showing FIG. 6(a) in more detail. C8 is a chip selection signal, and when this signal is at H level, it is in a non-selected state and the storage circuit is in a standby state.
Internal selection signal CSA is at H level and address manual buffer 7
The operation of the circuit 2 is inhibited, the operation of the decoder circuit 4 is stopped, and the levels of the word line and column selection line, which are memory cell selection lines, are kept low. The CTL controls the operation of the circuit, has a signal edge, and controls the operation of the precharge circuit of the data line that transmits the data of the memory cell array, the equalization circuit 5, the data amplification circuit 7, and the output circuit 8. During standby, this signal becomes H level, precharging and equalizing the data line, and stopping the operation of 7.8. A pulse signal generating circuit 3 is provided so that when C3 is at H level, CSB is at H level and CTL is kept at H level, and the operation is performed even when the address signal Ai changes. FIG. 7 shows a specific circuit example of the selection signal generation circuit 1, the address manual buffer 7 circuit 2, and the pulse signal generation circuit 3.
C5A is address signal input N. A is connected to R20 to prevent changes in Ai from being transmitted to the inside of the circuit when it is at H level. Changes in x are detected at the falling and rising edges of the signal in step 3, and a pulse signal ATD is generated for each address. The fall of the signal is delayed through the delay circuit DB of C5BGil, which performs the logical sum of all addresses, and when it reaches the L level, the P channel MOS transistor turns ON, and the logical sum circuit of 3-2 operates. Next, the operation of the circuit shown in FIG. 6 will be explained based on the timing diagram shown in FIG. When τ茗 changes from H level to L level, C
SA becomes L level and address signal Ai is transmitted internally through address signal input N0R20. When Ai is at L level, a change occurs in the internal address signal and an ATD pulse is generated. CTL falls at the end of the ATD pulse, but even if Ai is all at H level and no ATD pulse is generated, CSB falls at the same time as the fall of the ATD pulse and is delayed, so the falling time of CTL changes. The address signal is sent to the decoder circuit, and the word line and column selection line connected to the memory cell to be selected rise.0 As is well known, the word line is connected to the memory cell and selects the memory cell in the ROW direction. The column selection line selects a data line connected to a selected memory cell. Then, the information of the memory cell appears on the data line and is output to the output terminal through the amplifier circuit and the output circuit. Further, when Ai changes while C5 remains at L level, an ATD pulse is generated, CTL becomes H level, data lines are precharged and equalized, and reading from the next address is performed. [Problems to be Solved by the Invention] Since the conventional semiconductor memory device has the above configuration, the timing of CS access when the address signal is at L level is such that the address input is performed when C8 changes and CSA falls. The output of N0R20 changes. In the case of CS access, access will start from this point. on the other hand,
In the case of address access, since τSA is already at the L level, the output of N0R20 changes when the address signal changes, and access is started. Therefore, from C3 to C
The C100 access was slower than the address access due to the time required for the signal to reach the SA. In the case of a τ million access, the data line is originally in a precharged and initialized state, and the access is started from this state, so there are no restrictions on increasing the startup speed of the word line and column selection line. The faster it can be made, the better. Therefore, in the conventional example, the fall of C3B is accelerated, and AT
It is conceivable to try to narrow the width of the D pulse and increase the operating speed of the address manual buffer and decoder circuit. However, according to the conventional example, when the ATD pulse is narrowed, the CTL pulse width is also narrowed. However, in the case of address access, data from the previous cycle remains on the data line, so unless the data line is reset by precharging and equalizing for a sufficient period of time using CTL, the next selected memory cell will be erroneously selected. There is a risk that the stored data will be written and the stored data will be destroyed. Furthermore, if the operation of the data amplification circuit and output circuit is simply inhibited for a short period of time using CTL, the amplification circuit will operate before sufficient data appears on the data line, causing malfunctions due to noise and conversely reducing access time. You will be late. Therefore, in the conventional example, the width of the ATD pulse is narrowed and C
Speeding up S access causes problems in address access, so it has not been possible to speed up CS access by narrowing the width of the ATD pulse. The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device that achieves high-speed CS access time while maintaining stable address access operations. [Means for Solving the Problems] (1) The semiconductor memory device of the present invention includes a selection signal generation circuit that includes a chip selection signal terminal and generates an internal selection signal with a delay with respect to the chip selection signal, and a change in address signal. a pulse generation circuit that detects and generates a pulse signal; and a pulse width conversion circuit that receives the pulse signal and converts the pulse width; It is characterized in that it includes a first logic gate that provides a delayed signal of a pulse signal, and a second logic gate that performs a logical sum of the output of the first logic gate and the pulse signal. (2) The above [1] semiconductor memory device includes a selection line control circuit that generates a selection line control signal, and the selection line control circuit outputs the pulse signal when the internal selection signal is in the selected state. The word line or column selection line is characterized in that activation is controlled by the selection line control signal. [Examples] Examples of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a semiconductor memory device of the present invention, and FIG. 5 is a timing diagram explaining the circuit operation of FIG. 1. C
8 is a signal inputted from the chip selection signal terminal of the semiconductor memory device, which indicates a chip non-selected state when it is at H level and indicates a chip selected state when it is at L level 6 Selection signal generation circuit 1
is sent to the C line control circuit 10. Pulse signal generation circuit 3
The output CTLI is input to 9.10, and the precharge circuit, equalization circuit 5, data amplification circuit 7, and output circuit 8
is controlled by the operation control signal CTL2 output from 9. Also, the word line and column selection line are the address signal A.
selected by the decoder circuit 4 for decoding i, and 1
Activation and deactivation are controlled by a selection line control signal WCTL having an output of 0. Further, the selection signal generation circuit 1 is connected to the C3 as in the conventional example shown in FIG.
However, the delay of the delay circuit DB is set short so that the fall of CSB is faster than in the conventional case. The basic configuration of the address manual buffer circuit 2 is the same as that of the conventional example shown in FIG. 7, but the transistor size is made large to enable high-speed operation. Pulse signal generation circuit 3
The basic configuration is the same as the conventional example Fig. 7, but the ATD
Reduce the number of inverter stages to shorten the pulse width (
FIG. 2 is a circuit diagram showing an embodiment of the selection signal generation circuit 1, pulse width conversion circuit 9, and selection line control circuit 10 of the present invention. CSC is one delay circuit. The fall of the signal is delayed through DC2.When C3C is at H level at 9, CT
LI level is N. It is output as CTL2 through R91 and inverter 92. However, when C8C is at L level, CTLl is N0R.
91 and a 3-stage inverter and N0R90
Since the logical sum is performed at 91 via , a total of 4
The output of 90 is delayed by the time it passes through the gate of the stage, and C
TL2 appears as a signal with a long pulse width corresponding to the delayed time. CTL2 is a control signal that precharges and equalizes the data line when at H level, and inhibits data amplification and output. The pulse width of CTL2 when changing the address needs to be sufficiently long to prevent malfunctions, and must be set to the same extent as the pulse width of ATD and CTL in the conventional example. Since this pulse is shortened, the pulse width conversion circuit 9 increases this pulse width. That is, 9 is C3C
The pulse width is lengthened during address access when CSC is at L level, and CTL is increased during CS access when CSC is at H level.
2 is made to fall at high speed without delay. In addition, in the selection line control circuit 10, when C8C is at H level, WCTL remains at L level, and when C8C is at L level, CTTL remains at L level.
LI is output through NANDloo and inverter 101. That is, when C3C is at H level, precharging and equalization are only performed for a short period of time, and the word line and column selection line are not inactivated by WCTL.
When CSC is at the L level, a long precharge and equalization period is performed by the long pulse of CTL2, and the word line and column selection line are temporarily inactivated by WCTL to prevent malfunction at the time of address change. FIG. 3 is a circuit diagram showing another embodiment of the pulse width conversion circuit 9 and the selection line control circuit 10. In FIG. 3, when the IC chip is in a non-selected state, that is, when C3 is at H level, CTL2 must be at H level in order to perform precharging and equalization, and the word line and column selection line must fall. Therefore, WCTL must be at H level at °°1, and at 9,
Input CSB to N0R93, and inverter 10 at lO.
rNAND103+, :CSA is input via 2. This eliminates the need to input Te1B to 3 and input τSA to 4 as shown in FIG. That is, in FIG. 1, 8000 is input to the pulse signal generation circuit 3 and CTLI is controlled by CSB, but in FIG. 3, CSB is input together with CTLI to N0R93 and C3
The control by B is performed at 9. Further, in FIG. 1, the decoder circuit 4 is controlled by the C5A, but in FIG. 3, the WCTL also serves as the control of the decoder circuit by the C5A. Therefore, in the case of Figure 3, WCTL remains at H level until CSA falls.
The operation of the decoder circuit is prohibited. The fourth section is a circuit diagram showing an embodiment of the decoder circuit 4 of the present invention. In order to deactivate all word lines by WCTL, a signal is inputted from WCTL to the decoder N''A N rj40 through an inverter 41.WCTL
When is at H level, all outputs of the NAND 40 are at H level, so all word lines Wi are at L level. The same technique is used for column selection lines. Next, the operation of the circuit shown in FIG. 1 will be explained based on the timing diagram shown in FIG. When C3 is at H level, the chip is in a non-selected state, and at this time, τ100A, CSB, and C3C are all at H level. When (2) becomes L level and a selection state is indicated, CSA first becomes L level, and the address signal At is transmitted internally via the address human power buffer 7 circuit 20, and an ATD pulse is generated in the pulse generation circuit 3. . However, since CSB remains at H level, AT
Even if a D pulse is generated, CTLI does not change and remains at H level. When CTLI is at H level, CTL2 is also at H level, and CTL2 causes the precharge circuit and equalize circuit 5 to precharge and equalize the data line, and the data amplifier circuit 7 and output circuit 8 are prohibited from operating. It is in. CTLI falls in response to the falling of C3B. Since C8C is still at H level at the falling edge of CTLI, all inputs to N0R91 and 93 become L level as a result, and CTL
2 also falls according to CTL1. This completes precharging and equalization, and the amplifier circuit and output circuit operate. At this time, wcTL remains at L level, so NAND 40 in FIG. 4 is not restricted by WCTL. Therefore, the output of address manual buffer circuit 2 is decoded by decoder circuit 4, and a word line is selected. Similarly, the column selection line is also selected. Therefore, the level of the word line is determined by the address buffer 2 and the decoder circuit 4.
rises according to the operating speed of the memory cell and selects the memory cell. After that, it becomes L level. After data is read from a certain address, when Ai changes and address access starts, an ATD pulse is generated in the pulse signal generation circuit 3, and CTLI
The A TD field also changes accordingly and becomes an H level pulse. At this time, since CSC and CSB are already at the L level, the pulse width conversion circuit 9 is activated, and the rising edge of the CTLI pulse appears as the rising edge of CTL2 via N0R91 or 93. On the other hand, the falling edge of the CTLI pulse is delayed through a three-stage inverter and N0R90, and N0R90 is delayed.
It is input to 91 and 93. Therefore, the fall of CTL2 is delayed. In other words, as is clear from FIG. 5, the CTL1 pulse is converted into a long CTL2 pulse. At this time, the selection line control circuit 10 also operates and a pulse appears on WCTL. As shown in FIG. 4, when WCTL becomes H level, all NANDs 40 output H level, and thereby all word lines Wi become L level. Since the word line selects a memory cell at H level, all word lines are temporarily in a non-selected state when the address changes. As a result, memory cells are not selected when the address changes and the inside of the chip is in a fluctuating state, thereby improving eccentricity. As is clear from Fig. 5, CTL2 changes when there is an at/res change.
Since the pulse is long, when comparing the time from the rise of the ATD pulse to the end of access, CS access is shorter than address access. In order to prevent malfunctions in address access, the pulse width of CTL2 must be the same as the conventional one.
The pulse width of CTL2 when the address changes in the figure is compared to the conventional CT.
Set to the same level as L, and reduce the width of the ATD pulse,
The operation of the address manual buffer 7 circuit and the decoder circuit is accelerated, and CSB falls quickly. Therefore, compared to the conventional CS access, in the present invention, C3H falls quickly and the ATD pulse is short. Precharge and equalization finish quickly. Here address human power buffer 7 circuits,
If the operation speed of the decoder circuit is increased, the CS access speed will be increased accordingly. On the other hand, during address access, a short ATD pulse is converted into a sufficiently long pulse, so precharging and equalization of the data lines are reliably performed and no malfunction occurs. [Effects of the Invention] As described above, the present invention can speed up access during CS access while ensuring sufficient precharge and equalization periods during address access. At the time of CS access, the rising speed of the signal on the word line and column selection line is accelerated by speeding up the operation of the address manual buffer 7 circuit and the decoder circuit. In addition, the data line precharge and equalization are immediately terminated and the amplifier circuit is activated. Since the output circuit starts operating, the entire circuit can operate at high speed when the word line and column selection line rise. Furthermore, a sufficient precharge and equalization period can be secured during address access, and the word line and column selection line are raised after the data line has stabilized, so the data in the memory cell can be stabilized without being destroyed. amplify,
Output is done. Further, at the time of this address access, all word lines are temporarily inactivated, so that no malfunction occurs at the time of access. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor memory device of the present invention, FIG. 2 is a circuit diagram showing an embodiment of a pulse signal generation circuit, a pulse width conversion circuit, and a selection line control circuit, and FIG. 3 is a pulse width conversion circuit and selection line control circuit. FIG. 4 is a circuit diagram showing another embodiment of the line control circuit, and FIG. 4 is a circuit diagram showing an embodiment of the decoder circuit. FIG. 5 is a timing chart showing the operation of the semiconductor memory device of the present invention. FIG. 6 ÷ D←→, b ( is a block diagram of a conventional semiconductor memory device, and FIG. 7 is a circuit diagram showing a conventional example of a selection signal generation circuit, an address manual buffer circuit, and a pulse signal generation circuit. Fig. 8 is a timing diagram showing the operation of a conventional semiconductor memory device. Applicant: Seiko Epson Co., Ltd. Agent: Suzumi Tsuchi, Patent Attorney, Ki 13 Department (1 person) Fig. 4 Fig. 5

Claims (9)

[Claims] (1) In a semiconductor memory device to which a chip selection signal is input, a signal generation circuit generates an internal selection signal with a delay with respect to the chip selection signal, and a pulse generator detects a change in an address signal and generates a pulse signal. circuit, and a pulse width conversion circuit that inputs the pulse signal and outputs a control signal for precharging or equalizing data lines of a memory cell array, and the pulse width conversion circuit is configured to input the internal selection signal when the internal selection signal is in a chip selection state. 2. A semiconductor memory device, wherein the control signal is outputted having a pulse obtained by converting the pulse width of the pulse signal to a longer value when the pulse width is longer than the pulse width of the pulse signal. (2) The pulse width conversion circuit is characterized in that when the internal control signal is in a chip non-selected state, the output of the control signal ends substantially in synchronization with the end of the pulse of the pulse signal. 1. The semiconductor storage device according to 1. (3) The semiconductor memory device according to claim 1, wherein the control signal is a signal that precharges and equalizes data lines of the memory cell array and inhibits operations of a data amplification circuit and an output circuit. (4) The pulse width conversion circuit includes a first logic gate that outputs a delayed signal of the pulse signal when the internal selection signal is in a selected state, and a logic between the output of the first logic gate and the pulse signal. 2. The semiconductor memory device according to claim 1, further comprising a second logic gate that performs the sum and outputs the control signal. (5) a selection line control circuit that generates a selection line control signal; the selection line control circuit includes a third logic gate that outputs the pulse signal as the selection line control signal when the internal selection signal is in a selected state; 2. The semiconductor memory device according to claim 1, wherein activation of a word line or a column selection line of the memory cell array is controlled by the selection line control signal. (6) The word line is connected to a gate of a transistor that connects a memory cell to a data line, and the column selection line is connected to a gate of a transistor that connects a data line to a data amplification circuit. 5. The semiconductor memory device according to 5. (7) In a semiconductor memory device equipped with a chip selection signal terminal, a signal generation circuit generates an internal selection signal with a delay with respect to a chip selection signal from the signal terminal, and a signal generation circuit generates a pulse by detecting a change in an address signal. The pulse width conversion circuit includes a pulse generation circuit that generates a signal, and a pulse width conversion circuit that inputs the pulse signal and outputs a control signal that controls the operation of the memory cell array, and the pulse width conversion circuit is configured to convert the internal selection signal into a chip selection state. a first logic gate that outputs a delayed signal of the pulse signal when shown, and a second logic gate that ORs the output of the first logic gate and the pulse signal to form the control signal. A semiconductor memory device characterized by: (8) A selection line control circuit that generates a selection line control signal, the selection line control circuit generating a second control signal that deactivates the word line or column selection line when the internal selection signal is in the selection state. 8. The semiconductor memory device according to claim 7, wherein the semiconductor memory device outputs . (9) The semiconductor memory device according to claim 7, wherein the first logic gate is prohibited from outputting the delayed signal of the pulse signal when the internal selection signal indicates a chip non-selected state.