JPH02302120A - Pulse stretcher circuit - Google Patents

Abstract

PURPOSE:To obtain an output pulse proportional to a control pulse resulting from turning on/off a constant current source by decreasing a current IBC flowing from a 1st input terminal to the collector via the base of a 1st transistor(TR) while the 1st input terminal is at a high level and its output is at a high level. CONSTITUTION:The base of a 3rd TR Q3 (PNP) is provided between the collector of a 1st TR Q1 and a 1st connecting point X, its emitter is connected between a 1st input terminal connecting to the base of the 1st TR Q1 and the base of the 1st TR Q1 and its collector is connected to ground. Thus, when an output terminal is at a high level and a 1st input terminal is at a high level, the current flowing from the base of the 1st TR Q1 to a capacitor C via the collector is decreased. Thus, an output pulse width with high accuracy nearly proportional to the control pulse width resulting from turning on/off the constant current source is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a double integration circuit used in a D/A converter.

[Conventional technology]

Figure 4 is a circuit diagram of a pulse stretcher circuit that applies a double-integrator circuit used in a conventional D/A converter.
The figure is a waveform diagram showing the signals of each part of the circuit of Figure 4, and Figure 6 is a waveform diagram showing the signal of each part of the circuit of Figure 4, and Figure 6 is a waveform diagram of the circuit of Figure 4 when input pulses are periodically input continuously and the output pulse duty is close to 100%. FIG. 3 is a waveform diagram showing signals of each part.

In the figure, (1) is a current switch circuit, (2) is a voltage comparator, (3) is a reference voltage source, (4) is a first constant current source,
(5) is the second constant current source, (6) is the first transistor, (
7) is a second transistor, (9) is a resistor, q is a capacitor, αυ is a first input terminal, 4 is a second input terminal, and α4 is an output terminal.

This pulse stretcher circuit is a current switch circuit (
1), voltage comparator (2) and integrating capacitor αI
It is equipped with c. The current switch circuit (1) consists of a first transistor (6) Ql and a second transistor (7) Q2 of NPN type arranged in a differential type, and the base of the first transistor (6) Ql (ζ is a pulse The first input terminal Qυ to which the signal P1 is input is connected, and the second transistor (
7) A reference voltage source (3) is connected to the base of Q2, and the collector of the second transistor (7) Q2 is connected to the power supply Vcc. On the other hand, voltage comparator (2)
One inverting input terminal (→ is an integrating capacitor a (
jC and the collector of the first transistor (6) Ql is connected to the first connection point X, and the other non-inverting input terminal (±) of the voltage comparator (2) is connected to the first transistor (6).
A second connection point Y connecting both emitters of Ql and second transistor (7) Q2 is connected, and this second connection point Y is grounded via a resistor (9) R1.

Further, a first constant current source (4) is connected between the first connection point X and the source Vce, and a second constant current source (5) is connected between the first connection point X and the ground.
) are respectively provided, and the second constant current source (5) is provided with a second input terminal □□□ to which a control signal (P2) for controlling on/off of the second constant current source (5) is input.

Next, the operation will be explained with reference to FIG.

Figure 5 shows the input waveform of the /f pulse signal P1 input from the first input terminal αυ, the input waveform of the control pulse P2 input from the second input terminal @, and the first connection point X by the integrating capacitor Cl0C. voltage waveform Vc at , and pulse waveform P3 output from the output terminal reserve of the voltage comparator (2).
are shown respectively. Note that the control pulse P2 applied to the second input terminal (6) is the same as the pulse signal P1 and a predetermined pulse width T that is preset externally. This is the signal obtained from the difference from a reference pulse (not shown) having .

(1) Period time t of io-tl. f, when a pulse signal Pi of /'1 level is input to the first input terminal Q ring, the first transistor (6) Ql of the current switch circuit (1) becomes conductive, and the accumulation in the integrating capacitor αOC occurs. The charge and the current from the first constant current source (4) flow into the first transistor (6) Ql, and the potential Vc of the first connection point X gradually decreases. Then, at time 1. immediately before the control pulse P2 is input. Then, the first transistor (6) Ql is saturated. Therefore, the capacitor α1ccp potential Vc at this time t1 is equal to the comparison potential Vref i at the second connection point Y and the first transistor (6) Q
The sum of the emitter-collector voltage V3 of l (Vc
=Vref +Vs, where Vref = voltage of reference voltage source (3) Vreg + 2nd upper second transistor Q2
(base/emitter voltage). In this case, ■(=
Vref, the output of the voltage comparator (2) remains at low level.

(2) Period j1 to t2 When a high-level control pulse P2 is input to the second input terminal (b) at time t1, the second constant current source (5) is turned on and operation is started. As a result, the current drawn by the second constant current source (5) increases more than that of the first constant current source (4), so the potential Vc of the first connection point X decreases linearly. Therefore, the inverted input voltage (c) of voltage comparator (2)
becomes below Vref, and as a result, the output pulse of the voltage comparator (2) becomes high level.

(3) During the period tx to t3, the input signals of the first input terminal aυ and the second input terminal Α are both low level, so the current switch circuit (
The first transistor (6) Ql of 1) is non-conductive, and
The second constant current source (5) stops operating. Therefore, charging of the capacitor αOC is started, and the potential V at the first connection point
c gradually increases. In this case, until time t3, the potential Vc of the first connection point X is lower than the comparison voltage Vref, so the output of the voltage comparator (2) remains at a high level until time t3.

Next, referring to FIG. 6, a case will be described in which input pulses are periodically and continuously inputted and the output pulse duty becomes close to 100%.

As the high-level pulse signal P1 at the first input terminal αυ becomes longer from time t0 to t2, the output pulse length also becomes longer by a certain factor. Consider a case where the next high-level pulse signal P1 is input to the first input terminal Qυ when the output pulse is in a high-level state.

During the to% t4 period, the capacitor αOC is charged and discharged according to (1), (2), and (3) above.

During the period t4 to js, the first transistor (6) Ql
We will describe the operation of. The emitter potential (second connection point Y) of the first transistor (6) Ql is Vref, the collector potential is Vc, and the base potential is Vc + VBC! It becomes. (Here, VBO is the first transistor (6, IQI
It shows the base-collector voltage of . ] In this case, Vre
f) Vc, so the first transistor (6) Ql
The transistor is not operating, and current (IBO) flows from the base to the collector, charging the capacitor QOC. Therefore, the current charged to the capacitor C1OC is the current Em from the first constant current source (4) and the current IBO.
is the sum of In other words, 1 total = IA + IBO
It is.

[Problem to be solved by the invention]

Since the conventional pulse stretcher circuit is configured as described above, the current value charged in the capacitor C changes during the period when the output pulse overlaps with the next high-level pulse signal P1 of the first input terminal. , (Em increases to Im+IBO) A problem arises in that the output pulse length cannot be obtained at a constant magnification with respect to the input pulse length.

This invention was made to solve the above-mentioned problems, and its purpose is to obtain a pulse stretcher circuit that can obtain an output pulse proportional to a control pulse that turns on and off a constant current source. do.

Means to solve problems] In order to achieve the above object, the present invention has the following configuration.

(1) A base is provided between the collector of the first transistor and the first connection point X, and an emitter is provided between the first input terminal connected to the base of the first transistor and the base of the first transistor, Now, install a third transistor whose lid is grounded.

(2) A base is provided between the first transistor collector and the first connection point X, an emitter is provided between the first input terminal connected to the base of the first transistor and the base of the first transistor, and the collector A third transistor is provided which is grounded, and the emitter of the third transistor is connected to the first transistor.
A resistor is provided between the base of the transistor and the base of the transistor.

[Effect]

The pulse stretcher circuit according to the present invention reduces the current (IBO) flowing from the first input terminal toward the collector via the base of the first transistor Q1 during a period when the first input terminal is at a high level and the output is at a high level. be able to.

〔Example〕

Fig. 1 is a circuit diagram of a pulse stretcher circuit according to an embodiment of the present invention, Fig. 2 is a waveform diagram showing signals of each part of the circuit of Fig. 1, and Fig. 3 is a manual pulse of the circuit of Fig. 1. It is a graph showing output duty characteristics.

In the figure, (2) to (7) and (9) to Zeng are the same as those shown in the conventional example of FIG. 4, so their explanation will be omitted.

(8) is a PNP type third transistor.

The features of this embodiment are as follows: (A) The base of the third transistor (8) (PNP type) is provided between the collector of the first transistor (6) Ql and the first connection point X; 6) Ql
An emitter is provided between the first input terminal αυ connected to the base of the transistor (6) and the base of the first transistor (6) Ql, and the collector is grounded.

(B) As a third transistor (8) (P N P type), a base is provided between the collector of the first transistor (6) Ql and the first connection point X, and the first transistor (6) Ql
An emitter is provided between the first input terminal qυ connected to the base of the transistor (6) and the base of the first transistor (6) Ql, and the collector is grounded.
A resistor (9) R2 is provided between the emitter of Q3 and the base of the first transistor (6) Ql.

Next, the operation of the pulse stretcher circuit having the above configuration will be explained with reference to the waveform diagram shown in FIG.

(1) period to = in, period t1 to t2, t
Periods 2 to t4 The operations during these periods are the same as in the conventional example, and therefore the description thereof will be omitted.

(:21 period from t4 to t) During this period, if the output terminal (14 is at high level and the first input terminal (1υ is high 1 novel), the first
Most of the current that is charged to the capacitor QqC from the base of the transistor (6) Ql via the collector is (A) the third
The current flows to the ground through the transistor (8) Q3, and the current flowing into the collector of the first transistor (6) Ql can be reduced.

When the output terminal q4 changes from high level to low level, the circuit operates in the same way as the conventional circuit.

(B) Resistor (9) R2 and third transistor (8)
Q3 allows the current to flow to ground, thereby reducing the current flowing into the collector of the first transistor (6) Ql. When the output end reserve changes from high level to low level, it operates like a conventional circuit.

〔Effect of the invention〕

As described above, according to the present invention, (A) the first transistor Q3 (PNP type)
A base is provided between the collector of the transistor Ql and the first connection point X, an emitter is provided between the first input terminal connected to the base of the first transistor Q1 and the base of the first transistor Q1; 1/Since I grounded Kuta,
When the output terminal is at a high level and the first input terminal is at a high level, the current flowing from the base of the first transistor Q1 to the capacitor C via the collector can be reduced. Therefore, it is possible to obtain a highly accurate output pulse width that is approximately proportional to the control pulse width for turning on and off the constant current source, and it is possible to configure a highly accurate pulse stretcher circuit.

(B) The first transistor Q3 (PNP type)
A base is provided between the collector of the transistor Q1 and the first connection point X, an emitter is provided between the first input terminal connected to the base of the first transistor Q1 and the base of the first transistor Q1, and the collector is grounded, and the emitter of the third transistor Q3 and the first transistor Q1
Since the resistor R2 is provided between the base of the first transistor Q1 and the base of the first transistor Q1, when the output terminal is at high level and the first input terminal is at high level, the current flowing from the base of the first transistor Q1 through the collector to the capacitor "C" is reduced. Therefore, it is possible to obtain a highly accurate output pulse width that is approximately proportional to the control pulse width that turns the constant current source on and off.
A highly accurate pulse stretcher circuit can be constructed.

Figure 3 shows the input pulse vs. output duty characteristics. Fourth
In the conventional circuit shown in the figure, as the output duty approaches 100%, the linearity deteriorates and the input pulse becomes tl.
The output duty becomes 100%. On the other hand, when looking at the improved characteristics of the circuit of this invention, it becomes clear that the linearity is extremely improved. In this case, the output duty is 100% when the input pulse is tb.

As described above, according to the present invention, the linearity of the output duty with respect to the input pulse is extremely improved. Note that the graph indicated by the dotted line in the figure is the characteristic of the conventional circuit.

[Brief explanation of drawings]

Figures 1 to 3 show one embodiment of the present invention.
The figure is the circuit diagram of the pulse stretcher circuit, and Figure 2 is the circuit diagram of the pulse stretcher circuit.
FIG. 3 is a waveform diagram showing signals of various parts of the circuit shown in the figure, and FIG. 3 is a graph showing input pulse versus output duty characteristics of the circuit shown in FIG. Figure 4 is the circuit diagram of the pulse stretcher circuit, Figure 5
, and FIG. 6 are waveform diagrams showing signals of various parts of the circuit of FIG. 4. In the figure, (2) is a voltage comparator, (3) is a reference voltage source, (4) is a first constant current source, (5) is a second constant current source, and (6) is a reference voltage source.
) is the first transistor, (7n is the second transistor, (
8) is the third transistor, (9) is the resistor, QO is the capacitor, Qυ is the first input terminal, @ is the second input terminal, (to)
is the output terminal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) Equipped with a current switch circuit consisting of first and second transistors arranged differentially, a voltage comparator, and an integrating capacitor, and the base of the first transistor has an input terminal for a pulse signal. A reference voltage source is connected to the base of the second transistor, and a first connection point connecting the integrating capacitor and the collector of the first transistor is connected to one input terminal of the voltage comparator. , a second connection point connecting the emitters of the first and second transistors is connected to the other input terminal of the voltage comparator, and while this second connection point is grounded via a resistor, 1
A first constant current source is provided between the connection point and the power supply, and a second constant current source is provided between the first connection point and the ground, and the second constant current source is turned on and off. In a pulse stretcher circuit provided with a second input terminal for a control signal for off-control, the first transistor is used as a third transistor.
A base is provided between the collector of the transistor and the first connection point, and the first transistor is connected to the base of the first transistor.
A pulse stretcher circuit characterized in that an emitter is provided between an input terminal and a base of a first transistor, and a collector is grounded. (2) Equipped with a current switch circuit consisting of first and second transistors arranged in a differential type, a voltage comparator, and an integrating capacitor, and the base of the first transistor has an input terminal for a pulse signal. A reference voltage source is connected to the base of the second transistor, and a first connection point connecting the integrating capacitor and the collector of the first transistor is connected to one input terminal of the voltage comparator. A second connection point connecting the emitters of the first and second transistors is connected to the other input terminal of the voltage comparator, and while this second connection point is grounded via a resistor, A first constant current source is provided between the connection point and the current, and a second constant current source is provided between the first connection point and the ground, and the second constant current source is turned on and off. In the pulse stretcher circuit provided with a second input terminal for a control signal for off-control, a base is provided as a third transistor between the collector of the first transistor and the first connection point, and the base of the first transistor is connected to the base of the first transistor. An emitter is provided between the connected first input terminal and the base of the first transistor, the collector is grounded, and a resistor is provided between the emitter of the third transistor and the base of the first transistor. Pulse stretcher circuit.