JPH11112315A - Insensitive comparator circuit - Google Patents

Abstract

(57) Abstract: An object of the present invention is to provide a non-sensitive comparator circuit that suppresses variation in non-sensitive time due to temperature fluctuation or mixing of disturbance noise. SOLUTION: A first comparator 10 for comparing a voltage to be compared with a first reference voltage, a capacitor C charged with a predetermined time constant according to an output of the first comparator, and a voltage charged in the capacitor Is compared with a second reference voltage, and output circuits Q5 and Q7 that output signals of a level corresponding to the output of the second comparator. Has a sensitive time. Thus, the provision of the second comparator makes it possible to increase the logic amplitude of the switching of the output signal as compared with the conventional one, and to suppress variations in the insensitive time due to temperature fluctuations and mixing of disturbance noise. Can be.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insensitive comparator circuit, and more particularly to a comparator circuit having an insensitive time, that is, a delay time when switching.

[0002]

2. Description of the Related Art Conventionally, there is an insensitive comparator circuit which has an insensitive time, that is, a delay time at the time of switching, and is used for a reset circuit with a delay or the like. FIG. 5 shows a circuit diagram of an example of a conventional insensitive comparator circuit. This circuit is a circuit that detects that the power supply voltage V _CC has become equal to or lower than a predetermined value and generates a signal used for resetting and the like.

In FIG. 1, a constant regulator output voltage V_S
The resistors R1 and R2 are connected between the
From the connection point of R1 and R2_SReference voltage V obtained by dividing
_REFIs output to the inverting input terminal of the comparator 10.
Supplied. Also, the power supply voltage V _CCAnd a resistor R between
3 and R4 are connected, and are the connection points of the resistors R3 and R4
Voltage V_CCV divided from_PIs taken out and compared
Is supplied to the non-inverting input terminal of the data 10.

[0004] The output terminal of the comparator 10 is connected to the base of npn transistor Q1, the collector of the npn transistor Q1 is applied to the regulator output voltage V _S via a resistor R6, the emitter is grounded.
The collector of the npn transistor Q1 is connected to the bases of the npn transistors Q2 and Q3 and the external terminal 12 respectively.
It is connected to the. The npn transistor Q2 has an emitter grounded and a collector connected to a non-inverting input terminal of the comparator 10 via a resistor R5. The emitter of npn transistor Q3 is grounded and the collector is connected to the output terminal 14 is connected to a terminal that is applied to the regulator output voltage V _S through a resistor R7. The external terminal 12 is grounded via an external capacitor C.

Here, the power supply voltage V_CCIs high, the voltage
V_P[V_P= V_CC[R4 / (R3 + R4)] is the reference voltage
V_REFHigher, the npn transistor Q1 is on
And the capacitor C is in a discharged state, and the npn transistor
The signal output from the output terminal 14 because the
Is high level. Next, the power supply voltage V_CCIs the solid line in FIG.
As shown by the solid line II in FIG._PBut
Reference voltage V_REFIs less than the output of the comparator 10
Becomes low level, and the npn transistor Q1 is turned off.
The capacitor C is charged with the time constant C · R6, and the npn
Base voltage V of transistor Q3_AIs shown by the solid line III in FIG.
To rise. Then, the insensitive time (delay time) T_D
Later, the voltage V_AIs the voltage V_BE(V _BEIs an npn transistor
Exceeds the base-emitter forward drop voltage).
The pn transistor Q3 turns on and the output from the output terminal 14
The power signal switches to low level and the npn
The transistor Q2 turns on and the voltage V_PIs V_P= V_CC・ (R4
.R5) / [(R4.R5) + R3. (R4 + R5)]
To give hysteresis.

[0006]

In a conventional circuit,
When the charging voltage (voltage V _A ) of the capacitor C exceeds the logical amplitude V _BE of the npn transistor Q3, the npn transistor Q3 switches. However, since the logical amplitude V _BE is as low as about 0.6V, temperature fluctuations occur. or fluctuate logic amplitude V _bE of the npn transistor Q3 in the variation of the unresponsive time T _D is increased when the disturbance noise is mixed in the voltage V _a, can take a desired dead time (delay time) There was a problem that it might disappear.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a non-sensitive comparator circuit that suppresses variations in non-sensitive time due to temperature fluctuations and disturbance noise.

[0008]

According to a first aspect of the present invention, there is provided a first comparator for comparing a voltage to be compared with a first reference voltage, and a predetermined time constant according to an output of the first comparator. , A second comparator for comparing the voltage charged in the capacitor with a second reference voltage, and an output circuit for outputting a signal of a level corresponding to the output of the second comparator. And a dead time corresponding to a charging time constant of the capacitor.

As described above, by providing the second comparator, the logic amplitude of the switching of the output signal can be made larger than that of the conventional one, and the variation of the insensitive time due to the temperature fluctuation and the mixing of disturbance noise can be reduced. Can be suppressed. According to a second aspect of the present invention, in the insensitive comparator circuit according to the first aspect, at the time of switching of the signal output from the output circuit, the division ratio of the voltage to be compared is changed and supplied to the first comparator. It has a pressure ratio variable circuit.

As described above, the output of the first comparator is stabilized by changing the voltage dividing ratio of the voltage to be compared and giving the first comparator hysteresis. According to a third aspect of the present invention, in the insensitive comparator circuit according to the second aspect, a hysteresis is provided by changing a second reference voltage of the second comparator when a signal output from the output circuit is switched.

As described above, by providing the second comparator with hysteresis, the output of the second comparator is stabilized.

[0012]

FIG. 1 shows an insensitive comparator according to the present invention.
FIG. 3 is a circuit diagram of a first embodiment of the data circuit. This circuit is
Pressure V_CCResets when it is detected that
This is a circuit for generating a signal used for. In the figure,
Regulator output voltage V_SAnd resistors R1 and R2 between
And a voltage V from the connection point of the resistors R1 and R2._S
Reference voltage V obtained by dividing _REFIs taken out of the first
It is supplied to the inverting input terminal of the comparator 10. Also,
Power supply voltage V_CCAnd resistors R3 and R4 are connected between
And the voltage V from the connection point of the resistors R3 and R4._CCWas divided
Voltage V_P1Is taken out and the non-inverting input of the comparator 10 is obtained.
It is supplied to the terminal.

The output terminal of the comparator 10 is connected to the base of an npn transistor Q1, the collector of the npn transistor Q1 is connected to one end of a resistor R16,
The other end of the resistor R16 is applied to the regulator output voltage V _S via a resistor R17. npn transistor Q1
Are grounded. Further, resistors R16 and R1
The connection point 7 is connected to the inverting input terminal of the second comparator 20 and to the external terminal 12. The external terminal 12 is grounded via an external capacitor C.

The resistors R18 and R19 are connected between the regulator output voltage V _S and ground, and the resistors R18 and R1 are connected.
9, the second reference voltage V _{P2 obtained by} dividing the voltage V _S from the connection point 9
Is supplied to the non-inverting input terminal of the comparator 20. The output terminal of the comparator 20 is connected to the base of the npn transistor Q5. The npn transistor Q5 has an emitter grounded, and the npn transistor Q5
The collector 5 is connected to a terminal that is applied to the regulator output voltage V _S via a constant current source 22, also the collector is connected to the npn transistor Q6, Q7 respective base. The npn transistor Q6 has a multi-collector configuration, the emitter is grounded, and the first
The collector is connected to the non-inverting input terminal of the comparator 10 via the resistor R5, and the second collector is connected to the non-inverting input terminal of the comparator 20 via the resistor R20. It is needless to say that two npn transistors whose bases are connected in common may be used instead of npn transistor Q6.

The emitter of the npn transistor Q7 is grounded, the collector is connected to the output terminal 14, and is connected via a resistor R21 to the terminal to which the regulator output voltage V _S is applied. The above npn transistor Q
5, Q7, constant current source 22, and resistor R21 form an output circuit, and include an npn transistor Q6, a resistor R3,
R4 and R5 form a voltage division ratio variable circuit.

Here, the power supply voltage V_CCIs high, the resistance
Voltage V at the connection point between R3 and R4_P1[V _P1= V_CC・ R4 /
(R3 + R4)] is the reference voltage V_REFHigher, np
The n-transistor Q1 turns on and the capacitor C discharges.
State. By the way, at this time, the resistors R16 and R17
Voltage V at the connection point_M2[V_M2≒ V_S・ R16 / (R17 +
R16)] and the voltage V at the connection point between the resistors R18 and R19._P2
[V_P2= V_SR19 / (R18 + R19)] is V
_M2<V_P2The resistors R16 to R19 are selected so that
I have. As a result, the npn transistor Q5 is turned on,
Base voltage V of npn transistor Q7_AIs almost zero voltage
V, the npn transistor Q7 turns off, and the output terminal
The signal output from the child 14 is at a high level.

Next, when the power supply voltage V _CC decreases as shown by the solid line I in FIG. 2 and the voltage V _P1 shown by the solid line II in FIG. 2 becomes lower than the reference voltage V _REF , the output of the comparator 10 becomes low level, The npn transistor Q1 turns off, the capacitor C is charged with the time constant C · R17, and the resistors R16 and R1
Voltage V _M2 at the connection point between 7 rises as shown by a solid line III in FIG. Then, after the insensitive time T _D , V _M2 > V _P2 , the npn transistor Q5 is turned off, the base voltage _VA of the npn transistor Q7 becomes the voltage V _BE , and n
The pn transistor Q7 turns on, and the output signal from the output terminal 14 switches to a low level.

At this time, since the npn transistor Q6 is turned on and the resistor R5 is connected in parallel with the resistor R4, the voltage V _P1 is changed from V _P1 = V _CC · R4 / (R3 + R4) to V _P1 =
V _CC · (R4 · R5) / [(R4 · R5) + R3 · (R
4 + R5)] to provide hysteresis. At the same time, to the resistor R20 in parallel with the resistor R19 is connected, the voltage V _P2, as shown in dashed line in FIG. 2 IV,
From V _P2 = V _S · R19 / (R18 + R19), V _P2 = V
_CC・ (R19 ・ R20) / [(R19 ・ R20) + R1
8 · (R19 + R20)] to provide hysteresis.

Thereafter, when the power supply voltage V _CC rises as shown by the solid line I in FIG. 2 and the voltage V _P1 shown by the solid line II in FIG. 2 becomes higher than the reference voltage V _REF , the output of the comparator 10 becomes high level, The npn transistor Q1 turns on, the capacitor C is discharged with a time constant C · R16, and the resistors R16 and R16
The voltage V _{M2 at} the connection point 17 decreases as shown by the solid line III in FIG. Then, V _M2 <V _P2 , the npn transistor Q5 is turned on, the base voltage _VA of the npn transistor Q7 becomes almost 0 V, the npn transistor Q7 is turned off, and the output signal from the output terminal 14 becomes high level. Switch to

At this time, since the npn transistor Q6 is turned off and the resistor R5 is separated from the resistor R4, the voltage V
_P1 rises to V _P1 = V _CC · R4 / (R3 + R4) to provide hysteresis. Along with this, because the resistor R20 is disconnected from the resistor R19, the voltage V _P2, as shown in dashed line in FIG. _{2 IV, V P2 = V S} · R19 / (R1
8 + R19) to provide hysteresis.

Here, as shown in FIG. 3, the power supply voltage V _CC
If the noise drops for a short time due to noise, the voltage _VP1 also drops, and the capacitor C is charged when the voltage is equal to or lower than the reference voltage _VREF . However, before the voltage V _M2 reaches the threshold value V _P2 of the comparator, the power supply voltage V _CC recovers and V _P1 > V
_When it becomes _REF , the charging of the capacitor C is also stopped.
The output of the terminal 14 maintains a high level. In other words, because of the unresponsive time T _D, and prevents erroneous output due to noise.

In this embodiment, the logic amplitude of the comparator 20 for determining the insensitive time T _D can be arbitrarily set by the resistors R18 and R19. Therefore, the voltage V _M2 when changes by dV, the unresponsive time is T _D1 at mixing threshold value V _P2 shown in FIG. 4 is a disturbance noise or changes by dV due to temperature variations of the logic amplitude. Whereas, if the voltage V _A is the voltage V _P at mixing only variation or disturbance noise dV by temperature fluctuations as logic amplitude in the conventional circuit is varied by dV, the unresponsive time is T _D2. That is, in the present embodiment, the fluctuation of the insensitive time due to the temperature fluctuation and the mixing of disturbance noise is significantly reduced.

[0023]

As described above, the first aspect of the present invention provides
A first comparator that compares the compared voltage with a first reference voltage; a capacitor that is charged with a predetermined time constant in accordance with the output of the first comparator; A second comparator for comparing with a reference voltage; an output circuit for outputting a signal having a level corresponding to an output of the second comparator; and a dead time corresponding to a charging time constant of the capacitor.

As described above, by providing the second comparator, it is possible to increase the logic amplitude of the switching of the output signal as compared with the conventional one, and it is possible to reduce the variation of the insensitive time due to the temperature fluctuation and mixing of disturbance noise. Can be suppressed. According to a second aspect of the present invention, in the insensitive comparator circuit according to the first aspect, at the time of switching of the signal output from the output circuit, the division ratio of the voltage to be compared is changed and supplied to the first comparator. It has a pressure ratio variable circuit.

As described above, the output of the first comparator is stabilized by changing the voltage dividing ratio of the voltage to be compared and providing the first comparator with hysteresis. According to a third aspect of the present invention, in the insensitive comparator circuit according to the second aspect, a hysteresis is provided by changing a second reference voltage of the second comparator when a signal output from the output circuit is switched.

As described above, by providing the second comparator with hysteresis, the output of the second comparator is stabilized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a circuit of the present invention.

FIG. 2 is a signal waveform diagram for explaining the circuit of the present invention.

FIG. 3 is a signal waveform diagram for explaining the circuit of the present invention.

FIG. 4 is a characteristic diagram for explaining the circuit of the present invention.

FIG. 5 is a circuit diagram of a conventional circuit.

FIG. 6 is a signal waveform diagram for explaining a conventional circuit.

[Explanation of symbols]

 Q1 to Q7 Transistors R1 to R21 Resistor C Capacitor 10, 20 Comparator 22 Constant current source

Claims (3)

[Claims] A first comparator for comparing a voltage to be compared with a first reference voltage; a capacitor charged with a predetermined time constant in accordance with an output of the first comparator; and a capacitor charged in the capacitor. A second comparator for comparing a voltage with a second reference voltage; and an output circuit for outputting a signal having a level corresponding to an output of the second comparator, wherein insensitivity corresponding to a charging time constant of the capacitor is provided. An insensitive comparator circuit having time. 2. The insensitive comparator circuit according to claim 1, further comprising a voltage dividing ratio variable circuit that changes a voltage dividing ratio of the voltage to be compared and supplies the voltage to the first comparator when a signal output from the output circuit is switched. A non-sensitive comparator circuit comprising: 3. The insensitive comparator circuit according to claim 2, wherein a hysteresis is provided by changing a second reference voltage of the second comparator when a signal output from the output circuit is switched. Insensitive comparator circuit.