JPH0230225A - Digital adaptive filter - Google Patents

Abstract

PURPOSE:To improve the echo suppression quantity by writing an echo replica with higher accuracy than an echo replica written in a main memory into a sub memory and cancelling the effect due to a residual echo included in a reception signal. CONSTITUTION:A transmission signal is shifted sequentially from a main tap section 111 and each sub tap section 121, and an address signal is supplied from the main tap section 111 to a main memory section 131 and from each sub tap section 121 to each sub memory section 141. An echo replica corresponding to an address signal to be supplied is written in the main memory section 131 and the sub memory section 141 and an echo replica with higher accuracy than the accuracy of the echo replica written in the main memory section 131 is written in the sub memory section 141. An adder means 151 uses the echo replica from the main memory section 131 and the sub memory section 141 to cancel the echo component included in the reception signal.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Examples ■, Correspondence between the Examples and FIG. 1 ■ , Configuration and operation of the embodiment (i) Configuration and operation of the echo canceller (ii) Accuracy of echo replica■, Application example of the embodiment■, Summary of the embodiment■6 Modifications of the invention Effects of the invention 1 Already required] Transmission Regarding the digital adaptive filter that cancels the echo component where a part of the signal goes to the receiving side, the purpose of reducing the memory capacity and improving the amount of echo suppression is to sequentially shift the transmitted signal and output it in parallel. A plurality of taps are divided into a main tap section and at least one sub-tap section, and the main memory section uses the signal from the main tap section as an address signal to read and write echo replicas, and the main memory section uses the signal from the sub-tap section as an address signal. The main memory includes at least one sub-memory section for writing and reading echo replicas as signals, and adding means for adding the received signal and the echo replicas output from each tap section to cancel echo components. Echo replicas having higher precision than echo replicas written in the sub-memory section are stored in each of the sub-memory sections, and the echo component is canceled out by these echo replicas.

[Industrial Field of Application] The present invention relates to a digital adaptive filter for canceling an echo component of a part of a transmitted signal that has entered a receiving side.

When bidirectional data transmission is performed via a hybrid circuit, a portion of the transmitted signal goes around to the receiving side via the hybrid circuit, resulting in reception errors. Therefore, it is necessary to cancel the echo component that is a part of the transmitted signal that has gone around to the receiving side.

[Conventional technology]

FIG. 4 shows the configuration of the main parts of the data transmitting/receiving section.

The data transmitting/receiving section shown in the figure includes a digital filter 411 that generates an echo nibbler, a driver 42.1 that transmits data, and a hybrid circuit 431 that connects a two-wire transmission line and a four-wire transmission line. , adder 44
1.

Transmission data S (present) from a transmitter (not shown) is sent from a driver 421 to a transmission path such as a subscriber line via a hybrid circuit 431. Further, received data R (b) received via this transmission path is supplied to a receiving section (not shown) via this hybrid circuit 431.

In this case, a part of the transmission data S(g) goes around to the receiving side via the hybrid circuit 431 and an echo component e(k
) and is superimposed on the received data R(2).

That is, data D(k) output from the hybrid circuit 431 to the receiving side is D(k)=R(k)+e(k), and when this data D(k) is supplied to the receiving section, the receiving side make a mistake

Therefore, the digital filter 411 filters the transmitted data 5.
Using (2), an echo replica @(k) (=-e(b)) similar to the echo component e(g) is formed and the adder 441
To force ■ eh, to D) + @ (g) = R (2) 10 e [exist]) +
The echo component e(k) is canceled by the process in step 6 (g) so that only the received data R (goods) is supplied to the receiving section.

The digital filter 411 described above has, for example, the configuration shown in FIG. memory section 521
This becomes the address signal. The number of taps of this tap section 511 is selected in accordance with the characteristics of the echo replica component e (goods). Further, the memory section 521 includes a random access memory (RAM), a control section, and the like.

The memory section 521 stores the received data D(k) via the hybrid circuit 431 and the memory section 521 at the time of retraction.
The echo replica itself is written so that the residual echo component (k) of the sum with the echo replica group (b) read from is zero. By writing the echo replica @temporary to all addresses in the memory section 52■,
The retraction process ends. Next, when transmitting and receiving data, the echo replica number (k) corresponding to the pattern of the transmitted data 5(k) is read out and added to the adder 531, and the adder 531 receives the data from the hybrid circuit 431. The received data R(k), in which the echo component included in the data D(k) is canceled and the residual echo component component Qc) becomes zero, is transferred to the receiving section.

The number n of taps of the tap section 511 is selected in accordance with the length of the received data that is affected by the echo component e(2) that goes around from the hybrid circuit 431 to the receiving side. Therefore, the capacity of the memory section 521 increases in proportion to 2''. Also, the time required for processing increases accordingly.゜01.00, +3.'+1..-1.
In a transmission system using a four-value symbol (corresponding to the four-value level -3), the capacity of the memory section 521 increases in proportion to 4''.

Therefore, as shown in FIG. 6, a memory-divided digital adaptive filter has been proposed. That is, a tap section with n taps to which the transmission signal 5(k) is added is divided into a main tap section 611 with taps and a sub-tap section 613 with n- taps. The main memory section 62 adds the address signal from the main tap section 611.
1 and a submemory section 623 to which the address signal from the subtap section 613 is added. Further, the echo replica ECR1 from the main memory section 621 and the received data D(2) are added to the adder 631, and the residual echo component ε1 of the output from the adder 631 and the sub-memory section 623 are added to the adder 631.
The echo replica ECR2 from the adder 633 is added to the adder 633, and its output is used as received data R(9).

Therefore, a part of the echo component corresponding to the number of taps k of the main tap section 611 is canceled by the echo replica ECR1 from the main memory section 621, and a part of the echo component corresponding to the number of taps n-k of the sub-tap section 613 is canceled by the echo replica ECR1 from the main memory section 621. , echo replica E from sub-memory section 623
This will be canceled by CR2. In that case, the residual echo component ε1. The echo replica ECR1°ECR2 is written into the main memory section 621 and the sub-memory section 623 by performing a pull-in process using an algorithm that minimizes ε2.

As mentioned above, the number of taps of the main tap section 611 is k,
When the number of taps in the sub-tap section 613 is n-, the capacity of the main memory section 621 is proportional to 2k, and the capacity of the sub-memory section 623 is proportional to 2+s-k, so the total memory capacity is 2''+2n- Therefore, it is possible to significantly reduce the capacity compared to the capacity which is proportional to 2'' of the memory section 521 for the number n of memory pumps in FIG. 5.

[Problem to be solved by the invention]

By the way, in the above-mentioned memory division type digital adaptive filter, although it is possible to reduce the memory capacity, there is a problem that division loss occurs. That is, it does not cancel the echo component corresponding to the total number of taps n, but acts to divide and cancel the echo component corresponding to the divided number of taps n−k. Therefore, at the time of retraction, the number of taps in the main memory section 621 and the sub memory section 623 is n −
It is necessary to write the echo replicas ECRI and ECR2 corresponding to k with high accuracy. If there is an error in echo replica ECR1, the residual echo component ε1 will increase, and if there is also an error in echo replica ECR2, the residual echo component ε1 will increase. The component ε2 also increases synergistically.

The present invention was created in view of these points, and an object of the present invention is to provide a digital adaptive filter that reduces memory capacity and improves the amount of echo suppression.

[Means to solve the problem]

The digital adaptive filter of the present invention is capable of canceling out echo components caused by a portion of the transmitted signal going around to the receiving side, and will be explained with reference to FIG.

A plurality of taps that sequentially shift transmission signals and output them in parallel are divided into a main tap section 111 and at least one sub-tap section 121.

The main memory section 131 writes and reads echo replicas using the signal from the main tap section 111 as an address signal.

At least one submemory section 141 corresponds to each of the subtap sections 121, and writes and reads echo replicas using a signal from the subtap section 121 as an address signal.

Adding means 151 adds the received signal to main tap section 111.
and the echo replica output from each sub-tap section 121 to cancel the echo component.

Overall, the configuration is such that echo replicas with higher accuracy than the echo replicas written in the main memory section 131 are stored in each of the sub-memory sections 141, and the echo components are canceled by these echo replicas.

[For production]

The transmission signal is sent to the main tap section 111 and each sub tap section 1.
21, and address signals are supplied from the main tap section 111 to the main memory section 131 and from each sub-tap section 121 to each sub-memory section 141. Echo replicas corresponding to the supplied address signals (transmission signals) are written in the main memory section 131 and each sub-memory section 141, and in the sub-memory section 141,
An echo replica with higher accuracy than the echo replica written into the main memory section 131 is written.

The main memory section 131 and each sub-memory section 141 output echo replicas according to the supplied address signal, and the adding means 151 uses these echo replicas to cancel the echo component contained in the received signal.

In the present invention, an echo replica with higher accuracy than the echo replica written in the main memory section 131 is written in each sub-memory section 141, and the residual echo included in the received signal output from the adding means 151 is By reducing the influence of echo replicas read from the sub-memory section 241, the memory capacity can be reduced by dividing the taps and the division loss due to the division can be reduced. It becomes possible to improve the amount of echo suppression.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an embodiment of the present invention.

(1) Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The main tap section 111 corresponds to the main tap section 211.

The sub-tap section 121 corresponds to the sub-tap section 221.

The main memory section 131 corresponds to the main memory section 231.

The sub-memory section 141 corresponds to the sub-memory section 241.

The addition means 151 includes an adder 261. It corresponds to the adder 263.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

In FIG. 2, an echo canceller 210 that functions as a digital adaptive filter that cancels echo components includes a main tap section 211 and a sub-tap section 22 that shift transmission data and output it from a predetermined number of taps.
1, a delay circuit 251 that delays this shift operation, and a main memory section 231 that stores echo replicas. It includes a sub-memory section 241 and two adders 261 and 263.

The transmission data 5(k) is sent to the transmission line 273 via the hybrid circuit 271, and is also sent to the main tap section 2.
11, and is further applied to the sub-tap section 221 via the delay circuit 251 for one bit and shifted. Further, the echo component X that has passed through the λ hybrid circuit 271 is added to an adder 261 and an adder 263 via this adder 261.

The echo replica ECR is sent from the main memory section 231 according to the address signal output from the main tap section 211.
1 is read and added to adder 261. Echo replica ECR2 is read out from submemory section 241 in accordance with the address signal output from subtap section 221 and added to adder 263.

The adder 261 adds an echo replica EC to the echo component
R1 is added, and the adder 263 further adds an echo replica ECR2 to the addition result. Therefore, the echo canceller 210 outputs received data R(2) in which the echo component X has been canceled.

Next, we will discuss the division loss caused by dividing the memory into the main memory section 231 and the sub-memory section 241.

Now, the number of taps of the main tap section 211 is nl, and the echo replica ECR1 output from the main memory section 231 is
The minimum number of steps is at (l/2I' if the number of bits of the echo replica is m), the true amount of echoes to be canceled in the main memory section 231 is ECI, and the echo replica E is
It is assumed that the residual echo after canceling the echo component by CR1 is 81.

Further, the number of taps of the sub-tap section 221 is n2, the minimum number of steps of the echo replica ECR2 output from the sub-memory section 241 is at, the true amount of echo to be canceled by the sub-memory section 241 is EC2, and the echo component cancellation by the echo replica ECR2 is set. Let ε be the residual echo caused by

Assuming that the echo replica of the main memory section 231 can be estimated correctly, IEcI+ECRII = ε, <al...(t)
becomes. Therefore, the residual echo of maximum al will go around to the sub-memory section 241 side, so the residual echo ε on the sub-memory section 241 side will be (at +EC2)+EC
R2<t <(a1+EC2)+ECR2...(2), and by transforming equation (2), -al + (EC2+ECR2)<ε<a, + (E
C2+ECR2)...13) is obtained.

Here, assuming that the echo replica of the sub-memory section 241 can be estimated correctly, 1Ec2 +ECR2l <az + HHHH・(4
). Substituting equation (4) into equation (3), εl <a
, +az ・・・・・・・・・(5) is obtained.

Even if the echo replicas to be written to the main memory section 231 and the sub-memory section 241 are correctly estimated by equation (5), the final residual echo ε will be the sum of the respective minimum step numbers 31 + a z. It can be seen that the errors are cumulative.

In the conventional case, the minimum number of steps a regarding the main memory section 231 and the minimum number of steps a2 regarding the sub memory section 241 are i1. ! a, and IεI < 2
It becomes a +.

Therefore, by dividing the memory, the amount of echo suppression deteriorates by at least 6 dB. By the way, by setting this minimum number of steps to al>>at, 1εI<
2a+ζa, and the increase in cumulative error (division loss) due to memory division can be suppressed to a negligible level.

For example, the minimum number of echo replica steps a I to be stored in the main memory unit 231! =2-'s Minimum number of steps a of echo replicas stored in the sub-memory unit 241,
The result of actually operating the echo canceller 210 shown in FIG. (set the number to 6 bits), and set the minimum number of steps for echo replicas in the main memory section 231 and sub memory section 241 to 2-s.
The amount of echo suppression could be improved by about 6 dB compared to the case where

1-1 Next, an example of an algorithm for writing echo replicas into the main memory section 231 and sub-memory section 241 described above will be explained. The bit length of the echo replica stored in the main memory section 231 is n, and the sub memory section 24
The bit length of the echo replica stored in 1 is m (m≧n+
1).

FIG. 3 shows a detailed configuration of the echo canceller 310 for realizing the pull-in operation.

In the figure, the echo canceller 310 includes a main tap section 211. Sub tap section 221. Main memory section 231
．． Sub-memory section 241, delay circuit 251, convergence determination and specific pattern detection section 281, and convergence determination section 283
and four adders 291, 293, 295, and 297.

The transmission data 5(k) is sent to the transmission line 273 via the hybrid circuit 271, and is also sent to the main tap section 2.
11 and the main tap section 211 is applied to the sub-tap section 221 via the delay circuit 251 and shifted. Further, the echo component X that has passed through the hybrid circuit 271 is added to the adder 297 and
Echo replicas ECRI and ECR2 are read from the main memory section 231 and the sub-memory section 241 according to address signals from the sub-tap section 221 and the sub-tap section 221, and are added by the adder 295 and added to the adder 297. Therefore, received data R(k) with echo component X canceled
is output.

The convergence determination and specific pattern detection unit 281 detects whether the address signal applied from the main tap unit 211 to the main memory unit 231 is a specific pattern, and sends the detection signal to the main memory unit 231 and the sub memory unit 241. Based on the address signal, when echoes corresponding to the number of taps in the main tap section 211 are written to all addresses in the main memory section 231, convergence is determined, and the determination signal is sent to the main memory section 231. and the sub-memory section 241.

Furthermore, the convergence determination section 283 applies all addresses of the sub-tap section 221 to all addresses of the sub-memory section 241 based on the address signal applied from the sub-tap section 221 to the sub-memory section 241.
It is determined that convergence has occurred when echoes corresponding to the number of taps are written, and the determination signal is added to the main memory section 231 and the sub-memory section 24I.

The pull-in of the echo canceller 310 uses, for example, a random pattern as the transmission data 5(2),
The signal patterns output from the taps of the main tap section 211 and the sub-tap section 221 are random numbers. and,
The convergence determination and specific Bakun detection unit 281 averages the echo components obtained when the output of the specific pattern from the main tap unit 211 is detected over a predetermined number of times, such as several times or thousands of times. That is, the echo component X due to the feedback of the hybrid circuit 271 in the case of a specific pattern is added to the main memory section 231 via the adders 297 and 291, and is subjected to an averaging operation in the main memory section 231, or is sent to another arithmetic section. Performs the averaging operation. This averaged value is used as an echo replica,
Main memory section 23 using a specific pattern as an address signal
Write in area 1.

When this writing is completed, next, the echo replica written in the main memory unit 231 is subtracted from the echo component when the specific pattern is detected by the convergence determination unit 281 and the specific pattern detection unit 281 again. Based on the address signal from the sub-tap section 221, it is written into the sub-memory section 241. In this case, the main memory section 231
The address signal for the sub-memory section 241 is a specific pattern, but the address signal for the sub-memory section 241 is a random pattern.
Echo replicas for all 41 addresses can be written. When writing to all addresses is completed in this way, the convergence determination unit 283 determines whether the sub-memory unit 241
The convergence of is determined, and a determination signal is applied to the main memory section 231 and the sub memory section 241.

By convergence of the sub-memory section 241, the main memory section 231 extracts the echo component from the echo component when the address signal from the main tap section 211 has a pattern other than the specific pattern.
The echo replica obtained by subtracting the echo replica written to 1 is written in the area of the main memory section 231 according to the address signal. Then, when the convergence determination and specific pattern detection unit 281 determines that echo replicas have been written to all addresses in the main memory unit 231, pull-in convergence occurs.

In this way, after averaging and obtaining the echo replicas for the specific pattern of the main tap section 211 and writing them into the main memory section 231, the echo replicas for the pattern of the sub-tap section 221 are obtained. The echo replica obtained at this time is obtained with higher precision than the echo replica written in the main memory section 231 (the bit length is increased by one or more digits), and is written in the sub-memory section 241. For patterns other than the specific pattern in the main tap section 211, echo components
The echo replica ECR2 is subtracted from the echo replica ECR2 to obtain an echo replica.

■ As shown in 1, the main memory section 231 and sub memory section 2
41, an echo replica is written according to a predetermined algorithm. At this time, by making the accuracy of the echo replica written to the sub-memory section 241 higher than that of the echo replica written to the main memory section 231 (by increasing the bit length of the data), the main memory section 231 and the sub-memory section 241 can be separated. It is possible to suppress the division loss caused by division, and it is possible to reduce the memory capacity and improve the echo suppression amount (compared to the case of division) by division.

Incidentally, in the embodiment of the present invention described above, the main memory section 231 and one sub-memory section 241 were considered to be divided, but the main memory section 231 and a plurality of sub-memory sections 241 The present invention can also be applied to the case of dividing into a memory section. In this case, the precision of the echo replicas written to the plurality of sub-memory sections is set higher than the precision of the echo replicas written to the main memory section 231.

In addition, in "1. Correspondence between Examples and FIG. 1",
Although the correspondence between the present invention and the embodiments has been described, those skilled in the art will easily assume that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As described above, according to the present invention, in each sub-memory section,
By writing an echo replica with higher precision than the echo replica written in the main memory section and reducing the influence of the echo replica read from the sub-memory section on the residual echo included in the received signal output from the adding means, Reducing memory capacity by dividing taps,
Since it is possible to improve the amount of echo suppression by reducing the division loss caused by the division, it is extremely useful in practice.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the digital adaptive filter of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a block diagram of an embodiment of the present invention, and Fig. 4 is a block diagram of a conventional example. FIG. 5 is a block diagram of a conventional digital adaptive filter; FIG. 6 is a block diagram of a conventional digital adaptive filter. In the figure, 111 is a main tap section, 121 is a sub-tap section, 131 is a main memory section, 141 is a sub-memory section, 151 is an addition means, 210 and 310 are echo cancellers, 211 is a main tap section, 221 is a sub-tap section, 231 241 is the main memory section, 241 is the sub-memory section, 251 is the delay circuit, 261.263, 291, 293.2957 is the adder, 271 is the hybrid circuit, 273 is the transmission path, 281 is the convergence judgment and specific pattern detection section, 283 is the convergence determination part. Figure 2: A picture of a fool's blow on the side of a laughing stock of inventions, Figure 1: A picture of the processed ball of the customer on the other day, Figure 1: The structure of the book, Figure 3: Children of FunIJ' Water outlet diagram

Claims (1)

[Claims] (1) In a digital adaptive filter for canceling echo components generated when a part of the transmitted signal goes around to the receiving side, a main tap section ( 111) and at least 1
and a main memory section (131) that writes and reads echo replicas using the signal from the main tap section (111) as an address signal, and corresponds to each of the sub-tap sections (121). and at least one read/write echo replica using the signal from the sub-tap section (121) as an address signal.
adding means (151) for canceling the echo component by adding the received signals of the two sub-memory sections (141) and the echo replicas output from the main tap section (111) and each sub-tap section (121); , and store echo replicas with higher accuracy in each of the sub-memory parts (141) than the echo replicas written in the main memory part (131), and cancel out the echo components by these echo replicas. A digital adaptive filter characterized by comprising: