JPH0230246U - - Google Patents

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Publication number
JPH0230246U
JPH0230246U JP10847688U JP10847688U JPH0230246U JP H0230246 U JPH0230246 U JP H0230246U JP 10847688 U JP10847688 U JP 10847688U JP 10847688 U JP10847688 U JP 10847688U JP H0230246 U JPH0230246 U JP H0230246U
Authority
JP
Japan
Prior art keywords
voltage
circuit
inverter
grid
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10847688U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10847688U priority Critical patent/JPH0230246U/ja
Publication of JPH0230246U publication Critical patent/JPH0230246U/ja
Pending legal-status Critical Current

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  • Stand-By Power Supply Arrangements (AREA)
  • Supply And Distribution Of Alternating Current (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例の瞬時電圧低下補
償装置の構成を示すブロツク図、第2図は不感帯
特性を示す特性図、第3図は第1図の各部のタイ
ムチヤート、第4図は従来例の構成を示すブロツ
ク図、第5図は第4図の各部のタイムチヤートで
ある。 1……電力系統、2……負荷、3……インバー
タ回路、5……バイパススイツチ、11……系統
電圧検出回路、13……基準正弦波発生回路、1
4……瞬時電圧低下検出回路、15……第1の演
算回路、18……補償作動制御回路、20……イ
ンバータ制御回路、21……インバータ電流検出
回路、22……増幅回路、23……第2の演算回
路。
Figure 1 is a block diagram showing the configuration of an instantaneous voltage drop compensator according to an embodiment of this invention, Figure 2 is a characteristic diagram showing dead zone characteristics, Figure 3 is a time chart of each part of Figure 1, and Figure 4. 5 is a block diagram showing the configuration of a conventional example, and FIG. 5 is a time chart of each part of FIG. 4. DESCRIPTION OF SYMBOLS 1...Power system, 2...Load, 3...Inverter circuit, 5...Bypass switch, 11...System voltage detection circuit, 13...Reference sine wave generation circuit, 1
4... Instantaneous voltage drop detection circuit, 15... First arithmetic circuit, 18... Compensation operation control circuit, 20... Inverter control circuit, 21... Inverter current detection circuit, 22... Amplification circuit, 23... Second arithmetic circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電力系統と負荷との間に直列介挿した瞬時電圧
低下補償用のインバータ回路と、このインバータ
回路の出力端をバイパスするバイパススイツチと
、前記電力系統の系統電圧と同相でかつ正常時電
圧に相当する振幅を有する基準正弦波電圧を発生
する基準正弦波発生回路と、前記電力系統の系統
電圧を検出して系統電圧対応電圧を出力する系統
電圧検出回路と、前記電力系統の正常時電圧の所
定パーセントを超える瞬時電圧低下の発生を検出
する瞬時電圧低下検出回路と、前記インバータ回
路の出力電流を検出してインバータ出力電流対応
電圧を発生するインバータ電流検出回路と、不感
帯特性を有して前記インバータ出力電流対応電圧
を増幅する増幅回路と、前記基準正弦波電圧から
前記系統電圧対応電圧を減算して差電圧を求める
第1の演算回路と、前記第1の演算回路から出力
される差電圧から前記増幅回路の出力電圧を減算
して補償信号電圧を出力する第2の演算回路と、
前記第2の演算回路から出力される補償信号電圧
に応じて前記インバータ回路をスイツチング制御
することにより前記インバータ回路から補償電圧
を出力させるインバータ制御回路と、前記瞬時電
圧低下検出回路の瞬時電圧低下発生検出出力に応
答して前記バイパススイツチを開放するとともに
前記インバータ制御回路を能動化させる補償作動
制御回路とを備えた瞬時電圧低下補償装置。
An inverter circuit for instantaneous voltage drop compensation inserted in series between the power system and the load, a bypass switch that bypasses the output end of this inverter circuit, and an inverter circuit that is in phase with the grid voltage of the power system and corresponds to a normal voltage. a reference sine wave generation circuit that generates a reference sine wave voltage having an amplitude of , a grid voltage detection circuit that detects the grid voltage of the power grid and outputs a voltage corresponding to the grid voltage, and a predetermined normal voltage of the power grid. an instantaneous voltage drop detection circuit that detects the occurrence of an instantaneous voltage drop that exceeds 50%; an inverter current detection circuit that detects the output current of the inverter circuit and generates a voltage corresponding to the inverter output current; an amplifier circuit that amplifies the voltage corresponding to the output current; a first arithmetic circuit that obtains a differential voltage by subtracting the voltage corresponding to the grid voltage from the reference sine wave voltage; and a differential voltage output from the first arithmetic circuit. a second arithmetic circuit that subtracts the output voltage of the amplifier circuit and outputs a compensation signal voltage;
an inverter control circuit that outputs a compensation voltage from the inverter circuit by switching-controlling the inverter circuit according to a compensation signal voltage output from the second arithmetic circuit; and an instantaneous voltage drop occurrence in the instantaneous voltage drop detection circuit. An instantaneous voltage drop compensator comprising a compensation operation control circuit that opens the bypass switch and activates the inverter control circuit in response to a detection output.
JP10847688U 1988-08-18 1988-08-18 Pending JPH0230246U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10847688U JPH0230246U (en) 1988-08-18 1988-08-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10847688U JPH0230246U (en) 1988-08-18 1988-08-18

Publications (1)

Publication Number Publication Date
JPH0230246U true JPH0230246U (en) 1990-02-26

Family

ID=31343843

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10847688U Pending JPH0230246U (en) 1988-08-18 1988-08-18

Country Status (1)

Country Link
JP (1) JPH0230246U (en)

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