JPH023044A - Exposure method - Google Patents

Exposure method

Info

Publication number
JPH023044A
JPH023044A JP63150554A JP15055488A JPH023044A JP H023044 A JPH023044 A JP H023044A JP 63150554 A JP63150554 A JP 63150554A JP 15055488 A JP15055488 A JP 15055488A JP H023044 A JPH023044 A JP H023044A
Authority
JP
Japan
Prior art keywords
photomask
substrate
possessing
height
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63150554A
Other languages
Japanese (ja)
Inventor
Koji Tominaga
浩司 冨永
Koji Yoneda
幸司 米田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP63150554A priority Critical patent/JPH023044A/en
Publication of JPH023044A publication Critical patent/JPH023044A/en
Pending legal-status Critical Current

Links

Landscapes

  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE:To perform highly accurate exposure by a contact system by employing a photomask possessing a step of height similar to a semiconductor substrate when a photolithographic stage where the semiconductor substrate possessing a step is exposed. CONSTITUTION:When the photolithographic stage where the semiconductor substrate 10 possessing the step is exposed, the photomask 20 possessing the step similar to the substrate is employed. The height h1 of a higher plane 13 made by a mesa part 12 is 2mum from the lower plane 11 of the substrate 10, and the width W1 of the mesa part is 30mum. The height h2 of the lower plane 2 made by the mesa part 21 of the photomask 20 is set almost the same as the height of the mesa part 12 on the side of the substrate 10, and mask metals 25 and 26 are applied to the lower and higher planes 23 and 26 of the photomask 20, respectively. Consequently, the semiconductor substrate 10 possessing a step can be exposed accurately by a contact system.

Description

【発明の詳細な説明】 (イ) 産業上の利用分野 本発明は半導体装首製造の際のホ) IJソゲラフイエ
程における露光方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an exposure method in (e) IJ sogerafue process during the manufacture of semiconductor devices.

(ロ)従来の技術 この種の露光方iにおいて、従来よりコンタクト方式が
知られているC例えば、株式会社工業調査会発行「最新
I、eエプロセス技術JP261.1984)。
(B) Conventional technology In this type of exposure method, the contact method has been known for a long time.

コンタクト方式は、ウェー1%。全面に一度にパターン
露光を行うものであるからスループットの高い利点を持
つが、被露光面に段差がある場合、ホトwスクと被露光
面との密着が得られないため高い露光解像度を実現でき
ない。
The contact method is 1% way. It has the advantage of high throughput because pattern exposure is performed on the entire surface at once, but if there are steps on the exposed surface, high exposure resolution cannot be achieved because the photoscreen and the exposed surface cannot be in close contact. .

i/ウ  発明が解決しようとする課題本発明は、段差
を有する半導体基板にも、コンタクト方式で精度良く露
光を行い得る方法を提供しようとするものである。
I/C Problems to be Solved by the Invention The present invention aims to provide a method that can accurately expose a semiconductor substrate having a step using a contact method.

に)課題を解決するための手段 本発明の露光方法は、段差を有する半導体基板にホトリ
ソグラフィ工程の露光を実施する際に、上記段差とほゞ
同じ高さの段差を有するホトマスクを用いることを特徴
とする。
B) Means for Solving the Problems The exposure method of the present invention includes the use of a photomask having a step approximately the same height as the step when exposing a semiconductor substrate having a step in a photolithography process. Features.

(ホ)作用 本発明によれば、被露光面の段差とホトマスクの段差と
が互いにかみ合い、ホトマスクが被露光面とほゞ密着す
る。
(E) Function According to the present invention, the steps on the exposed surface and the steps on the photomask mesh with each other, and the photomask comes into close contact with the exposed surface.

(へ)実施例 本発明実施例の露光方87に説明するに、この場片、第
3図に示す如く、低位面111と、メサ部α2の作る高
位面αJとを備える半導体基tfz !IGに対し、そ
の低位、高位各面1110311c夫々V字pI(+4
1(至)を同時形成するに当って、本発明露光方法を適
用するものである。
(F) Embodiment To explain the exposure method 87 of the embodiment of the present invention, this field piece, as shown in FIG. 3, is a semiconductor substrate tfz! having a low-level surface 111 and a high-level surface αJ formed by the mesa portion α2. V-shaped pI (+4
1 (to), the exposure method of the present invention is applied.

この様な、V字溝は、2種類の半導体レーザダイオード
を同−基ff1Ilαに同時形収するために利用される
。即ち、第6図に示す基板1101表面に、第1クラッ
ド層、活性層、第2クラッド層等、周知のレーデ構改層
を順次液相エピタキシャル改良させること忙より、活性
層の厚みは、高位[10aJ上おいて小さく、低位面(
!l)上において大きくなる。前者の活性層は高出力レ
ーザ発i1に、又後者のそれは低雑音レーザ発振を犬々
可能ならしめる。
Such a V-groove is used to simultaneously accommodate two types of semiconductor laser diodes in the same base ff1Ilα. That is, since the surface of the substrate 1101 shown in FIG. 6 is successively liquid-phase epitaxially improved with well-known Rade structural layers such as a first cladding layer, an active layer, and a second cladding layer, the thickness of the active layer is at a high level [ It is small above 10aJ, and the lower surface (
! l) Becomes larger at the top. The former active layer enables high-output laser oscillation i1, and the latter enables low-noise laser oscillation.

第1図に示す工程では、メサ部[12+を有するGaA
3基tfitlαが準備され、その基板表面にホトレジ
スト膜0υが被着さnる。メサ部の作る高位面rJ31
の高さhlは、基板の低位面(11)に対し2μmであ
り、又メサ部の幅Wtは60μmである。
In the process shown in FIG.
Three tfitlα are prepared, and a photoresist film 0υ is deposited on the surface of the substrate. High surface rJ31 created by mesa part
The height hl is 2 μm with respect to the lower surface (11) of the substrate, and the width Wt of the mesa portion is 60 μm.

第1図に示す工程では、更に、ホトマスク翰が準備され
る。このマスクは、下向きメサ部圓ヲ有するガラス製マ
スク基板固を含む。メサ部@珀の作る低位下面(至)の
高さhlは、前記基板11α側のメサ部α2の高さKは
y等しく設定され、今の場合、マスク基板□□□の高位
下面(241に対し2μmである。ホトマスク(イ)は
、更にcrからなるマスクメタル(至)翰を含み、それ
らメタルは、基ffz +lαの低位面+111及び高
位面a3に対応して、夫々ホトマスク翰の低位下面−及
び高位下面嶽に被着されている。マスクメタル(2I5
)翰の幅W1は2μm程度を適当とする。
In the step shown in FIG. 1, a photomask is further prepared. The mask includes a glass mask substrate having a downward facing mesa. The height hl of the lower lower surface (toward) formed by the mesa part @ is set equal to the height K of the mesa part α2 on the substrate 11α side, and in this case, the height hl of the lower lower surface (toward) of the mask substrate □□□ is set equal to y. The photomask (A) further includes a mask metal (to) ridge made of cr, and these metals correspond to the lower surface +111 and the higher surface a3 of the base ffz +lα, respectively, and the lower surface of the photomask ridge is 2 μm. - Mask metal (2I5
) The appropriate width W1 of the wire is about 2 μm.

第21aK示す工程では、第1図における基板1101
の表面にホトマスク−の下面を接触させて露光が行なわ
れ、次いでホトレジスト膜αυの現像処理により未露光
部分のみが除去され窓鰭(ハ)が投けられの る。本工程における基板とホ)wスフと接触は、八 基板側にメサ部O2による段差があるにもか\わらず、
ホトマスク側にも、同等高さの下向きメサ部防)による
段差がある念め、良好にf!M着的である。
In step 21aK, the substrate 1101 in FIG.
Exposure is carried out by bringing the lower surface of a photomask into contact with the surface of the window, and then only the unexposed portions are removed by developing the photoresist film αυ, leaving the window fin (c). In this process, the contact between the substrate and the (H) and (W) steps was made despite the fact that there is a step on the substrate side due to the mesa part O2.
There is also a step on the photomask side due to the downward facing mesa part (of the same height), so the f! M-suitable.

尚、ホトレジスト膜061に形収された窓ガ瞥の幅は1
.2μm程度である。
Note that the width of the window pattern formed in the photoresist film 061 is 1
.. It is about 2 μm.

第6図に示す工程では、前記ホトレジスト膜α−の窓(
27IQ811に:通じてエツチングが行われ、この結
果、低位、高位各面flllf13に夫々7字溝(14
1CLf9が同時形成される。エッチャントにはリン酸
系のものが用いられ、得られる各V字溝の開口幅及び深
さは、夫々22μ販び1.5μm程度である。
In the step shown in FIG. 6, the window (
27IQ811: As a result, a 7-figure groove (14
1CLf9 is formed simultaneously. A phosphoric acid-based etchant is used, and the opening width and depth of each V-shaped groove obtained are approximately 22 μm and 1.5 μm, respectively.

以上の実tla例で仁、GaA4板が使用された力(池
の材料からなる基板にも、本発明は適用され得にも、コ
ンタクト方式で精度良く露光を行うことができる。
The present invention can also be applied to a substrate made of the same material as the GaA4 plate used in the above actual example, and exposure can be performed with high precision using the contact method.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第6図は本発明の実施例方法を示す工程別断
面図である。 11α−半導体基板、α2−メサ部、−一ホトレジスト
膜、−一ホトマスク、?B−下向きメサ部、(ハ)(イ
)−リスクメタル。
FIGS. 1 to 6 are cross-sectional views showing steps of an embodiment of the present invention. 11α-semiconductor substrate, α2-mesa part, -1 photoresist film, -1 photomask, ? B-Downward mesa part, (C) (B)-Risk metal.

Claims (1)

【特許請求の範囲】[Claims] (1)段差を有する半導体基板にホトリソグラフイ工程
の露光を実施する際に、上記段差とほゞ同じ高さの段差
を有するホトマスクを用いることを特徴とする露光方法
(1) An exposure method characterized by using a photomask having a step approximately the same height as the step when exposing a semiconductor substrate having a step in a photolithography process.
JP63150554A 1988-06-17 1988-06-17 Exposure method Pending JPH023044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63150554A JPH023044A (en) 1988-06-17 1988-06-17 Exposure method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63150554A JPH023044A (en) 1988-06-17 1988-06-17 Exposure method

Publications (1)

Publication Number Publication Date
JPH023044A true JPH023044A (en) 1990-01-08

Family

ID=15499417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63150554A Pending JPH023044A (en) 1988-06-17 1988-06-17 Exposure method

Country Status (1)

Country Link
JP (1) JPH023044A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04278951A (en) * 1991-03-07 1992-10-05 Fujitsu Ltd Mask for producing semiconductor device and production of semiconductor device
US5205569A (en) * 1986-11-10 1993-04-27 Ishikawa Gasket Co., Ltd. Metal laminate gasket with graphite sheet

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5205569A (en) * 1986-11-10 1993-04-27 Ishikawa Gasket Co., Ltd. Metal laminate gasket with graphite sheet
JPH04278951A (en) * 1991-03-07 1992-10-05 Fujitsu Ltd Mask for producing semiconductor device and production of semiconductor device

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