JPH02304653A - Memory access mode switching system - Google Patents

Abstract

PURPOSE:To switch a data transfer mode from a cache memory to a CPU in accordance with the generation frequency of a memory error by providing a mode for executing a data transfer after checking an error in the case the memory error is generated frequently. CONSTITUTION:At the time of data transfer to a CPU 7 from a cache memory 1, in a first data transfer mode, the data is transferred to the CPU 7 before a result of error check by an error analyzing means 4 in the memory 1 is known. In the case it is known that an error is generated, its error generation is informed the CPU 7 by an interruption. Also, in a second data transfer mode, it is awaited that a result of error check by the means 4 is known, and at the point of time when it is known that there is no error, the data is transferred to the CPU 7 from the cache memory 7. A first and a second data transfer modes are switched in accordance with the error detection frequency executed by the means 4, and in accordance with the degree of generation of a memory error, the data transfer mode can be switched, and the system which is operated at a high speed and strong against an error can be constituted.

Description

[Detailed Description of the Invention] [Summary] Regarding the memory access mode switching method that switches the mode of data transfer from the cache memory to the central processing unit according to the frequency of occurrence of memory errors, when memory errors occur frequently, the error The purpose of this method is to provide a mode in which data is transferred after checking, and to provide a method for switching the mode of data transfer from cache memory to the central processing unit depending on the frequency of memory error occurrence. In a cache memory composed of a tag memory that stores the address of as tag data and a static random access memory SRAM that stores the stored data, an error check is performed on the tag data of the tag memory and the data stored in the SRAM. It has an error analysis means and a timing control means for controlling the mode of data transfer from the SRAM to the central processing unit of the system, and the data is transferred to the central processing unit before the error check result by the error analysis means is known. a first data transfer mode in which when it is determined that an error has occurred, the central processing unit is notified of the error occurrence through an interrupt; The second data transfer mode for transferring data to the device is configured to be switchable.

[Field of Industrial Application] The present invention relates to a cache memory used as a means to speed up access time in order to increase the processing capacity of a central processing unit of a computer system, and more specifically, to improve the frequency of memory error occurrence. The present invention relates to a memory access mode switching method for switching the mode of data transfer from a cache memory to a central processing unit according to the data transfer mode.

Many of the recent single-chip CPUs have built-in cache memory. However, the capacity of such a built-in cache is small, and it is generally necessary to provide an external large-capacity cache memory.

Cache data is exchanged between the built-in cache and the external cache as a cache access. For example, in read access to the external cache, high-speed data transfer in block units is expected.

During such data transfer, if an error check is performed on the data stored in the external cache, the data transfer speed will be slowed down. Therefore, in order to shorten the access time as much as possible and realize high-speed block data transfer, it is necessary to establish a transfer method that is compatible with the degree of failure in the external large-capacity cache system.

[Conventional technology]

A cache memory is located between a central processing unit and a main memory of a computer system, and is used to improve the time taken to read information from the central processing unit to the main memory, and is also called a buffer memory.

Such a cache memory consists of a data storage section that stores the data itself, and a tag section (tag memory) that stores which address in the main memory stores the data. In a cache memory that generally uses static RAM (SRAM) as a data storage unit, data is transferred between the main memory and the cache memory when there is a cache miss, that is, the data accessed by the central processing unit does not exist in the cache memory. However, the basic unit for data exchange is called a block. The optimal size of the block is determined by the trade-off between cache miss processing and transfer time.

In a set-associative cache memory of, for example, 64 bytes, which is used to reduce system errors and use cache memory efficiently, the main memory and cache memory are divided into units of, for example, 64 bytes per block. It is divided into 64 sets. Therefore, the cache memory is divided into 16 blocks for one set. Data is sent and received between corresponding sets of main memory and cache memory.

In the cache memory, whether or not data is stored in the data storage section, that is, whether it is a hit or a miss, is determined based on the storage contents of the tag memory. If there is a hit, that set of data is output from the SRAM. That is, when reading data, it is determined whether or not there is a hit based on the address accessed by the central processing unit and the contents stored in the tag memory, and if it is a hit, the SRAM to be operated is determined and data output is performed.

In the case of a miss, data is transferred to the central processing unit via the cache memory by accessing the main memory, and at the same time the tag memory is updated and the SRA
The data of M is replaced.

When writing data, the SR that should operate in the case of a human
AM is determined and data is rewritten. In the case of a miss, data from the central processing unit is transferred to the main memory and the cache memory is not rewritten. Here, we explained the method using cache memory as a relay, but
There is also a method in which the cache memory and main memory control unit operate in parallel.

FIG. 5 shows a time chart of a conventional method of data transfer from a static random access memory (SRAM) in a cache memory to a central processing unit. In the figure, the contents of the tag memory are checked based on the address of data A at the access start position given by the central processing unit, and free hit data indicating that data at that address is stored in the cache memory is output. After the data complete signal DC is sent to the central processing unit, data A is output from the SRAM. After that, data B, C, D of the next address in the SRAM.
... are output one after another from the cache memory and transferred to the central processing unit. In this case, the time required to output one data matches the cycle time of the SRAM.

[Problem to be solved by the invention]

In the conventional data transfer method as shown in Figure 5, the time required to output data from the SRAM is inferior to the SRAM cycle time, and if there is no difference between this cycle time and the bus cycle time, , there is a problem that there is no time to check the output data of the SRAM for errors. SR to check SRAM data
If one AM cycle time is required, there is a problem in that the access time will double if the data is transferred to the central processing unit after being checked for errors.

The present invention provides a method for providing a mode in which data transfer is performed after error checking when memory errors occur frequently, and switching the mode of data transfer from the cache memory to the central processing unit depending on the frequency of memory error occurrence. The purpose is to

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention. In the figure, cache memory 1 includes tag memory 2, static random access memory (SRAM) 3, and error analysis means 4.
, and timing control means 5. The tag memory 2 stores the address on the main memory 6 of the data stored in the cache memory 1 as tag data,
SRAM3 stores stored data.

The error analysis means 4 analyzes the tag data in the tag memory 2 and the SR.
Performs error checking of the data stored in AM-3, for example, parity check. The timing control means 5 controls the mode of data transfer from the cache memory 1 to the central processing unit 7 of each system.

Here, the data transfer mode is, for example, the error analysis means 4.
It shall be switched depending on the frequency of error detection.

[For production]

In FIG. 1, from the cache memory l to the central processing unit 7
The effect when transferring data to is explained. In the first data transfer mode, in order to make the access time as fast as possible, the cache is Data is transferred from memory l to central processing unit 7. If it is determined that an error has occurred as a result of the error check by the error analysis means 4, the occurrence of the error is notified to the central processing unit 7 by, for example, an interrupt. During interrupt processing, the central processing unit 7 can learn the address at which the error has occurred, for example, by reading the contents of a register (not shown) provided in the cache memory I.

In the second data transfer mode, the error check result of the error analysis means 4 is waited for, and when it is determined that there is no error, data is transferred from the cache memory l to the central processing unit 7. This mode can be used, for example, with tag memory 2.
In one case, the data is transferred to the central processing unit 7 when it is determined that there is no error in the tag data in the tag memory 2, and in the other, the data is transferred to the central processing unit 7 when it is determined that there is no error in the tag data in the tag memory 2 and the data stored in SRAMa. The central processing unit 7
It can also be divided into cases where data is transferred to

Switching between the first data transfer mode and the second data transfer mode as described above is performed in accordance with the frequency of error detection by the error analysis means 4, as described above. In general, when memory errors occur, they tend to occur frequently, so in such cases, data is transferred using the second data transfer mode, and when errors occur less frequently, data is transferred using the second data transfer mode. A first mode can be used.

As described above, according to the present invention, data transfer modes can be switched depending on the degree of occurrence of memory errors.

〔Example〕

FIG. 2 shows a block diagram of the overall configuration of an embodiment of a cache memory system using the memory access mode switching method of the present invention. In the same figure, the system includes tag memory 2, S
It consists of a RAM 3, an external cache control section 8, and an MPU 9 corresponding to the central processing unit 7 of the system. The external cache control section 8 includes a tag access control section 10, an SRAM access control section 11, a bus access monitoring section 12, an error analysis control section 13, and a timing control section 14.

The tag access control unit 10 receives address data from the MPU 9 from "AO" to "A29" of the total 32 bits.

The receiver takes the 30 bits from “”AO”’ to “A2”.
The tag memory 2 outputs 0゛ as tag data and ``A21'' to ``A29'' as entry address data.The tag memory 2 outputs the data stored corresponding to the entry address when accessed from the MPU 9 and the data given at the time of access. When the comparison results in a match, a hit signal indicating that the corresponding data is stored in the SRAM 3 is output to the SRAM access control unit 11. This hit signal also causes the SRAM 3 to be stored. This becomes the chip select signal C8 for operation.

The SRAM access control unit 11 receives "A30" and "A31" from the address data sent from the MPU 9, sends these 2 bits to the SRAM 3 as an intra-block address at the time of the first SRAM access, and then sends them to the SRAM 3.
Create a data transfer address from AM3 and send it one after another. The bus access monitoring unit 12 activates the timing control unit 14 when a bus cycle starts under conditions of external cache access.

The error analysis control unit 13 checks the tag data in the tag memory 2 and the stored data in SRAMa, for example, for parity errors, holds the results, and notifies the MPU 9 of errors corresponding to the data transfer mode. ,
The timing control unit 14 is caused to perform timing control corresponding to the mode.

There are three types of data transfer modes, and the 11th mode, mode "O", interrupts the MPU 9 when an error is detected in the tag data or data stored in the SRAM, and the data transfer from the SRAM 3 ends when the error check is completed. done before.

That is, in mode "0°", when the hit signal is output from the tag memory 2 to the SRAM access control section 11, the timing control section 14 outputs the data complete signal D.
C is output to the MPU 9.

Mode “l” which is the first case of the second mode
After the hit signal is output from the tag memory 2, when the error analysis control section 13 determines that there is no error in the tag data, the timing control section 14 outputs the signal DC.
is output to the MPU 9, and data transfer is performed. If there is an error in the tag data, a tag bus error is output from the error analysis control section 13 and a data complete signal DC is output from the timing control section 14 to the MPU 9. Furthermore, if an error is detected in the data stored in SRAMa after data transfer, the error analysis control unit 13 notifies the MPU 9 of the error as an interrupt.

The second case in the second mode, i.e. mode “2”
Then, the error analysis control unit 13 analyzes the tag data and SRA.
When it is determined that there is no error in both the data stored in M and the data stored in M, a data complete signal DC is output from the timing control unit 14 to the MPU 9, and the data is transferred.

If there is an error in either the tag data or the data stored in the SRAM, the error analysis control section 13 outputs a bus error and the timing control section 14 outputs a data complete signal DC to the MPU 9.

FIG. 3 shows a basic configuration block diagram of an embodiment of the timing control section 14. The timing control section 14 includes a timing setting register 15 and a timing tree 16. The timing tree 16 includes the bus access monitoring unit 1 shown in FIG.
A timing start signal is input from 2.

In FIG. 3, the timing setting register 15 has three registers from '0' to 2' according to the three data transfer modes mentioned above.
A bit is set, and the timing of the bit that is 1° out of the 3 bits is selected. The contents of this timing setting register are managed by the error analysis control unit 13 according to the frequency of occurrence of memory errors, for example. Then, the timing output of the selected bit is SR in Figure 2.
It is output to the AM access control section 11. When a plurality of bits from 0° to 2° in the timing setting register are set to 1, for example, the upper bits are given priority.

FIG. 4 is a time chart of an embodiment of data block transfer according to the present invention. In the same figure, (a), (b)
), (C) are respectively mode “0” II I I
I.

A time chart of “2” is shown.

In FIG. 4(a) of the block transfer time chart in mode "0°", when the address of data A at the access start position is given together with the block transfer instruction signal, the MPU 9 A data complete signal DC is sent. At the same time, a signal indicating the data transfer mode is output, A, B, C,
Data is transferred one after another to the MPU 9 in order D(7). In this transfer, data B is transferred immediately after data A is transferred in the next SRAM cycle. Data C and D are subsequently transferred in the same manner. That is, in this mode, data is transferred before the end of the error check as described above, so if an error is detected by the error analysis control unit 13, the MPU 9 is notified of it by an interrupt.

FIG. 4(b) is a time chart of data transfer in mode "1". In the figure, when the address of data A at the access start position and the block transfer instruction signal are given, an error check of the tag data in the tag memory 2 is performed by the error analysis control unit 13, and it is determined that there is no tag error. At this point, the data complete signal DC is M
It is output to PLJ9, and data A is transferred at the same time. At this time, a data transfer mode signal is also output at the same time.

Thereafter, in preparation for transferring data B at the next address of data A, the error analysis control unit 13 performs an error check on the tag data for data B. When it is determined that there is no error, a data complete signal DC is output to the MPU 9 and data B is transferred at the same time. Thereafter, data C and D are transferred in exactly the same manner.

FIG. 4(C) is a transfer time chart for mode "2". In the figure, when an address to data at an access start position and a block transfer instruction signal are given, the error analysis control unit 13 checks both tag errors and errors in data stored in the SRAM. When it is determined that there is no error, a data complete signal DC is output to the MPU 9, and a data transfer mode signal is also output. Data A is then transferred. Next, the address is updated, and the next address B is checked for tag errors and data errors in SR'AM.

When it is determined that there is no error, the data complete signal DC and data B are output to the MPU 9. Thereafter, data C9D is transferred in exactly the same manner.

As described above, according to the present invention, tag data and SRAM
The data transfer mode can be switched depending on the frequency of occurrence of data errors within the data transfer mode. Note that switching the data transfer mode is not based on the frequency of memory errors, but based on the MPU9.
It can also be performed according to the process executed by. That is, for example, mode "2" is used for a specific process that would have a large effect if incorrect data were used.

〔Effect of the invention〕

As explained above, by using the memory access mode switching method of the present invention, it is possible to configure a high-speed and error-resistant system without sacrificing the processing capacity of the central processing unit of the computer system. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention. FIG. 2 is a block diagram showing the overall configuration of an embodiment of a cache memory system. FIG. 3 is a block diagram showing the basic configuration of an embodiment of a timing control section. is a time chart of an embodiment of data block transfer, and FIG. 5 is a time chart of a conventional example of a data transfer method. 1... Cache memory, 2... Tag memory, 3... SRAM. 9...MPU. 13... Error analysis control section, 14... Timing control section.

Claims (1)

[Claims] A tag memory (2) that stores the address on the main memory (6) of stored data as tag data, and a static random access memory SR that stores the stored data.
In the cache memory (1) consisting of an AM (3), an error analysis means (4) performs an error check on the tag data of the tag memory (2) and the data stored in the SRAM (3).
), and timing control means (
5), transmitting the data to the central processing unit (7) before the error check result by the error analysis means (4) is known;
A first data transfer mode in which when it is determined that an error has occurred, the central processing unit (7) is notified of the error occurrence through an interrupt; and a point in time when it is determined that there is no error as a result of error checking by the error analysis means (4). A memory access mode switching method characterized in that it is possible to switch between a second data transfer mode for transferring data to the central processing unit (7) and a second data transfer mode for transferring data to the central processing unit (7).