JPH0230547B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an external memory device that is detachably attached to the main body of an electronic musical instrument.

BACKGROUND ART Electronic musical instruments are sometimes provided with a removable external memory device so that settings of panel operators such as timbre switches and effect switches or performance processes can be recorded. Magnetic cards, magnetic tapes, magnetic bubble memories, EEPROMs, etc. are known as external memory devices, but CMOS battery backup is particularly popular as it has a simpler peripheral circuit and is cheaper than other types of memory. UP memory (hereinafter abbreviated as CMOS memory) is known.

FIGS. 1 and 2 are diagrams showing the external appearance and internal configuration of a conventional CMOS memory 1, respectively. In FIG. 1, reference numeral 2 is a power pin, 3 is a chip enable pin, and 4 is an address pin and a data pin, and these pins 2 to 4 are each inserted into a connector on the main body of the electronic musical instrument. Also, in Figure 2,
5 is CMOS-RAM, and this CMOS-RAM
Terminals T _V and T _CE are a power supply terminal and a chip enable terminal, respectively. Note that this CMOS-RAM is of course provided with data terminals and address terminals, but they are not shown here. this
The CMOS-RAM 5 becomes enabled, that is, readable/writable state, when the voltage V _CE at the “L” level (0V) is supplied to the terminal T _CE ; When the voltage V _CE is supplied, it becomes a disabled state (read/write disabled state). 6 is the output voltage V _B
backup battery, 7 and 8 are diodes, 9
is a resistor, and 10 is a capacitor for stabilizing the power supply voltage. Further, reference numerals 11 and 12 indicate the connections between the pins 2 and 3 and the connector of the main body of the electronic musical instrument using switches.

When this CMOS memory 1 is inserted into the connector of the main body of the electronic musical instrument, the power supply voltage V _P (V _P > V _B ) output from the power supply section inside the electronic musical instrument is passed through the switch 11, pin 2, and diode 8. CMOS
It is supplied to the terminal TV of RAM5 (voltage _{V CC} ), and
The chip enable signal CE output from the control section of the electronic musical instrument is sent to the terminal T _CE via switch 12 and pin 3.
(voltage V _CE ). On the other hand, when this CMOS memory 1 is unplugged from the connector of the electronic musical instrument, switches 11 and 12 are both turned off, and the output voltage of the battery 6 is
V _B is applied to the terminal as voltage V _CC through diode 7.
_{The voltage V CC is} supplied to the terminal T _CE via the resistor 9 . Furthermore, as is well known,
For CMOS-RAM5, when performing read/write processing, the power supply voltage V _CC supplied to terminal _TV must be 4.5V or higher, while when not performing read/write processing, the power supply voltage is approximately 2V. Data can be retained by V _CC . Therefore, 5.0V and 2.2V are usually used as the voltages V _P and V _B.

By the way, when playing an electronic musical instrument, the above-mentioned CMOS memory 1 is stored in advance with data regarding the setting status of the panel controls, etc., and the CMOS memory 1 is inserted into the connector during the performance.
There are cases where you want to use the internal data immediately. In such a case, in order to utilize the data in the CMOS memory 1 in the shortest possible time, it is desirable to hold the chip enable signal CE at the "L" level in advance. However, in the case of the above-mentioned CMOS memory 1, the chip enable signal CE is set to "L" in advance.
If you leave it at a low level, the data in CMOS-RAM5 may be destroyed. The reason for this will be explained below.

First, the following characteristics are known as the characteristics of CMOS-RAM5.

When the CMOS memory 1 is inserted into the connector, the voltage V _CE must be held at the "H" level for a predetermined period of time (for example, 200 nsec) from the time when the voltage V _CC exceeds 4.5 V. Voltage
As soon as V _CC reaches 4.5V, voltage V _CE is set to “L”
level, the internal data will be destroyed.

When the voltage V _CC is 4.5V or less, set the voltage V _CE to “H”
must be maintained at the level. If this condition is violated, the internal data will also be destroyed.

On the other hand, FIG. 3 shows the power supply voltage V _CC (solid line) and chip enable voltage V _CE (dashed line) when the CMOS memory 1 is inserted into and removed from the connector with the signal CE set to "L" level in advance. ) is a diagram showing changes in . In this figure, time t ₁ is the switch 11 shown in FIG.
is turned on, and the power supply voltage V _CC gradually rises after this time t ₁ due to the action of the capacitor 10, reaches 4.5V at time t ₂ , and finally reaches 5V.
becomes. Note that the voltage drop across the diode 8 is ignored. On the other hand, switch 12 is switch 1
1 is turned on at time t ₃ after a predetermined time T ₁ has elapsed, and at this time t ₃ the voltage V _CE becomes “L” level. Here, the time T ₁ is the time difference caused by the different lengths of pins 2 and ₃ shown in FIG. If you insert it slowly, the time T ₁ will increase.

However, when plugging in, CMOS-RAM5
In order for _the data in
later than t ₂ , and the time difference T ₂ between time t ₂ and t ₃
must be greater than 200n sec. However, if CMOS memory 1 is inserted into the connector rapidly, or if CMOS memory 1 is not inserted properly and is inserted and removed many times within a short period of time, the above conditions may not be satisfied. In this case, the data in the CMOS-RAM 5 will be destroyed. Note that time t ₄ is the time when the switch 12 is turned off, and time t ₅ is the time when the switch 11 is turned off.
is the time when is turned off, and in this case (i.e., when removing CMOS memory 1), the power supply voltage
When V _CC is below 4.5V, voltage V _CE is always “H”
level and therefore the data will not be destroyed.

In this way, the conventional
If the signal CE is held at “L” level, the CMOS memory 1 will be able to connect to the CMOS-RAM at the time of insertion.
5 may be destroyed. Therefore,
So that the voltage V _CE falls slowly when plugged in.
It is conceivable to insert a capacitor between the terminal _TCE of CMOS-RAM5 and ground. However, when this capacitor is inserted, the rise of the voltage V _CE at the time of removal is delayed, and as a result, when the power supply voltage V _CC drops below 4.5 V, the voltage V _CE may still be at the "L" level. , in this case, the data will be destroyed.

As described above, in the conventional CMOS memory 1, it is impossible to hold the signal CE at the "L" level in advance, and for this reason, the following means are generally used.

(i) Normally, the signal CE is held at the "H" level, and only when performing read/write processing of the CMOS-RAM 5, the signal CE is set to the "L" level using a manual switch.

(ii) A cover is attached to the place where the CMOS memory 1 is inserted, and a switch 14 (see Fig. 4) is provided which is turned on when the cover is opened and turned off when it is closed. As shown in FIG. 4, when the lid is in the open state, the signal CE is at the "H" level, and when the lid is in the closed state, the signal CE is at the "L" level. If you do this, the signal will not start until you insert CMOS memory 1 into the connector and close the lid.
CE becomes "L" level, thus data destruction can be prevented.

However, according to the means (i) or (ii) described above, some operation is required after inserting the CMOS memory 1, and therefore the data cannot be used at the same time as the CMOS memory 1 is inserted. , signal CE
The circuit that controls this becomes complicated, leading to increased costs.

In view of the above circumstances, the present invention has been developed to allow the internal data to be used immediately by simply inserting the electronic musical instrument into the connector of the main body, and to enable the chip enable signal.
This provides an external memory device for electronic musical instruments that does not require any CE control, and the power supply voltage supplied to the storage means (for example, CMOS-RAM 5 in Figure 2) is a specified voltage (4.5V in Figure 2). A control means is provided inside the memory device to supply a disable signal to the storage means from the time when the specified time has elapsed until a certain period of time has elapsed, and to supply an enable signal to the storage means after the certain period of time has elapsed. It is a feature.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 5 is a diagram showing the configuration of a CMOS memory 20 (external memory device) according to the present invention, and in this figure, parts corresponding to those in FIG. 2 are given the same reference numerals. In Figure 5,
The voltage V _P is _the power supply voltage output from the power supply section of the electronic musical instrument.
A voltage higher than RAM5's rated power supply voltage of 5V (e.g.
12V) is used. This voltage V _P is switch 1
1 to power supply pin 2. A capacitor 21 and a resistor 22 are connected between pin 2 and ground.
23 series circuits are inserted, and pin 2 is connected to one end of resistor 24. The other end of the resistor 24 is a Zener diode 25 with a Zener voltage of 5V.
and the anode of the diode 8, the anode of the Zener diode 25 is grounded, and the cathode of the diode 8 is connected to the CMOS-RAM
It is connected to the power supply terminal _TV of 5. Also,
The collector of the transistor 27 is connected to the chip enable terminal _TCE of the CMOS-RAM 5, the emitter of the transistor 27 is grounded, and the base is connected to the connection point between the resistors 22 and 23. here,
The resistance values of resistors 22 and 23 are such that the voltage at pin 2 is approximately
The transistor 27 is set to turn on when the voltage reaches 11V. Note that the connections of the battery 6, diode 7, and resistor 9 are the same as in FIG.

Next, the operation of the above-described CMOS memory 20 when it is inserted into and removed from the connector will be explained with reference to the waveform diagram shown in FIG. Note that in the following explanation, the voltage drop across the diodes 7 and 8 will be ignored. The curves shown in FIG. 6 are the voltage V _A at pin 2, the cathode voltage V _D of the Zener diode 25, the voltage V _CC applied to the power supply terminal TV of the CMOS-RAM 5, and the chip enable terminal T of the _CMOS -RAM 5, respectively. It shows the change in voltage V _CE applied to _CE .

First, when the CMOS memory 20 is removed from the connector of the main body of the electronic musical instrument, the voltage V _CC is the voltage of the battery 6, which is 2.2V, and since the transistor 27 is in the off state, the voltage V _CE is also 2.2V.
(“H” level).

Next, at time t ₁ shown in the same figure, the CMOS memory 20 is inserted into the connector of the electronic musical instrument body, and the switch 11 is turned on, and the voltage V _A gradually increases from 0 V due to the action of the capacitor 21. However, along with this, the voltage V _D also gradually increases. Then, when the voltage V _D exceeds 2.2V, diode 7
is reverse biased, so that henceforth the voltage V _CC will be the same as the voltage V _D. Voltage V _A further increases to 5V
When the voltage V D and V CC reach 5 V, the Zener diode 25 acts to maintain both the voltages V _D and V _CC at 5 V.
Further, at this point, the transistor 27 is still in the off state, so the voltage V _CE is also 5V. When the voltage V _A further increases and reaches 11V (time t ₃ ),
Transistor 27 is turned on. As a result, the voltage V _CE becomes 0V, and from then on CMOS-RAM5
can be read/written.

The above is the operation of the CMOS memory 20 at the time of insertion. In the above operation, the voltage V _CC
Assuming that the time when the voltage reaches 4.5V is _t2 (FIG. 6), before this time _t2 , that is, when the voltage _VCC is 4.5V or less, the voltage _VCE is kept at the "H" level. Also,
The time T from this time t ₂ to the time t ₃ when the voltage V _CE becomes 0V is the time until the voltage V _A becomes 11V from 4.5V, and this time T can be changed by adjusting the capacitance of the capacitor 21. , 200n sec or more is fully possible. That is, when this CMOS memory 20 is inserted, the CMOS memory 20 described above is
-Conditions for not destroying data in RAM5,
We are both satisfied.

Next, the operation at the time of extraction will be explained. Now, the 6th
At time _t4 shown in the figure, when the CMOS memory 20 is removed from the connector and the switch 11 is turned off, the voltage V _A gradually decreases to 0V due to the action of the capacitor 21. . When voltage V _A becomes less than 11 V at time t ₅ , which is slightly after time t ₄ , transistor 27 is cut off. At this time, the voltage V _CC is still at 5V, so the cut-off of transistor 27 causes the voltage V _CE to be 5V.
(“H” level). The voltage V _A further decreases,
After reaching 5V, the voltages V _D , V _CC , and V _CE become the voltage V _A
decreases with the decrease of . And the voltage V _A is 2.2V
When reaching , diode 7 becomes forward biased,
After that, both voltages _CC and V _CE are held at 2.2V, and
The voltages V _A and V _D further decrease and reach 0V.

The above is the operation during extraction. In the above operation, when the voltage V _CC falls below 4.5 V (after time t ₅ shown in Figure 6), the voltage V _CE is at "H" level, and therefore the data in CMOS-RAM 5 is There is no fear that it will be destroyed.

In this way, the CMOS memory 20 shown in FIG.
can set the chip enable voltage V _CE to 0V by simply plugging it into the connector of the electronic musical instrument.
Therefore, the data in the CMOS-RAM 5 can be used at the same time as it is inserted. Furthermore, as is clear from the fact that the chip enable signal CE in FIG. 2 is not used, there is no need to control the chip enable signal CE on the electronic musical instrument side. Furthermore, when inserting and removing
There is no risk that the data in CMOS-RAM5 will be destroyed.

In addition, although the CMOS-RAM 5 is used as a storage means in the above-mentioned embodiment, it is of course possible to use other types of RAM in the present invention.
In addition, the CMOS-RAM5 in the above-mentioned embodiment
If the address terminal (not shown) becomes open, the internal data is not guaranteed.
Therefore, the address terminal of CMOS-RAM5 is
It is necessary to ground the CMOS memory 20 through a resistor.

Next, FIG. 7 is a block diagram showing an example of an electronic musical instrument using the above-mentioned CMOS memory 20.
In this figure, a key switch circuit 30 detects the on/off state of each key on a keyboard (not shown) based on the output of a key switch provided corresponding to each key, and codes the key of the key that is currently in the on state. The KC is outputted to the musical tone signal forming section 31 and the performance recording/playback control circuit 32. The panel setting section 33 is a circuit that outputs panel data PD corresponding to the operation status of each operation switch (tone setting switch, effect setting switch, etc.) on the operation panel surface, and the output panel data PD is transmitted to the musical tone signal forming section 31. and is supplied to the preset control circuit 34. The musical tone signal forming section 31 forms a musical tone signal having a pitch corresponding to the key code KC and a musical tone aspect (timbre, effect, etc.) corresponding to the panel data PD, and outputs it to the sound system 35. Further, when the preset switch on the operation panel is operated, a musical tone signal having a musical tone mode corresponding to the preset data PSD outputted from the preset control circuit 34 is generated and output.

On the other hand, when the CMOS memory 20 is inserted into the connector, the connector circuit 36 detects this and outputs a signal P to the external memory R/W (read/write) control circuit 37. External memory R/W control circuit 3
7 receives this signal P and outputs a signal Q to the preset control circuit 34. Preset control circuit 34
receives this signal Q and reads the CMOS memory 20.
The panel data in the CMOS-RAM 5 is read out and the musical tone signal forming section 31 reads it as preset data PSD.
Output to. Thereby, the musical tone signal forming section 31 forms and outputs a musical tone signal based on the panel data in the CMOS-RAM 5. The performance recording/playback control circuit 32 includes a key switch circuit 30
The key code KC output from the internal
The key code KC is recorded in the RAM, and the recorded key code KC is sequentially output to the musical tone signal forming section 31 based on instructions from the operation switch on the operation panel. Also, under the control of the external memory R/W control circuit 37, the CMOS
- Read the key codes recorded in the RAM 5 and sequentially output them to the musical tone signal forming section 31. In this case, the musical tone signal forming section 31 forms and outputs a musical tone signal based on the key code output from the performance recording/playback control circuit 32. In addition, CMOS
- The output of the panel data read from the RAM 5 to the tone signal forming section 31 may be controlled by a separately provided switch.

As explained above, according to the present invention, a disable signal is sent to the storage means (for example, CMOS-RAM) for a certain period of time after the power supply voltage supplied to the storage means (for example, CMOS-RAM) reaches a specified voltage. control means (for example, the transistor 27 and the resistors 22 and 2 in FIG.
3. Since a circuit consisting of a capacitor 21 is provided inside the memory device, by simply inserting the external memory device according to the present invention into the connector of the main body of the electronic musical instrument, the internal data can be immediately used, and the storage means can be used. This has the advantage that the data within the electronic musical instrument can be reliably protected, and there is also the advantage that there is no need to provide a control circuit for controlling the voltage of the chip enable terminal in the main body of the electronic musical instrument.

[Brief explanation of drawings]

Figures 1 and 2 are an external view and an internal configuration diagram of a conventional CMOS memory, respectively, and Figure 3 is the same.
Waveform diagram to explain the characteristics of CMOS memory,
FIG. 4 is a circuit diagram showing an example of a circuit that controls the voltage applied to pin 3 of the CMOS memory, FIG. 5 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG.
The figure is a waveform diagram for explaining the operation of the embodiment, and FIG. 7 is a block diagram showing an example of the configuration of an electronic musical instrument using the CMOS memory according to the embodiment. 2...Power pin (power input terminal), 5...
CMOS-RAM (storage means), 6... Backup battery, 7, 8... Diode, 21... Capacitor, 9, 22, 23, 24... Resistor, 25...
Zener diode, 27...transistor.

Claims (1)

[Scope of Claims] 1. An external memory device configured to be detachably attached to the main body of an electronic musical instrument, comprising: a storage means, a backup battery, a power input terminal, and a power supply input terminal supplied from the main body of the electronic musical instrument to the power input terminal. a power supply circuit driven by a power supply and having a time constant circuit; when the output voltage of the power supply circuit is below a predetermined value, the output voltage of the backup battery is supplied to the storage means; when the output voltage is above the predetermined value, the output voltage of the backup battery is supplied to the storage means; a switching means for supplying the output voltage of the power supply circuit to the storage means; and a switching means for supplying the output voltage of the power supply circuit to the storage means; an external memory device for an electronic musical instrument, comprising control means for supplying a disable signal to the memory device and supplying an enable signal after the predetermined period of time has elapsed.