JPS633039Y2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to the configuration of an erasing circuit that eliminates the erasure of recorded information due to malfunction of the erasing signal circuit when turning on and off the power of a magnetic bubble memory device.

(b) Technical background Magnetic bubble memory (hereinafter abbreviated as bubble memory)
is a non-volatile magnetic memory developed with the aim of realizing a small, high-performance solid-state file memory, and it has high reliability because it does not include any mechanically moving parts. Here, as a method for implementing bubble memory, we will use a bubble memory device as a coil drive circuit,
A method of using a bubble memory device as a memory card by mounting it on a printed wiring board together with direct peripheral circuits such as a function drive circuit and sense amplifier, and indirect peripheral circuits such as a timing circuit and a control circuit, and a method of forming a bubble memory device into a cassette shape. There is a method in which the memory card has a removable structure and is connected to direct peripheral circuits and indirect peripheral circuits mounted on the memory card through a cassette holder. The present invention relates to an erase circuit that eliminates malfunctions caused by voltage fluctuations when used as the latter cassette-shaped memory device (hereinafter referred to as a bubble cassette).

(c) Prior art and problems Figure 1 shows a conventional erasing circuit.
That is, the bubble cassette has a built-in erase coil L for erasing all bubble information. Here, the method for erasing bubble information is to send an H level signal to the terminal E of the erasure signal circuit 1, and the transistor
By turning on Tr1, Tr2 is turned on, and the erase power supply V _E supplies an erase current to the erase coil L through the resistor R1 and the transistor Tr2, and the resulting magnetic field is applied to the bubble memory chip. Since a bias magnetic field is applied to the bubble chip memory using a permanent magnet, the magnetic field values generated by the erasing coil L are added together to reach the collapse magnetic field value of the bubble, and all bubble information is erased. be done. As mentioned above, bubble information is erased by sending an H level signal to the terminal E of the erase signal circuit 1, which is used in this circuit 1.
If the operating voltage of the IC deviates from the guaranteed operating voltage range, the IC will become unstable and the transistor Tr1 will
The base potential of the transistor Tr becomes H level and the transistor Tr
1 turns on, the transistor Tr2 turns on and the bubble information may be erased. Since such unstable IC operation occurs when the power is turned on and off, conventionally it was necessary to take a protective measure by removing the bubble cassette from the cassette holder before turning on and off the power. .

(d) Purpose of the invention The purpose of the invention is to provide a configuration of an erasing circuit that can turn on and off the power while the bubble cassette is inserted into the cassette holder.

(e) Structure of the invention The purpose of the invention is to provide a power-off warning signal circuit and a reset signal circuit in parallel with the erase signal circuit connected to the base of the transistor via a TTL circuit, so that the voltage change of the erase power supply exceeds a specified level. This can be achieved by using a circuit in which both of the circuits switch from the H level to the L level and maintain the base potential of the transistor at the L level to compensate for unstable operation of the IC.

(f) Example of implementation of the invention Figure 2 shows a transistor that is used only during the fluctuation time of the erase voltage.
This is a circuit that locks the base potential of Tr1 to L level, and the open collector logic shown in Fig. 1 is used.
Erasing signal circuit 1 consisting of IC and transistor Tr1
The configuration of the erase circuit remains unchanged, except that it is replaced with the second circuit. In other words, the power cutoff warning signal (PF) is connected in parallel to the conventional erase signal circuit 1 that outputs the erase signal (EC).
A circuit 2 for generating a reset signal (RST) and a circuit 3 for generating a reset signal (RST) are provided and connected to the base of the transistor Tr1, thereby locking the base potential of the transistor Tr1 at the L level only during the period of fluctuation of the power supply voltage.

The present invention will be described below using the drawings as an example of a case where a power outage occurs.

FIG. 3 shows the time relationship between signals sent to the power-off warning signal (PF) circuit 2 and the reset signal (RST) circuit 3 in response to fluctuations in the power supply voltage. In this embodiment, the power supply voltage 4, which was maintained at 12 [V] ±2 [%], drops to a state of potential 5 of 0 [V] due to the power cutoff. Therefore, the operating voltage of the IC in the erase signal circuit 1 shown in Figure 2 also decreases, but since the guaranteed operating voltage range of the IC is 4.75 [V] ±5 [%], if the voltage drops significantly more than this, there is a risk of malfunction. Gender arises. Therefore, when the power supply voltage value shown in FIG. 3 drops to the first level A due to a power cut, the power cut warning signal circuit 2 changes from the conventional H level to the L level, and therefore the base potential of the transistor Tr1 is suppressed to the L level. . In this case, even if the erase signal circuit 1 goes to H level due to a malfunction of the IC, since the voltage correction diode D1 is provided on the emitter side of the transistor Tr1, the current will flow through the diode D2, and the current will flow through the transistor Tr1.
The base potential of 1 never becomes H level. Next, when the power supply voltage further decreases and reaches the second level low, the reset signal circuit 3 changes from the H level to the L level. In this way, due to fluctuations in power supply voltage,
Even if the operating voltage of the IC exceeds the guaranteed operating range and outputs a signal at H level, the guarantee circuit according to the present invention can lock the base potential of transistor Tr1 at L level, so there is no risk of bubble information being erased due to malfunction of the IC. You can eliminate sexuality.

(g) Effects of the invention By implementing this invention, the power supply can be turned on and off like before.
There is no need to remove the bubble cassette when turned off, and the reliability of the bubble memory can be improved.

[Brief explanation of the drawing]

FIG. 1 shows a conventional bubble memory erasing circuit, FIG. 2 shows a circuit that locks the base potential of transistor Tr1 at L level, and FIG. 3 shows the time relationship between voltage fluctuations and the PF signal and RST signal. In the figure, 1 is an erase signal circuit, 2 is a power-off warning signal (PF) circuit, 3 is a reset signal (RST) circuit, A is a first level, and B is a second level.

Claims (1)

[Scope of utility model registration request] In a transistor circuit for erasing recorded information by energizing an erasing coil built in a magnetic bubble memory device from an erasing power supply, a power cutoff notice signal circuit and a reset signal circuit are provided in parallel with an erasing signal circuit connected to the base of the transistor, When the voltage change of the erase power supply exceeds a specified level, the outputs of both circuits are switched to keep the transistor in the off state.
A magnetic bubble memory erase circuit characterized by compensating for unstable operation of an IC.