JPH0230575B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to polysilicon self alignment technology, which has recently attracted attention.
The present invention relates to a method for manufacturing semiconductor devices, particularly bipolar transistors, using PSA technology (hereinafter referred to as PSA technology).

PSA technology is a process that aims to enable bipolar transistors to operate at low power without sacrificing high speed. It is becoming frequently used due to the demand for miniaturization of transistors.

In the above-mentioned LSI, the bipolar transistor that is naturally used is used.In order to operate at low current, the load resistance of the transistor is increased to suppress the collector current, while in order to increase the speed, the parasitic capacitance and base resistance of each part are reduced, and the emitter It has been found that it is best to make each diffusion depth of the base and the base shallow.

In order to reduce the base resistance together with the emitter series resistance, the resistance value of the polysilicon wiring in contact with the base and emitter diffusion layers can be changed by, for example, making the upper surface of the polysilicon wiring a metal silicide, such as platinum-silicide (hereinafter referred to as Pt-silicide). In order to reduce the parasitic capacitance, most of the above-mentioned polysilicon wiring and also polysilicon It is preferable to use a method such as forming the resistors to be formed on a thick field oxide film.

Figure 1 shows a cross-sectional view of an active element, that is, a conventional bipolar transistor for LSI, which is formed with this design concept in mind.For example, if it is a PnP type, the semiconductor substrate (n type)
For example, the thickness formed on a predetermined surface portion of
There is P ⁺ between the field oxide films 2 of about 1 μm.
Active regions such as a type collector contact impurity doped layer 12 and an n type base impurity doped layer 3 are formed, and a P ⁺ type emitter impurity doped layer 4 is formed in a part of the base impurity doped layer 3. There is. In addition, 14 is a P type collector impurity doped layer, 15 is a P ⁺ type buried layer, 13 is a polysilicon resistor, 5, 6, 7 are each polysilicon wiring for emitter, base and collector, 8, 9, 1
0 is a Pt--Si layer formed on the upper surface of the polysilicon wirings 5, 6, and 7 for the purpose of reducing the resistance value thereof, and 11 is an oxide film for defining the emitter and base.

In the conventional method of forming the emitter, base, and collector wirings and resistors using a polysilicon film as shown in Fig. 1, the base impurity doped layer 3 is first formed as shown in Fig. 2a. Semiconductor substrate 1
A polysilicon layer as shown at 21 is provided entirely on the surface of the field oxide film 2 and on the surface of the field oxide film 2. Then, after covering the top with a nitride film (Si ₃ N ₄ ) 20, an opening window as shown at 22 is opened in a predetermined part of the nitride film 20, and then placed in an oxidizing atmosphere. The polysilicon film directly under 22 is made of silicon dioxide (SiO ₂ ) as shown in Figure 2b.
A film (hereinafter simply referred to as an oxide film) 23 is formed.

In this way, the emitter wiring, base wiring, collector wiring, and polysilicon layers 5, 6, 7, and 13 used as resistors are separated, so that the emitter 4 and the P ⁺ type collector contact impurity-doped layer are then separated. By removing the nitride film on the region where No. 12 is to be formed and diffusing boron (B), the base impurity doped layer 3 is formed as shown in FIG. 2b.
There is a P ⁺ type emitter impurity doped layer in a part of the
A P ⁺ collector contact impurity doped layer 12 is formed on the surface of the collector impurity doped layer 14.
The PnP transistor is completed. However, in FIGS. 2a and 2b, the same parts as in FIG. 1 are designated by the same reference numerals.

However, when adjusting the resistance value of the polysilicon as the resistor 13 formed on the field oxide film 2 by, for example, implanting impurity ions into it, the thickness of the polysilicon film is
If it is less than 0.3 μm, an inconvenient phenomenon will occur in which the thickness dependence suddenly becomes large, so it is desirable to set the thickness of the polysilicon film for the resistor 13 to be large.

On the other hand, for polysilicon wiring in various parts of the active region such as the emitter, base, and collector, a Pt-Si layer is placed on the top surface of these wirings, or a low resistance layer is formed by ion implantation. However, the emitter, base, and collector contact surfaces 18, 16, and 27 of each of these wirings 5, 6, and 7 shown in FIG.
A certain degree of resistance value exists between 9, 17, and 28, which causes the disadvantage that the speed of this semiconductor device, that is, the transistor becomes slow. Therefore, the thickness of the wiring polysilicon 5, 6, 7 must be made small.

In order to satisfy these two conflicting demands, the present inventor first provided a first polysilicon layer on the field oxide film 2 and the semiconductor substrate 1 in the active region, and then formed a polysilicon layer to serve as a resistor. The silicon film is left on the field oxide film, the polysilicon on the active region is removed, and a second polysilicon film is newly deposited on the entire surface, thereby making the resistor polysilicon film 13 thick and thick. A method for manufacturing a semiconductor device in which wiring polysilicon films 5, 6, and 7 are formed thinly is provided.

Here, a method for forming the collector contact impurity doped layer 12 and the emitter impurity doped layer 4 will be described.

For a transistor in which the collector impurity layer 4 has been formed in advance and the base impurity layer 3 is further formed in a part thereof, a thickness of, for example, about 1 μm is shown as surrounded by a dotted line in FIG. 2b. After covering the surface of the transistor with a resist film 50 of By implanting ions, the emitter impurity doped layer 4 and the collector contact impurity doped layer 12 are formed.

Here, if we leave aside the collector contact impurity doped layer 12 and focus on the emitter impurity doped layer 4, the position of the end P of the impurity doped layer 4 is oxidized on the base impurity doped layer used as a part of the mask. This is determined by the width of the film 23. In this case, if the width d of the oxide film 23 made by oxidizing the polysilicon 21 is large, there will be a gap between the end P of the emitter impurity doped layer 4 and the end of the base polysilicon wiring 6. It will happen. Therefore, in the base impurity doped layer 3 shown in FIG. 2b, a parasitic base resistance r occurs between the end P of the emitter impurity doped layer and the bottom Q of the base polysilicon wiring. A high value of the parasitic base resistance r causes the transistor to lose its high speed performance.

Therefore, it is desirable that the lateral length d of the oxide film 23 on the base impurity doped layer is small.

However, as described above, this oxide film 23 is made by oxidizing a part of the polysilicon that is disposed all at once to constitute the base, emitter, and collector wirings as well as the resistor on the field oxide film. Ta. When using the polysilicon 13 on the field oxide film as a resistor, the polysilicon 13 is made to have a large thickness of, for example, 0.7μ, so that thickness dependence does not appear when controlling the resistance value by a method such as ion implantation. It is formed in Incidentally, the thickness of the wiring polysilicon film 6 is selected to be approximately 0.2 μm. However, in FIG. 2b, in order to avoid complication, it is omitted that the resistor polysilicon 13 on the field oxide film 2 is particularly thick. Therefore, if we were to accurately draw a cross-sectional structural diagram of the main parts, leaving only the parts necessary for the following discussion, we would end up with something like Figure 3. In the following, the oxide film on the base impurity doped layer is referred to as 23a to distinguish it from the oxide film on the field oxide film in FIG.
to distinguish them.

Before being oxidized, the oxide film on the field oxide film 2 shown as 23b in FIG. μm second
As a result of overlapping polysilicon films, the total thickness increased to 0.7 μm. On the other hand, the oxide film on the base impurity doped layer shown as 23a in the figure is also a second polysilicon film disposed to have a thickness of, for example, 0.2 μm before oxidation. .

As described above, although the thickness of the polysilicon at the two locations differs greatly, the oxidation rate is constant. Therefore, when selectively oxidizing the polysilicon at the above two locations in the same oxidizing atmosphere, the polysilicon on the base impurity doped layer, which is smaller in thickness, naturally oxidizes earlier than the polysilicon on the field oxide film. Although the oxidation is completed, selective oxidation of the polysilicon on the field oxide film is not completed at that point. When the selective oxidation of the polysilicon on the field oxide film is completed, the polysilicon that has already been oxidized on the base impurity doped layer has been oxidized in the lateral direction, and the mask for selective oxidation is This results in an oxide film that spreads laterally beyond the opening of the nitride film used as a nitride film.

In this case, as described above using FIG. 2b, ion implantation will be performed using this extra lateral oxide film as part of the mask, so as shown in FIG. The end P of the emitter impurity doped layer 4 is further away from the bottom Q of the polysilicon wiring 6 in the figure, and as a result, the parasitic resistance r
This results in the inconvenience of an increase in .

The present invention has been made in view of these drawbacks, and is based on the fact that selective oxidation of the thin polysilicon on the base impurity doped layer is completed and the base polysilicon wiring is formed at the boundary between the base impurity doped layer and the emitter impurity doped layer on the surface of the active region. Once the oxide film that defines the ends of the pattern and the emitter polysilicon wiring pattern has been formed, a new nitride film is formed in the openings of the nitride film used as a mask for selective oxidation.
The method described above involves depositing the polysilicon by CVD or the like to prevent the opening and preventing further oxidation, and then proceeding to selectively oxidize the thick polysilicon on the field oxide film. This is intended to suppress phenomena such as an increase in parasitic base resistance, and will be described using the drawings from FIG. 4 onwards.

FIGS. 4a and 4b are cross-sectional views of essential parts showing the method of manufacturing a semiconductor device according to the present invention, particularly the step of selective oxidation of polysilicon disposed on the base impurity doped layer and the field oxide film, which will be directly discussed. Unnecessary parts are omitted from the illustration. In this figure, the same portions as in FIGS. 1 to 3 are denoted by the same reference numerals, and only the portion where the emitter impurity doped layer is formed is indicated by a dotted line A.

The polysilicon 21 formed at different thicknesses as described above on the base impurity doped layer 3 and the field oxide film 2 is uniformly covered with the first nitride film 51, and the upper surface of the base impurity doped layer and the field oxide film are covered with the first nitride film 51. If an opening is provided in a predetermined portion of the upper surface of the substrate 2 and placed in an oxidizing atmosphere, the exposed portion of the polysilicon will be oxidized sequentially from above in the opening. When the polysilicon on the base impurity doped layer is completely oxidized and becomes an oxide film 23a as shown at 54 in FIG.
The polysilicon in the area indicated by is so thick that it has not been completely oxidized yet.

As shown in FIG. 4B, when the portion indicated by 54 is completely oxidized, an opening is formed on the opening of the first nitride film 51 serving as a mask, that is, on the top of the oxide film 23. A second nitride film 56 is deposited in a shape that covers the area, and patterning is performed. Then, oxidation of the partially oxidized polysilicon shown in 53 above is continued again in an oxidizing atmosphere. In this way, the portion indicated by 53 is finally completely oxidized and becomes an oxide film 23b as shown in FIG. 4b. As a result, the polysilicon 21 is separated to form emitter, base, and collector wirings 5, 6, and 7, respectively.

In addition, in FIG. 4a, symbols 23a shown in parentheses below each of symbols 54 and 21, and symbols 5, 6, and 7 indicate the parts that should become after the above processing is completed.

In this way, the oxide film 23a formed on the base impurity doped layer 3 will not spread oxidized in the lateral direction, so even if an emitter impurity doped layer is formed later, that portion P and the bottom Q of the base polysilicon wiring 6, and the resistance r formed between the bottom Q and the end P does not increase.

The method for manufacturing a semiconductor device, that is, a transistor according to the present invention described above does not require any major process changes, and if applied to the manufacturing of transistors in an LSI, the high-speed performance of the LSI will not be impaired. Therefore, since high performance can be maintained, great practical effects can be expected.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the cross-sectional structure of a semiconductor device, that is, a transistor, formed using normal PSA technology, FIGS. 2a and b are diagrams showing the conventional manufacturing method of the transistor, and FIG. FIGS. 4a and 4b are cross-sectional views of essential parts showing that the resistor polysilicon is particularly thick. FIGS. 1: semiconductor substrate, 2: field oxide film, 3;
Base impurity doped layer, 5: Emitter polysilicon wiring, 6: Base polysilicon wiring, 7: Collector polysilicon wiring, 21: Polysilicon film,
23a: Emitter, oxide film for base definition, 23
b: Polysilicon resistor 13 on field oxide film
51: first nitride film;
56: Second nitride film.

Claims (1)

[Claims] 1. A thin polysilicon layer is formed on a region including an active region on which a base impurity doped layer and an emitter impurity doped layer are formed, and a thick polysilicon layer is formed on a field oxide film. When forming a base polysilicon wiring pattern, an emitter polysilicon wiring pattern, and a resistor by oxidizing predetermined portions of silicon, the thin polysilicon and thick polysilicon described above are once covered with a nitride film, and then the predetermined portions are oxidized. a first step of forming an opening in the active region; and oxidizing the polysilicon immediately below each of the nitride film openings in an oxidizing atmosphere to form an oxide film. When an oxide film defining the ends of the base polysilicon wiring pattern and the ends of the emitter polysilicon wiring pattern is formed at the boundary between the base impurity doped layer and the emitter doped layer on the surface of the active region, the active region a second step of disposing and patterning a second nitride film so as to cover the nitride film opening on the field; A method for manufacturing a semiconductor device, comprising a third step of completely oxidizing polysilicon.