JPH02306775A - Contour correction circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a contour correction circuit in video signal processing.

[Conventional technology]

The simplest contour correction circuit is known to superimpose a second-order differential signal of a video signal on the original signal, thereby making the contour apparently steeper. However, this method has the side effect of causing pre-shoot and post-shoot ringing before and after the contour.

In order to avoid the above-mentioned side effects, for example, in Japanese Patent Application Laid-Open No. 61-33078, a charge transfer device (CCD) with a capacity for one horizontal scanning period (IH) is used, and the write clock is set to the secondary of the video signal. The rise time of one contour portion is compressed by modulating the differential component and setting the read clock at a constant frequency. Also, JP-A-63-4688
In No. 1, data is written into the memory using a constant frequency clock.

The phase of the read clock is made variable according to the second-order differential signal, and the same effect as in the prior art example described above is obtained.

[Problem to be solved by the invention]

Techniques for controlling clock timing include, for example, V
BACKGROUND ART A TBC (time base corrector) that corrects time axis fluctuations in a TR (video tape recorder), etc., a frame synchronizer that synchronously combines different video signals, and the like are known.

The aforementioned contour correction technology does not take into consideration the combination with other technologies such as the TBC mentioned above, and configuring each independent system would increase the circuit scale, making it impossible to take advantage of the commonality of clock timing control. There wasn't.

An object of the present invention is to simultaneously perform contour correction and time axis conversion such as TBC.

[Means to solve the problem]

In order to achieve the above object, the present invention includes an A/D converter that digitizes a video signal, a memory that stores this digital signal, a D/A converter that converts the memory output into an analog signal, and an A/D converter that digitizes the video signal. Time axis conversion is performed by means for generating a clock for writing to a memory, and means for generating a clock synchronized with an external video signal to which free-run oscillation or an input video signal is to be synchronously combined. Furthermore, means is provided for detecting contour information of the input video signal and locally changing the period of either the writing or reading clock based on this information.

[Effect]

Depending on the contour information, the period of the write clock to the memory is made longer in the contour portion than in the non-contour portion.

By reading out the signals written in the memory in this way using a constant cycle clock, the data sense of the @ edge portion is time-compressed compared to the time of writing, and a contour correction effect that sharpens the waveform of the contour portion is obtained.

Furthermore, since data is written to and read from the memory using a clock that is synchronized with the time variation of the input signal and is read using a clock that does not have time variation, time axis correction can be performed at the same time.

In addition, the same effect as the above-mentioned means can be obtained by writing with a clock having a constant cycle and making the clock cycle shorter in the contour part than in the non-contour part during reading.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the invention.

In the figure, 1 is an A/D converter, 2 is a memory, and 3 is a D/A converter. The memory 2 is of an asynchronous type in which writing and reading can be performed using different clocks (write clock WCK, read clock RCK). 4 is a circuit that generates a write control pulse for the memory 2, and 5 is a circuit that also generates a read control pulse. The above control pulses differ depending on the memory system, but in this embodiment, the FIFO (first-in-first-out) system is used, and a reset signal, WRES (write reset signal), and RRES (read reset signal) are used to determine write and read timing. shall be controlled. Of course, the following effects can also be obtained using the addressing method; in this case, the write control pulse generation circuit 4. The address may be generated in the read control pulse generation circuit 5. 6 is a crystal oscillator that generates a read clock. Of course, the oscillator may be anything other than a crystal oscillator.

7 is a voltage controlled oscillator (VCO), and 8 is a phase F+1 comparator, which inputs a read clock and a CO output clock to the phase comparator 8. This constitutes a PLL (phase locked loop) and synchronizes the write clock and read tally.

9 is a differentiating circuit, which extracts the change in the input signal; 1
0 is an absolute value circuit that takes the absolute value of the amount of change in the signal. 1
1 is a comparison circuit, and 12 is an adder.

13 is a capacitor, and 14 is a reference potential of the comparator.

The voltage that controls the oscillation frequency of the VCO is the phase comparator output voltage (DC) and the voltage (DC) depending on the amount of change in the input signal.
AC). As a result, the frequency of the write clock is on average the same as the read clock, but clocks with locally different periods are obtained.

The details of the operation of the present invention will be described below. Figure 2 shows
FIG. 3 is a timing diagram showing the operation of the present invention.

(α) is an input signal, and (b) is a signal obtained by differentiating the input signal and taking an absolute value, and is a signal obtained by extracting the contour of the signal. However, only when the comparator 12 has a difference greater than a predetermined level is determined to be a contour portion. By adding a control voltage superimposed with an AC voltage reflecting this contour component to vCo7,
The period of the generated clock changes at the contour. As the control voltage increases, the clock period becomes longer, so if a CO configuration is used, the clock will be as shown in (Q) (in the figure, only the rising (or falling) edge of the clock is shown) , Therefore, the point indicated by the black circle of the input signal (α) is sampled and written to the memory 2. Reading is performed using a clock with a constant cycle as shown in (d). As a result, the read signal has a waveform as shown in (e). That is, the signal of one contour part has the effect of being compressed by one hour, and the change becomes steep. by this,
Obtains a contour correction effect that sharpens contours that were blurred before processing. 1. In this embodiment, the contour is detected from the input signal itself, but when component signals, such as a luminance signal and a color difference signal, or R, G, and B signals are targeted, it is necessary to detect mutually correlated signals. The outline may be detected using Further, the contour signal from itself and the contour signal of another signal may be used, both may be mixed, or either one may be selected.

Next, a second embodiment of the present invention will be described.

FIG. 10 is a block diagram of this embodiment. 16 is a synchronization separation circuit that separates the horizontal synchronization signal HD from the video signal. 17 is a phase comparison circuit, and 18 is a frequency dividing circuit. Synchronous separation circuit 162, phase comparison circuit 17, frequency division circuit 18. vCo
7, the frequency division of the 0 frequency divider circuit that configures the PLL circuit and generates the clock locked to the HD of the input signal is 1/n.
(n: natural number), the frequency of vCo9 is n times the frequency of HD.

With the PLL circuit described above, writing to the memory 2 is performed using a clock that follows the jitter of the input signal. On the other hand, a clock generated by a crystal oscillator using a crystal resonator 15 is used for reading.

Further, as in the first embodiment, the vCo control voltage superimposes an AC component according to the contour information and changes the clock cycle of the contour portion.

If the storage capacity of the memory is one frame (field), this configuration can perform contour correction and frame (field) synchronization at the same time. Then, a signal with jitter removed can be obtained. Further, if a PLL circuit is provided in the read control pulse generation circuit as well as in the write side, an external cycle is also possible.

In addition, by locking the phase of the VTR's servo control to the readout control signal, the memory capacity can be reduced and the TB
It can also be used as a time base collector.

Next, a third embodiment of the present invention will be described.

FIG. 3 is a block diagram of the second embodiment. 1°2.3
．． 5 is the same as described above. 21 is a delay circuit, 2
2 is an edge detection circuit for detecting the rising and falling edges of a signal, and 23 is a write control pulse generation circuit for the memory 2, which includes the PLL circuit shown in the first embodiment. 24 is vCo, 2, which controls the oscillation frequency with the output voltage of the adder 13;
5 is a DC power supply.

FIG. 4 shows the delay circuit 21. This is a configuration example of the edge detection circuit 22. 51 is a delay element such as a D flip-flop (however, the number of bits is the same as the resolution of the A/D converter), and 2n pieces (n: a natural number) are connected in cascade. 52 is a subtracter, 53 is an absolute value conversion circuit, 54 is a comparator, and 55 is a reference level generation circuit for the comparator.

FIG. 5 shows a timing diagram of the operation of the 0 circuit, where 56 is an AND circuit. Each waveform of A-H is shown in FIG.
This is a waveform at each point of H. D is the absolute value of the difference between A and B, and E is obtained by comparing it with the 5!51794 level shown by the dotted line in the comparator 54. Similarly, Gtil- is obtained from the difference between B and C. If you AND E and G, you get H, but
This corresponds to the rising and falling periods of B. I-I (1 bit) is written into the memory at the same time as the data of B.

Next, the operation of this embodiment will be explained. FIG. 6 is an operation timing diagram of this embodiment. (cL) is an input signal, (b) is a write clock, (C) is edge information written to memory 2, (d) is edge information read from memory, (e) is a read clock, (f) is is the output signal.

Writing is performed using a fixed cycle clock.

The value indicated by the black circle is written to memory. On the other hand, reading is performed by superimposing an AC voltage proportional to the edge information (waveform C) on the DC voltage vO on the control voltage of the VCO 24.
The period of the read clock varies locally. Here, it is assumed that as the control voltage increases, the period becomes shorter. By changing the read clock in this way, the output signal can have a steep edge slope as shown in (f).

In this embodiment, since edge detection is also performed by digital signal processing, it has the advantage that it can be easily integrated into an IC and the circuit scale can be reduced.

In this embodiment, a frame synchronizer configuration is shown, but it goes without saying that it may be configured to synchronize the write clock and the read clock as in the first embodiment.

A fourth embodiment of the present invention will be described. FIG. 7 is a block diagram of this embodiment. In the memory 2 used in this embodiment, write and read addresses are designated from outside. 71 is a circuit that generates a clock address for reading R, 72 is a circuit that generates a clock address for reading, 73 is a circuit that adds 1 to the address value, 74 is a circuit that also subtracts 1, and 75 is a multiplexer. .

Delay circuit 21. An example of the edge detection circuit 22 is shown in FIG. 61 and 62 are circuits that detect pulse edges;
Others are the same as those already explained. FIG. 8 is an operation timing chart of this embodiment, and each waveform of A- is shown in FIG.
This is a waveform at each point at A- in FIG.

The operation of this embodiment will be explained below. The input signal digitized by the A/D converter is delayed by one clock at a time in the D flip-flop, and the waveform at each point from A to D becomes as shown in FIG. By taking the absolute value of the difference between points A and B, we obtain the waveform E, and similarly, from points B and 0, we obtain the waveform F.

This is compared with a preset reference level, and a portion exceeding the reference level is determined to be a contour portion, and pulses shown at G and H are generated. Furthermore, the pulse edge detection circuit 61 detects the falling edge of the G pulse and generates the pulse shown in (2).

Further, a pulse edge detection circuit 62 detects the rising edge of the H pulse and generates a pulse shown at J. Edge information H and I are written to the memory 2 together with the video signal C. When reading from the memory 2, if the edge information H is at a high level, the multiplexer 75 sets the address by subtracting 1, and the edge information L If the address is at a high level, 1 is added to the address, and if both H and I are at a low level, no addition or subtraction is performed. In this way, by changing the address at the contour, the signal read from the memory becomes steeper at the contour, as shown in (■) in FIG. 9, and a contour correction effect is obtained.

In this embodiment as well, frame synchronization is of course possible as in the previously described embodiment.

Further, there is no problem even if the clocks for writing and reading are the same.

〔Effect of the invention〕

According to the present invention, it is possible to essentially enhance the high-frequency information of the contour portion, and there is an effect of improving the blurring and blurring of the contour portion of the image without causing side effects such as pre-shooting.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is an operation timing diagram of the first embodiment. 3 and 4 are block diagrams showing a second embodiment of the present invention, and FIGS. 5 and 6 are operation timing diagrams of the second embodiment. 7 and 8 are block diagrams of the third embodiment of the present invention, and FIG. 9 is an operation timing diagram of the third embodiment,
FIG. 10 is a block diagram of a fourth embodiment of the present invention. 1...A/D converter. 2...Memory. 3...D/A converter. 9...VCO. 22... Edge detection circuit. Story 11!1 Trap 2I! ] (shi) 60th (ko) 5th group 4th closure 5th country H q mouth 9th torture

Claims (1)

[Claims] 1. An A/D converter that converts an input signal into a digital signal, a memory that stores the digital signal, a D/A converter that converts the digital signal read from the memory into an analog signal, and an input. Means for generating a memory write clock synchronized with a video signal; means for generating a read clock synchronized with an external video signal for free-run oscillation or synchronous coupling of the input video signal; and contour information of the input video signal. 1. A contour correction circuit comprising means for detecting the information and locally changing the period of either the writing or reading clock based on this information. 2. The contour correction circuit according to claim 1, further comprising at least one of a period combination circuit for an input video signal and a memory write clock, or an external period signal and a read clock. 3. An A/D converter, a memory, a D/A converter, a circuit for generating write and read addresses for the memory, means for detecting the contour of an input signal, and a means for detecting the read address according to the contour information. A contour correction circuit characterized by being provided with variable means.