JPH02307123A - Computer - Google Patents

Abstract

PURPOSE:To eliminate the useless time required for the access to an external memory and at the same time to decrease the useless external access frequency by selecting a simultaneous state with the access to an instruction cache or a mishit state of this cache when an access is given to the external memory. CONSTITUTION:When the hit is estimated for the access of this time, an access is first given to an instruction cache memory 1 only. Then an external bus using request signal is outputted to a bus arbitrating circuit 7 only when the access has a mishit to the memory 1. Then an address is outputted to an external address bus 3 and an access is given to an external memory 2. When the mishit of the access is estimated, an access is given to the memory 1 and at the same time an address is outputted to the bus 3 to have an access to the memory 2. Thus it is possible to reduce the useless time required for reading the data on the memory 2 and at the same time to decrease the useless application frequency of the bus 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a computer, and particularly to a computer having an instruction cache memory.

[Conventional technology]

In conventional computers with instruction cache memory,
After obtaining a valid address containing the instruction to be read, the instruction was read in one of the following ways:

That is, in the first method, the instruction cache memory is first accessed, and if there is a hit, the data is read, and if there is no hit, the external memory is read via the external bus. FIG. 3 is a timing chart when this operation misses, and FIG. 5 is a block diagram showing the configuration of a conventional instruction cache memory.

When CPU valid instruction read address 9 is output,
The instruction cache memory 1 outputs a hit signal 10 when the memory access is hit. If this is a miss, control circuit 6 outputs external bus request signal 11 to access external memory. Then, when the bus arbitration circuit 7 outputs the external bus use permission signal 12, the control circuit 6 outputs the buffer drive signal 13, outputs the address to the external address bus 3, and the contents of the external memory 2 are transferred to the external data bus 14. Read out.

At this time, the signal on the external data bus 14 is outputted to the CPU via the wiring 19 in response to a signal for multiplexer switching supplied from the control circuit 6 via the wiring 15.

The second method is to access external memory via the external bus at the same time as accessing the instruction cache memory, and when the cache memory has a hit, the data in the cache memory is read, and when there is a miss, the data in the external memory is read. FIG. 4 is a timing chart of this operation. This will be explained below in conjunction with FIG.

When a valid CPU instruction read address is output to the wiring 9, the control circuit 6 outputs the external bus request signal 11, regardless of whether it hits the instruction cache memory 1 (that is, regardless of the state of the hit signal 10). Output. Then, the bus arbitration circuit 7 issues the external bus use permission signal 1.
2, the control circuit 6 outputs the buffer drive signal 13, outputs the address to the external address bus 3, and the contents of the external memory 2 are read out as the external data bus 14. In this case as well, the signal on the external data bus 14 is output to the CPU via the wiring 19 in response to a signal for multiplexer switching supplied from the control circuit 6 via the wiring 15.

[Problem to be solved by the invention]

In the above-mentioned computer with an instruction cache, the first method has the advantage of not using the external bus if the cache is hit, but if there is a miss, the instruction cache is accessed and then the external memory is accessed. The disadvantage is that it takes time to access the data. In addition, in the second method, since the external memory is accessed from the beginning, it has the advantage that no extra time is required to access the external memory even if there is a mishit, but it always uses the external bus. It has its drawbacks. Since the external bus is used for purposes other than reading instructions, unnecessary use of external access leads to a decrease in performance.

Compared to the above-mentioned conventional computer having an instruction cache, the computer of the present invention has the difference that both the first method and the second method can be used, and they can be used depending on the situation. .

[Means to solve the problem]

The computer of the present invention has an external memory that can be accessed via an external bus and an instruction cache memory that can be accessed without using an external bus. The first instruction reading function accesses the external memory via the external bus only when the instruction cache memory and the external memory are accessed at the same time, and when the instruction cache memory is hit, the cache memory value is a second instruction reading function that uses the value in external memory when the instruction cache memory has not been hit; a prediction function that predicts a hit/miss in the instruction cache memory from the history of past hits in the instruction cache memory; It is configured to have a third instruction reading function that reads an instruction using the first instruction reading function, and reads the instruction using the second instruction reading function when a miss is predicted.

[Embodiment] FIG. 1 is a diagram illustrating the configuration of an instruction cache memory according to a first embodiment of the present invention. In this embodiment, the portion related to the write operation to the cache memory is omitted to simplify the explanation.

The instruction cache memory 1 inputs an address signal 9 for reading an instruction, and when a hit occurs, it outputs data to a wiring 16 and outputs a hit signal 10. Tri-state buffer 5 outputs an instruction read address signal to external address bus 3 when buffer drive signal 13 is active. The external buses are external address bus 3 and external data bus 1.
It consists of 4. The external bus is a tri-state buffer 5
Since the external bus may be connected to other devices, it is necessary to secure an external bus before use, and the bus arbitration circuit 7 does this.

When the control circuit 6 activates the external bus request signal 11 to request the use of an external bus, the bus arbitration circuit 7 determines whether to use the external bus based on requests from others, the usage status, and a predetermined priority. In order to make it easier to understand FIG. 6 in which the permission signal 12 is output, the configuration for the bus arbitration circuit 7 to know requests from others and the usage status is not shown in FIG.

The external memory 2 then writes or reads data to or from the address designated by the external address bus 3. The read data is input to the multiplexer 8 via the external data bus 14. The multiplexer 8 outputs either the wiring 16 or the external data bus 14 to the CPU via the wiring 19 in response to a signal for multiplexer switching outputted from the control circuit 6 via the wiring 15. The cache hit prediction circuit 20 predicts whether or not the instruction cache will be hit based on the history of the instruction read address and the hit signal, and outputs this result to the control circuit 6.

In this embodiment, writing to the instruction cache memory is as follows:
Pre-reading (where the cache memory predicts the CPU operation and reads in advance data for which no read request has been issued) is not performed using only the mishit data.

In such a situation, the instruction cache is often hit because the program is stuck in a loop.

Here, the following algorithm is used for cache hit prediction. If the instruction cache hits during a certain instruction read access, it is predicted that the next instruction read access will hit the cache, and if there is a miss, it is predicted that the next one will also be a miss.

At this time, the operation of this embodiment is as follows. If it is predicted that the current access will be a hit based on the result of the previous access, first, only the instruction cache memory 1 is accessed, and only when there is a miss, an external bus use request signal is output to the bus arbitration circuit 7. Then, the address is output to the external address bus 3 and the external memory is accessed. That is, the operation shown in FIG. 3 is performed. When a miss is predicted, the instruction cache memory 1
At the same time, an external bus use request signal is output to the bus arbitration circuit 7, an address is output to the external address bus 3, and the external memory is accessed. If instruction cache memory 1 hits, the data in the cache memory is transferred to the CP
At the same time, access to the external memory is interrupted.

If the cache memory misses, the data in the external memory is sent to the CPU, ie, the operation shown in FIG. 4 is performed.

FIG. 2 is a diagram illustrating the configuration of an instruction cache memory according to a second embodiment of the present invention.

Only the differences from the first embodiment shown in FIG. 1 will be explained.

The contents include that the wiring 18 connecting the instruction cache memory and the multiplexer and the external data bus 17 have a width of 4 words, and writing to the cache memory in the event of a miss is performed in units of 4 words. Here, the width of l word is the width of the wiring 19 that sends data to the CPU. In this configuration, when a miss occurs and a write is performed to the cache memory, the read to the same 4-word block (hereinafter referred to as a block) immediately after it will be a hit, so the algorithm of the cache hit prediction circuit 20 is as follows. do. If the same block as the previous access is accessed, a hit is predicted. When accessing a different block, if the previous block hit the cache, it is predicted to be a hit, and if it was a miss, it is predicted to be a miss. The other operations are the same as in the first embodiment.

〔Effect of the invention〕

As explained above, the present invention makes it possible to select whether to access the external memory at the same time as the instruction cache access or when the instruction cache memory misses, and when the probability of a hit is high, the instruction cache memory After an access, the external memory is accessed only when there is a miss, and when there is a high probability of a miss, the external memory is accessed at the same time as the instruction cache memory, so even if the instruction cache memory misses, the external memory is This has the advantage that it is possible to configure a computer that requires less extra time to read data and uses less unnecessary external buses.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the second embodiment, and FIG.
The figure is a timing chart of the operation of accessing the external memory after a miss in the instruction cache. Figure 4 is the timing chart of the operation of the instruction cache memory accessing the external memory at the same time as the cache memory access. Figure 5 is the conventional timing chart. FIG. 2 is a block diagram showing the configuration of an instruction cache memory according to the technique of FIG.

Claims (1)

[Claims] In a computer having an external memory that can be accessed via an external bus and an instruction cache memory that can be accessed without using the external bus, the instruction cache memory is accessed and a miss occurs. The first instruction reading function accesses the external memory via the external bus only when the instruction cache memory is hit, and the instruction cache memory and external memory are accessed simultaneously, and when the instruction cache memory is hit, the cache memory value is A second instruction reading function that uses the value in external memory when there is no hit, a prediction function that predicts a hit/miss in the instruction cache memory from the history of past hits in the instruction cache memory, and a hit and prediction function. When a mishit is predicted, the first instruction reading function is used to read the instruction, and when a miss is predicted, the second instruction reading function is used to read the instruction. Featured calculator.