JPH06149677A - Cache memory system - Google Patents

Abstract

PURPOSE:To allow a bus master also on a system bus to access a cache memory in addition to a CPU. CONSTITUTION:A dual port cache memory 2 can be accessed from both of a CPU 1 and a CPU 15 to be a bus master on the system bus 11. When data accessed from the CPUs 1, 15 exist in the memory 2, a cache controller 3 allows the CPUs 1, 15 to access the memory 2, and when the data are not stored in the memory 2, allows the CPUs 1, 15 to access a main memory 16. Since also the bus master on the system bus 11 can use the high speed cache memory 2, the processing speed of the system can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory system, and more particularly to a cache which can be accessed not only by a CPU having a cache memory but also by another CPU connected to the system bus or a bus master such as a DMA controller. Regarding memory system.

[0002]

2. Description of the Related Art In a conventional cache memory system, only a CPU having a cache memory can access the cache memory.

[0003]

As described above, since the conventional cache memory system cannot access the cache memory except the CPU having the cache memory, the DMA controller on the system bus frequently uses the main memory. There is a problem that the processing speed of the entire computer system is lowered by the main memory having a slow response speed when accessing or when the other CPU on the system bus accesses the main memory.

An object of the present invention is to provide a cache memory system in which a bus master on the system bus can access the cache memory.

[0005]

In order to achieve the above object, the present invention provides a CPU, a system bus to which a main memory and a bus master are connected, and a dual port cache memory accessible from both the CPU and the bus master. If the data accessed by the CPU exists in the dual port cache memory, the CP
U accesses the dual port cache memory, causes the CPU to access the main memory if not present, and causes the bus master to access the data accessed by the bus master on the system bus if the data is present on the dual port cache memory. A cache controller is provided for accessing the dual port cache memory and for allowing the bus master to access the main memory if it does not exist.

[0006]

When the data accessed by the CPU and the data accessed by the bus master on the system bus exist in the dual port cache memory, the cache controller accesses the dual port cache memory, and otherwise accesses the main memory.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a CPU 1, a dual port memory 2, a cache controller 3, a CPU control bus 4 and a C are shown.
PU address bus 5, CPU data bus 6, CPU
Address transceiver 7 and CPU data buffer 8
A system address transceiver 9, a system data buffer 10, a system bus 11 including a system control bus 12, a system address bus 13 and a system data bus 14, a CPU 15, a main memory 16, and buses 17 and 18. It consists of

The dual port cache memory 2 is a CP
It is a cache memory accessible from both U1 and the system bus 11.

The address terminal of the dual port cache memory 2 is connected to the CPU address transceiver 7 and the system address transceiver 9 via the bus 17, and the data terminal thereof is connected to the CPU data buffer 8 via the bus 18.
It is connected to the system data buffer 10. The system address transceiver 9 is the system address bus 13
In addition, the system data buffer 10 is connected to the system data bus 14. The CPU address transceiver 7 is connected to the CPU 1 via the CPU address bus 5, and the CPU data buffer 8 is connected to the CPU 1 via the CPU data bus 6.

The cache controller 3 controls reading / writing of data from / to the dual port cache memory 2, and includes a CPU bus state machine 31, a system bus state machine 32, and a command control circuit 3.
3, command encoder 34, and directory 35
Address control circuit 36 and address bus control circuit 3
7, a data bus control circuit 38, and a cache memory control circuit 39.

Next, the operation of this embodiment will be described.

First, a CP in which the CPU 1 performs a read operation.
The operation of the U read cycle will be described.

When reading, the CPU 1 outputs a read command to the CPU control bus 4 and a read address to the CPU address bus 5.

The read command output to the CPU control bus 4 is added to the CPU bus state machine 31 in the cache controller 3, and the read address output to the CPU address bus 5 is the address control circuit 36.
Added to.

The CPU bus state machine 31 decodes the added read command and sends the decoded result to the command control circuit 33, and the address control circuit 36 compares the added read address with the contents of the directory 35, A hit or a miss hit is determined and the determination result is sent to the command control circuit 33.

In the command control circuit 33, the decoding result from the CPU bus state machine 31 indicates a read command,
If the determination result of the address control circuit 36 indicates a hit, the address bus control circuit 37 and the data bus control circuit 38 are controlled to control the CPU address transceiver 7,
The CPU data buffer 8 is opened and the cache memory control circuit 39 is controlled to output a read signal to the dual port cache memory 2.

As a result, the read address is supplied to the address terminal of the dual port cache memory 2 via the CPU address transceiver 7, and the data read from the dual port cache memory 2 by this read address is stored in the CPU data buffer 8 and the CPU. It is supplied to the CPU 1 via the data bus 6.

If the decoding result of the CPU bus state machine 31 indicates a read command and the judgment result of the address control circuit 36 indicates a mishit, the command control circuit 33 controls the address bus control circuit 37. The CPU address transceiver 7 and the system address transceiver 9 are opened, and the command encoder 34 is controlled to output a read command to the system control bus 12, and the address control circuit 36 is further provided.
Is instructed to update the directory 35.

As a result, the read address is supplied to the main memory 16 via the CPU address transceiver 7, the bus 17, the system address transceiver 9, and the system address bus 13, and the data corresponding to the address is supplied from the main memory 16 to the system data bus 14. Is output to. Further, the address control circuit 36 causes the old address in the directory 35 to be one CPU address bus 15
It is updated to the read address output to.

Next, the address control circuit 36 controls the data bus control circuit 38 to open the CPU data buffer 8 and system data buffer 10, and controls the cache memory control circuit 39 to control the dual port cache memory 2. To output a write signal.

As a result, the data output from the main memory 16 to the system data bus 14 is read into the CPU 1 via the system data buffer 10, the bus 18 and the CPU data buffer 8 and written into the data port cache memory 2. One old data is updated.

Next, the CP in which the CPU 1 performs the write operation.
The operation of the U write cycle will be described.

At the time of writing, the CPU 1 outputs a write command to the CPU control bus 4, a write address to the CPU address bus 5, and a write data to the CPU data bus 6.

The write command output to the CPU control bus 4 is decoded by the CPU bus state machine 31, and the decoded result is added to the command control circuit 33. Further, the write address output to the CPU address bus 5 is added to the address control circuit 36 to make a hit / miss hit determination.

In the command control circuit 33, when the decoding result indicating the write command is added from the CPU bus state machine 31 and the determination result indicating the hit is added from the address control circuit 36, the address bus control circuit 37 and the data bus control circuit 38. To open the CPU address transceiver 7, the CPU data buffer 8, the system address transceiver 9, and the system data buffer 10 and to control the cache memory control circuit 39 to send a write signal to the dual port cache memory 2. Then, the command encoder 34 is controlled to output a write command to the system control bus 12.

As a result, the data output from the CPU 1 to the CPU data bus 6 is written in the dual port cache memory 2 and the command encoder 34 is also used.
Write command output from the system control bus 12 to the CPU address transceiver 7, bus 1
7, the write address output to the system address bus 13 via the system address transceiver 9 and the data output to the system data bus 14 via the CPU data buffer 8, bus 18, and system data buffer 10 to the main memory 16 Written.

When the judgment result applied from the address control circuit 36 indicates a mishit, the command control circuit 33 controls the address bus control circuit 37 and the data bus control circuit 38 to control the CPU address transceiver 7. , The CPU data buffer 8, the system address transceiver 9, and the system data buffer 10 are opened, and the command encoder 34 is controlled to output a write command to the system control bus 12.

As a result, the data output to the system data buffer 14 via the CPU data buffer 8, the bus 18 and the system data buffer 10 is converted into the write command output from the command encoder 34 to the system control bus 12 and the CPU address. It is written in the main memory 16 by the write address output to the system address bus 13 via the transceiver 7, bus 17, and system address transceiver 9.

Next, the operation of the system read cycle in which the bus master on the system bus 11 performs a read operation will be described.
A case where the CPU 15 performs a read operation will be described as an example.

When reading, the CPU 15 on the system bus 11 outputs a read command to the system control bus 12 and a read address to the system address bus 13.

The system bus state machine 32 decodes the read command output to the system control bus 12 and adds the decoded result to the command encoder 34, and the address control circuit 36 outputs the read address and directory 35 output to the system address bus 13. The hit / miss hit is determined based on the contents of the above, and the determination result is output to the command control circuit 33.

If the decoding result from the system bus state machine 32 indicates a read command, and the determination result of the address control circuit 36 indicates a hit, the command control circuit 33 outputs the address bus control circuit 37,
The data bus control circuit 38 is controlled to open the system address transceiver 9 and the system data buffer 10, and the cache memory control circuit 39 is controlled to output a read signal to the dual port cache memory 2, and a command is issued. The encoder 34 is controlled to output a data output prohibition command for the main memory 16 to the system control bus 12.

As a result, data is output from the dual pointer cache memory 2 to the system data bus 14 via the system data buffer 10, and this data is taken into the CPU 15.

Here, the CPU that outputs the data output prohibition command from the command encoder 34 is the CPU.
This is to prevent data from being output from the main memory 16 by the read command and read address output by 15.

If the decoding result from the system bus state machine 32 indicates a read command and the judgment result of the address control circuit 36 indicates a mishit, the command control circuit 33 determines the address bus control circuit 37,
The data bus control circuit 38 is controlled to open the system address transceiver 9 and the system data buffer 10, and the cache memory control circuit 39 is controlled to output a write command to the dual port cache memory 2 to further write the address. The control circuit 36 is instructed to update the directory 35.

As a result, the data output from the main memory 16 to the system data bus 14 is written into the dual port cache memory 2 via the system data buffer 10, and at the same time, one old address in the directory 35 is stored in the system address bus 13. It is updated by the read address output to. Further, the data output from the main memory 16 to the system data bus 14 is taken in by the CPU 15.

Next, the operation of the system write cycle in which the bus master on the system bus 11 performs the write operation is
A case where the PU 15 performs a write operation will be described as an example.

At the time of writing, the CPU 15 outputs a write command to the system control bus 12, a write address to the system address bus 13, and a write data to the system data bus 14.

The system bus state machine 32 decodes the write command output to the system control bus 12 and adds the decoded result to the command control circuit 33, and the address control circuit 36 outputs the write address and the directory output to the system address bus 13. Based on the contents of 35, a hit or a miss hit is determined and the determination result is added to the command control circuit 33.

In the command control circuit 33, when the decoding result of the system bus state machine 32 indicates a write command and the judgment result of the address control circuit 36 indicates a hit, the address bus control circuit 37 and the data bus control circuit 38. To control the system address transceiver 9,
The system data buffer 10 is opened and the cache memory control circuit 39 is controlled to output a write signal to the dual port memory 2.

As a result, the data output from the CPU 15 to the system data bus 14 is written in the dual port cache memory 2 via the system data buffer 10. The data output from the CPU 15 to the system data bus 14 is also written in the main memory 16.

Further, the command control circuit 33 does not perform any processing when the decoding result of the system bus state machine 32 indicates a write command and the determination result of the address control circuit 36 indicates a mishit. Therefore,
In this case, CPU 15 to system control bus 1
2 by the write command output to the CPU 2 and the write address output to the system address bus 13.
The write data output from 5 to the system data bus 14 is written into the main memory 16 only.

[0044]

As described above, according to the present invention, the dual port cache memory accessible by the CPU and the bus master on the system bus is provided, and the bus master on the system bus also uses the high speed cache memory. Therefore, the processing speed of the system can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Explanation of symbols]

 1 ... CPU 2 ... Dual port cache memory 3 ... Cache controller 31 ... CPU bus state machine 32 ... System bus state machine 33 ... Command control circuit 34 ... Command encoder 35 ... Directory 36 ... Address control circuit 37 ... Address bus control circuit 38 ... Data bus control circuit 39 ... Cache memory control circuit 4 ... CPU control bus 5 ... CPU address bus 6 ... CPU data bus 7 ... CPU address transceiver 8 ... CPU data buffer 9 ... System address transceiver 10 ... System data buffer 11 ... System bus 12 System control bus 13 System address bus 14 System data bus 15 CPU 16 Main memory 17, 18 Bus

Claims (3)

[Claims] 1. A system bus to which a CPU, a main memory and a bus master are connected, a dual port cache memory accessible from both the CPU and the bus master, and data accessed by the CPU is stored in the dual port cache memory. If present, the CPU is made to access the dual port cache memory, and if not present, the CPU is made to access the main memory, and data accessed by the bus master on the system bus is present in the dual port cache memory. A cache controller for causing the bus master to access the dual-port cache memory if the bus master does not exist, and for allowing the bus master to access the main memory if the bus master does not exist. system. 2. When the data read by the bus master exists in the dual port cache memory, the cache controller instructs the main memory on the system bus to prohibit data output and outputs from the bus master. 2. The cache memory system according to claim 1, wherein the read address that has been read is supplied to the dual port cache memory, and the read data read from the dual port cache memory is output to the system bus. 3. The cache memory system according to claim 1, wherein the bus master includes a CPU and a DMA controller.