JPH02308497A - Semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to an output buffer circuit.

[Prior art 1] Figure 3 is a diagram showing an example of a conventional output buffer circuit, and Figures 4 (a), (b), (c), and (d) show the characteristics of the prior art shown in Figure 3. FIG.

In the prior art shown in FIG. 3, the output 5AOUT of the sense amplifier circuit 100 is connected to the gates of the NAND gate 11 and the negative AND gate 12, and the output OE of the output control circuit 200 is directly connected to the gate of the NAND gate 11. and is connected to the gate of the negative AND gate 12 via an imperme IO. Furthermore, Nantes Gate 11
The output PG of the negative AND gate 12 is connected to the gate of the P-channel MOS transistor Pl of the output driver, and the output NG of the negative AND gate 12 is connected to the gate of the N-channel MOS transistor N1 of the output driver.

Here, depending on the data from the memory cell, 5AOUT changes from a low level (hereinafter referred to as "L") to a high level (hereinafter referred to as "L").
The case of changing to H'' will be described in detail below with reference to FIGS. 3 and 4 (a) and (b).

When the semiconductor memory device is in a read state, the output OE of the output control circuit is set to °H''.

Therefore, when 5AOUT changes from °L to °H,
The output PG of the NAND gate 11 and the output NG of the negative AND gate 12 change from "H" to "L" almost simultaneously. At this time, the potential of PG of the P-channel MOS transistor P1 of the output driver is ■. . -■tfiD
(However, the N-channel MOS transistor N1 turns on at the time t when it reaches Vo (+ is the power supply voltage, and vthp is the threshold voltage of the P-channel MOS transistor P1), and the NG potential is Vt, , (where V tn is the threshold voltage of N-channel MOS transistor N1)
It turns off at time t, when it reaches t. Therefore, the external output OUT changes from "L" to "H" with a waveform as shown in FIG. 4(a).

Next, data from the memory cell causes 5AOUT to
The case of changing from 'H' to L'° will be described in detail below with reference to FIGS. 3 and 4(c) and (d).

When 5AOUT changes from °°H" to L°°, the output PG of the Nant gate 11 and the output NG of the negative AND gate 12 change from L" to °°H" almost simultaneously. At this time, the output The N-channel MOS transistor N1 of the driver has a time t when the potential of NG reaches Vth.
The P-channel type MOS transistor P1 is turned on at 2, and the potential of PG is Vo. −V t,, time t to reach p,
to turn off. Therefore, the external output OUT changes from ``H'' to ``L'' with a waveform as shown in FIG. 4(c).

[Problem to be solved by the invention]

However, in the conventional technology as described above, there occurs a period in which both the P-channel type MOS transistor P1 and the N-channel type MOS transistor N1 are on in the output driver. t as shown in d)
, ~t2, Voo P I N 1-Vs
A through current flows between t (where Vst is a ground potential). This current becomes larger as the number of output bits increases, and it not only becomes a hindrance in realizing low power consumption semiconductor storage devices (the peak current affects internal circuits, It may also become a factor causing it to malfunction.

The present invention solves the above problems, and its purpose is to provide a semiconductor memory device with low power consumption and stable operation that completely eliminates the through current in the output driver. .

[Means for Solving the Problems] A semiconductor memory device of the present invention includes an output buffer circuit that outputs data of a selected memory cell sensed by a sense amplifier to the outside, and an output control circuit that controls the output buffer circuit. In a semiconductor memory device, a first logic circuit receives a signal output from a sense amplifier circuit including the sense amplifier and a signal output from the output control circuit; and a first logic circuit receives an output signal from the sense amplifier circuit. a second logic circuit that receives a signal output from the sense amplifier circuit and a signal output from the output control circuit;
a third logic circuit which receives as input a signal obtained by delaying and inverting the output from the logic circuit; a signal output from the sense amplifier circuit; and a signal output from the sense amplifier circuit;
a fourth logic circuit that receives as input a signal obtained by delaying and inverting the output from the logic circuit; a signal output from the third logic circuit; and a signal output from the fourth logic circuit. It is characterized by being equipped with an output driver that outputs data to the outside.

[Function 1] According to the above configuration of the present invention, even if the output 5AOUT of the sense amplifier circuit changes, the time during which the P-channel type MOS transistor P1 in the output driver is turned off and the time when the N-channel type MOSFET transistor N1 is turned on are changed. It is possible to set an arbitrary time difference between the time when the N-channel type MOS transistor N1 turns off and the time when the P-channel type MOS transistor N1 turns on.

Embodiment 1 FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2(a) and 2(b) are characteristic diagrams of the circuit of FIG. 1.

In the circuit shown in FIG. 1, the output of the sense amplifier circuit 100 is 5A.
OUT is connected to the gate of the Nant gate 51, the gate of the negative AND gate 52, the gate of the Nant gate 53, and the gate of the negative AND gate 54,
The output OE of the output control circuit 200 is directly connected to the gate of the Nantes gate 51 and is connected to the negative AND gate 52.
The output of the Nant gate 51 is connected to the delay circuit 300, and the output of the negative AND gate 52 is connected to the delay circuit 301.
connected to. Further, the output of the delay circuit 300 is connected to the gate of the Nantes gate 53, and the output of the delay circuit 300 is connected to the gate of the Nantes gate 53.
The output of the negative AND gate 54 is connected to the gate of the negative AND gate 54, the output PG of the Nant gate 53 is connected to the gate of the P-channel type MO5I transistor P1 of the output driver, and the output NG of the negative AND gate 54 is connected to the N-channel type of the output driver. MOSl--connected to the gates of the transistors N1, respectively. The above circuit operation is shown in Figure 2 (a
) and (b) will be described in detail below.

When the semiconductor memory device is in a read state, the output OE of the output control circuit is set to °H.

Therefore, when 5AOUT changes from °゛L°゛ to ゛°H, the output NG of the negative AND gate 54 immediately becomes '
The N-channel MOS transistor N1 of the output driver changes from NG to ■th,
, (where V thn is the threshold voltage of the N-channel MOS transistor N1) and is turned off at time t2.

Further, the output PG of the Nant gate 53 is output from the delay circuit 300.
Immediately after the output changes from °゛L゛ to “H”, “
The potential of P-channel MOS transistor Pl of the output driver changes from °H° to °L”, and the potential of PG changes to V,,
, -Vthp (where, V oo is the electric tA voltage, and V t
119 turns on at time 1+ when reaching the threshold voltage of P-channel type MOS transistor Pl.

At this time, due to the effect of the delay circuit 300, △t1
Therefore, there is no period in which both N1 and Pl are on, so Vl)
The through current in the path of ,, (where V is the ground voltage) can be completely eliminated.

Next, when 5AOUT changes from °'H" to °°L", the output PG of the Nant gate 53 immediately changes from "L" to °°L.
The output driver P-channel MOS transistor P1 changes to PG potential V oo V tr
It turns off at time t1 when it reaches H. Moreover, the output NG of the negative AND gate 54 means that the output of the delay circuit 301 is
After changing from H′° to °L゛°, it immediately changes from °°L°° to H゛°, and the N-channel type MOS of the output driver
The transistor N1 is turned on at time t2 when the potential of NG reaches V thn.

At this time as well, the time tl when the P-channel type MOS transistor P1 turns off and the time tl when the P-channel type MOS transistor P1 turns off and the time tl when the P-channel type MOS transistor P1 turns off and the time tl when the P-channel type MOS transistor
At time t2 when 1 turns on, due to the effect of the delay circuit 301,
A time difference of Δt2 can be ensured, and there is no period in which both Pl and Nl are on. Therefore vo. -PI-Nl-V
The through current in the ss path can be completely eliminated.

In this manner, the present invention can completely eliminate the through current in the output driver, making it possible to realize a semiconductor memory device with low power consumption. Furthermore, it is possible to completely eliminate malfunctions of internal circuits caused by these peak currents, etc., and it is possible to provide a semiconductor memory device with stable operation.

Also, so far we have described the configuration of a Nant gate and a negative AND gate as shown in Figure 1, but the same effect can be obtained even if these elements are combined in impark etc. Needless to say.

Furthermore, it goes without saying that the present invention can be widely applied even if the output driver has a configuration other than that shown in FIG. 1 (for example, both are composed of N-channel type MO3I-LAN disks).

Furthermore, although the structure of the delay circuit is an inverter circuit in FIG. 1, it is not limited to this, and it is clear that it can be widely applied by combining transistors, capacitors, etc.

[Effects of the Invention] As described above, according to the present invention, the P-channel type MOS transistor of the output driver and the N-channel type MO3I-
It is possible to set an arbitrary time difference between the on-off times of the transistors. As a result, the through current in the output driver can be completely eliminated, making it possible to provide a semiconductor memory device with low power consumption.Also, it is possible to eliminate malfunctions in the internal circuit due to the peak current of the through current, etc. Therefore, it is possible to provide a semiconductor memory device with stable operation.

[Brief explanation of the drawing]

1 is a diagram showing an embodiment of a semiconductor memory device according to the present invention, FIGS. 2(a) and 2(b) are characteristic diagrams of the circuit in FIG. 1, FIG. 3 is a diagram showing a conventional technique, Figures (a), (b), (c
) and (d) are characteristic diagrams showing the characteristics of the prior art shown in FIG. 100...Sense amplifier circuit 200...Output side i output circuit 300.301/Delay circuit 5AOUT...Sense amplifier circuit output OE...
・Output control circuit output PG, NG...Output driver input signal 0LIT...
...External output 50...Inverter circuit 51.53...Nant gate 52.54...Negative AND gate PI...
...P-channel type MOS transistor N1... ...N-channel type MO3I-transistor and above Applicant Seiko Epson Co., Ltd. Agent Patent attorney Kizobe Suzuki (1 other person) Figure 1 TIME Figure 2 (a) TIME Figure 2 (b) Figure 3 TIME Figure 4 (a) TIME Figure 4 (b) TIME Figure 4 (C) I ME Figure 4 (d)

Claims (1)

[Scope of Claims] A semiconductor memory device comprising an output buffer circuit that outputs data of a selected memory cell sensed by a sense amplifier to the outside, and an output control circuit that controls the output buffer circuit, comprising: a first logic circuit that receives a signal output from the sense amplifier circuit and a signal output from the output control circuit; a second logic circuit that receives the signal output from the sense amplifier circuit; and a second logic circuit that receives the signal output from the sense amplifier circuit;
a third logic circuit which receives as input a signal obtained by delaying and inverting the output from the logic circuit; a signal output from the sense amplifier circuit; and a signal output from the sense amplifier circuit;
a fourth logic circuit that receives as input a signal obtained by delaying and inverting the output from the logic circuit; a signal output from the third logic circuit; and a signal output from the fourth logic circuit. What is claimed is: 1. A semiconductor memory device comprising: an output driver for outputting data to the outside;