JPH02309679A - Insulated-gate fieid-effect transistor - Google Patents

Abstract

PURPOSE:To facilitate the fine formation of a patterning and to reduce a channel resistance by a method wherein an overlapped structure, wherein source regions are respectively provided on each gate film, is adopted. CONSTITUTION:First conductivity type regions (such as, source regions 15) do not exist between mutually adjacent polycrystalline silicon gate electrode films 14 and 14 and a second conductivity type region (such as, a channel diffused region 16) only exists between the gate electrode films 14 and 14. Moreover, a channel inversion layer 18, which is formed in the second conductivity type region, faces an insulating film along the side ends of the films 14 and is orientated in the film thickness directions (the longitudinal direction) of the films 14. Accordingly, there is no need to form electrodes, which are conducted to the source regions 15, next the films 14 and each region 15 and the source contact of the region 15 can be constituted on each film 14 as an overlapped structure. Thereby, the fine formation of a patterning is possible and a channel resistance can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to power MO3FET and conductivity modulated MO3
The present invention relates to insulated gate field effect transistors such as FETs (hereinafter abbreviated as single rGBT), and particularly relates to insulated gate field effect transistors having a multilayer structure having a source region on a gate film.

[Conventional technology]

For example, the structure of a conventional power MO3FET, as shown in FIG. Polysilicon 4 directly below 4 formed through
, a highly doped P-type channel diffusion region 5 and a highly doped N-type source region 6 formed by double diffusion using the polysilicon gate 4 as a mask, a source electrode 7 in conductive contact with the source region 6, and a source It has an interlayer insulating film 8 that insulates the electrode 7 and the polysilicon gate 4, and a drain electrode 9 deposited on the back side of the substrate.

This is because electrons flow horizontally from the source region 6 to the drain/drift region 2 via the channel inversion layer 9 formed on the surface of the channel diffusion region 5 directly under the polysilicon 4, and then flow vertically toward the drain electrode 9. It flows in one direction.

The structure of the IGBT is as shown in FIG. 4, with a highly concentrated P-type minority carrier (hole) injection layer under the drain layer l, and the structure of the M2S part is the same as that shown in FIG.
It is no different from O3FET.

By the way, the on-resistance of the vertically structured power MO5FET can be approximately expressed as the sum of the channel resistance of the M2S portion and the resistance of the drain drift region 2. Billet 1
The resistance of the drain drift region 2 is mainly determined by its thickness, and the thickness is almost uniquely determined by the withstand voltage, so it is impossible to lower the resistance of the drain drift region 2 while maintaining the same withstand voltage. Can not. On the other hand, in order to reduce the channel resistance, it is necessary to miniaturize the pattern to achieve shorter channels.

[Problem to be solved by the invention]

However, the insulated gate field effect transistor having the MO3 structure has the following problems.

That is, the distance a between adjacent polysilicon gates 4.4 is 1.
The limit is around 0 μm, and miniaturization smaller than that results in technical difficulties and a decrease in yield. The reason for this is that the patterning of the interlayer insulating film 8 and the contact formation between the source region 6 and the source electrode 7 are included in the planar distance a, which is also the size of the cell. Since is the contact dimension between the source electrode 6 and the semiconductor, if this is made too small, the contact resistance will increase and contact with the source region 6 will not be possible. Furthermore, if the distance a is reduced to reduce the difference between the patterning dimensions, contact between the source electrode 6 and the polysilicon gate 4 may occur due to patterning misalignment or side etching of the insulating film 8, which may result in device failure. big. In other words,
Since each region is created between adjacent polysilicon gates using multiple photolithography processes, there is a limit to the miniaturization of the M2S part, making it difficult to significantly reduce channel resistance. Ta.

Therefore, an object of the present invention is to facilitate miniaturization of patterning by adopting a multilayer structure in which a source region is provided on a gate film without providing a source region and source electrode contact portion between adjacent gates. An object of the present invention is to provide an insulated gate field effect transistor that achieves a significant reduction in channel resistance.

[Means to solve the problem]

In order to solve the above problems, the means taken by the present invention is to provide a gate electrode film surrounded by an insulating film on a first conductivity type semiconductor layer (e.g., a drain region) that is electrically connected to a first electrode (e.g., a drain electrode). (for example, a polysilicon gate), and is formed on the gate electrode film with the insulating film interposed therebetween,
A first conductivity type region (for example, a source region) is provided which is electrically connected to a second electrode (for example, a source electrode), is adjacent to the gate electrode film with the insulating film in between, and is adjacent to the first conductivity type semiconductor layer and the first conductivity type semiconductor layer. A second conductivity type region (for example, a channel diffusion region) is formed in contact with both conductivity type regions.

[Effect]

According to this means, there is no first conductivity type region (for example, a source region) between adjacent gate electrode films, and only a second conductivity type region (for example, a channel diffusion region) exists.

Further, the channel inversion layer formed in the second conductivity type region faces the insulating film along the side edges of the gate electrode film, and is oriented in the thickness direction (vertical direction) of the gate electrode film. Therefore, there is no need to form an electrode that conducts to the source region next to the gate electrode film, and the source region and its source contacts are configured as a multilayer structure on the gate electrode film, which allows for finer patterning than in the past. Since the channel length can be limited to the thickness of the gate electrode film,
A significant reduction in channel resistance is achieved. Furthermore, since the source region is formed on the gate electrode film, the source electrode can be brought into contact with the entire surface of the source region, simplifying the wafer process and improving yield.

〔Example〕

Next, embodiments of the present invention will be described based on the accompanying drawings.

FIG. 1 is a longitudinal sectional view showing an embodiment of an insulated gate field effect transistor according to the present invention.

In the figure, ■ is a highly doped N-type drain layer, on which a lightly doped N-type drain drift region 2 is formed.

A silicon oxide film 14a is formed on the drain drift region 2.
A polysilicon gate 14 surrounded by a polysilicon gate 14 is formed. Furthermore, a silicon oxide film 1 is formed on the polysilicon gate 14.
A highly doped N-type source region 15 is formed through 4a. Therefore, drain layer 1. Drain drift region 2. The polysilicon gate 4 and the source region 15 constitute a multilayer structure. Separated polysilicon gate 1
A P-type channel diffusion region 16 is formed between the regions 4 and 4. This channel diffusion region 16 is a polysilicon gate 4
It faces the silicon oxide film 14a at the side end portion of and is in contact with the source region 15 on the polysilicon gate [4].

Reference numeral 17 is a source electrode that almost contacts the entire surface of the source region 150, and reference numeral 9 is a drain electrode that is deposited on the back side of the substrate.

A source region 15 is formed on the polysilicon layer 14 (such as this).
In the multilayer structure with , the channel inversion layer 18 is produced around the side edges of the polysilicon gate 14 and has a channel length approximately equal to the thickness of the polysilicon gate 4 . Since only the P-type channel diffusion region 16 is formed in the region between the polysilicon gates 14 separated from each other, the cell size A can be set to about 1 μm.
The width and thickness of the polysilicon gate 14 can be relatively miniaturized, and the channel resistance and device occupation area can be reduced. When the surface of polysilicon gate 14 is completely covered with source region 15, the length of channel inversion layer 18 is approximately limited to the thickness of polysilicon gate 14. That is, since the orientation direction of the channel inversion layer 18 is not mainly in the plane direction of the polysilicon gate 14, but is mainly in the thickness direction, it is possible to reduce the channel resistance by shortening the channel from this point of view. can be significantly improved. Furthermore, by providing the source region 15 on the polysilicon gate 14, the contact of the source electrode 17 to the source region 15 is over the entire surface of the source region 15, which is convenient for wafer processing and improves yield.

When such a multilayer structure in which the source region 15 is formed on the polysilicon gate 14 is applied to an IGBT, it has the following advantages. Since the IGBT allows not only majority carriers but also minority carriers to flow, current also flows in the P-type channel diffusion region 16. For this reason, conventionally, the potential of the channel diffusion region may rise higher than that of the source region, resulting in a parasitic NPN transistor consisting of an N-type source region, a P-type channel diffusion region, and an N-type drain/drift region. is activated and rough lumps are likely to occur. However, in the structure of this embodiment, the contact between the channel diffusion region 16 and the source electrode 17 can be formed closer to the substrate than the contact between the source region 15 and the source electrode 17.
The rise in potential of the channel diffusion region 16 is suppressed, contributing to prevention of latch-up.

Next, the manufacturing method of the above embodiment will be explained based on FIG. 2.

First, as shown in FIG. 2(A), the surface of the substrate provided with the drain drift region 2 is thermally oxidized to form a silicon oxide film 2a to be used as a gate oxide film. Then the second
As shown in FIG. 2B, a polysilicon layer 20 is deposited on silicon oxide film 2a by CVD. Next, the polysilicon layer 20a is buttered to form a polysilicon gate 14 as shown in FIG. 2(C), and then the exposed portion of the silicon oxide film 2a is buttered as shown in FIG. 2(D). Remove. Next, thermal oxidation is performed again as shown in Figure 2 (E
), after forming a silicon oxide film 21a on the side and top surfaces of the polysilicon gate 14, the silicon oxide film 21a other than the polysilicon gate 14 is removed as shown in FIG. 'The silicon gate 14 is surrounded by silicon oxide films 2a and 21a. Next, as shown in FIG. 2(G), CVD is applied over the entire surface.
After depositing a polysilicon layer 22 by a method, the polysilicon layer 22 is recrystallized by laser irradiation or a 70-ting zone method to obtain a single crystal layer 23 shown in FIG. 2(H). Next, after introducing boron into the entire surface of the single crystal layer 23 by ion implantation or the like, a P-type diffusion region 24 shown in FIG. 2(1) is formed by thermal diffusion. Next, selective ion implantation is performed on the polysilicon gate 14, as shown in FIG.
), a highly doped N-type source region 15 is formed. As a result, the remaining region of the previously formed P-type diffusion region 24 becomes the channel diffusion region 16. Next, a source electrode 17 that contacts the surface of the source region 15 is deposited.

The feature of this manufacturing method is that after forming a silicon oxide film 2a on the lower surface of the polysilicon gate 14 in advance, a silicon oxide film 21a is formed on the remaining surfaces (side and top surfaces) of the polysilicon gate 14, and then the polysilicon gate A polysilicon layer 22 is deposited from the level of the lower surface of the polysilicon layer 14 and then recrystallized.

FIGS. 3(A) to 3(H) are longitudinal cross-sectional views of semiconductors illustrating another manufacturing method for obtaining the structure of this embodiment. In this manufacturing method, first, as shown in FIG. 3A, a groove in which a gate is to be buried is formed on the surface of a substrate provided with a drain drift region 2 by etching. Next, as shown in FIG. 3(B), a silicon oxide film 32 is formed on the surface of the substrate including the inside of the substrate by thermal oxidation or the like. Then the third
After depositing a polysilicon layer 33 by the CVD method as shown in FIG. The buried polysilicon becomes a polysilicon gate 14. Next, as shown in FIG. After forming the polysilicon gate 1, as shown in FIG.
Remove silicon and oxide films other than 4. As a result, polysilicon gate 14 is surrounded by silicon oxide films 32 and 34. Next, as shown in FIG. 3 (G), CVD
After depositing a polysilicon layer 35 on the entire surface by the method, a third
As shown in Figure (H), this polysilicon layer 35 is recrystallized by laser irradiation, floating zone method, etc. to obtain a single crystal layer 36. The subsequent process is the same as that shown in FIG. 2 (J) and subsequent steps in the previous manufacturing method.

The feature of this manufacturing method is that after a silicon oxide film 32 is formed in advance on the lower and side surfaces of the polysilicon gate 14, a silicon oxide film 34 is formed on the upper surface of the polysilicon gate 14, and then one layer of the polysilicon gate 14 is formed. The point is that a polysilicon layer 35 is deposited from the surface level and then recrystallized.

〔Effect of the invention〕

As described above, the insulated gate field effect transistor according to the present invention has a multilayer structure in which a first conductivity type region is formed on a gate electrode film surrounded by an insulating film on a first conductivity type semiconductor layer. Since the second conductive type region is provided in contact with both the first conductive type semiconductor layer and the first conductive type region, the following effects are achieved.

■ Only the second conductivity type region where a channel inversion layer is to be formed exists on the side of the multilayer structure, and the first conductivity type region as a source region exists.
Since there is no conductivity type region and its electrode contact portion, the M2S portion can be significantly miniaturized compared to the conventional structure. Further, since the channel inversion layer is primarily oriented in the thickness direction of the gate electrode film, a further shortened channel can be achieved from this point of view as well, and the channel resistance can be significantly reduced.

■Another advantage of the multilayer structure consisting of a drain region, a gate electrode, and a source region is that the source electrode can be easily taken out in the manufacturing process, and when applied to IGBTs, the source electrode and the second conductivity type region It is possible to bring the contact portion with the first conductivity type semiconductor layer closer to the first conductivity type semiconductor layer side, and it is possible to suppress the increase in potential of the second conductivity type region that also functions as the base region of the parasitic transistor, thereby contributing to prevention of latch-up.

[Brief explanation of drawings]

FIG. 1 is a longitudinal sectional view showing an embodiment of an insulated gate field effect transistor according to the present invention. Figures 2 (A> to (K)) are longitudinal cross-sectional views illustrating a manufacturing method for obtaining the structure of the same example. FIG. 4 is a vertical cross-sectional view illustrating a manufacturing method. FIG. 4 is a vertical cross-sectional view showing an example of a conventional insulated gate field effect transistor. [Explanation of symbols] 1 Drain layer, 2 Drain/drift region, 9 Drain Electrode, 14 Polysilicon gate, 14a
Silicon oxide film, 15 source region, 16 channel diffusion region, 17 source electrode, 18 channel inversion layer, 2 a, 21a, 32.34 silicon oxide film, 20, 22.33.35 polysilicon layer, 23° 36 single crystal 14a.-, silicon oxide film Figure 1 Figure 2 (Part 1) Figure 2 (Part 2) Figure 3 (Part 1) Figure 3 (Part 2) Figure 4

Claims (1)

[Claims] 1) A gate electrode film surrounded by an insulating film on a first conductivity type semiconductor layer that is electrically connected to a first electrode, and a gate electrode film that is formed on the gate electrode film via the insulating film and that is electrically connected to a second electrode. It is characterized by having a first conductivity type region and a second conductivity type region adjacent to the gate electrode film with the insulating film in between and in contact with both the first conductivity type semiconductor layer and the first conductivity type region. Insulated gate field effect transistor.