JPH023199B2 - - Google Patents

Description

[Detailed description of the invention]

(Industrial application field) The present invention generates musical tones through digital signal processing.
related to electronic musical instruments that produce musical sounds similar to those of natural instruments.
Regarding electronic musical instruments. (Conventional technology) In recent years, electronic musical instruments have become more popular due to the introduction of digital signal processing.
It has become possible to create advanced sounds. Such an electron
For example, the musical instrument is shown in Japanese Patent Application Laid-open No. 107823/1983.
Ru. The block diagram is shown in Figure 14, and its operation will be explained.
I will clarify. 300 is a keyboard. 301 is R number
It is a memory and corresponds to the key pressed on the keyboard 300.
Generates corresponding frequency information (hereinafter referred to as R number)
do. 302 is a gate, which is opened and closed by clock φ.
Ru. 303 is an accumulator, and the clock φ timing
Repeatedly add the R number. Hence the accumulator
The output S of 303 becomes S=0, every time the clock φ is input.
It changes as R, 2R, etc., but when it exceeds a certain number N, S-
N remains in accumulator 303. 310 and 320 are waveforms
memory, waveform memory, and of the accumulator 303.
Read two series of waveforms using output S as address
vinegar. Therefore, waveform memory 310 and waveform memory 3
If the address space of 20 is N, the frequency of the output
teeth =R/N×(frequency of clock φ) …(1) becomes. Here, the waveform memory 310, waveform memo
The waveform logW which has been logarithmically transformed in advance is₁，
logW₂is stored in memory. 330 is a time function
It is a generator and generates a time function (t). 33
1 is a logarithmic converter (L/LG converter).
311 is an adder and a₁+a₂Calculate. 321 decreased
With a calculator, b₁−b₂Calculate. 312, 322 is a pair
It is a numerical/linear converter (LG/L converter).
341 is an adder. 350 comes from envelope
It is a natural organ. 342 is a multiplier, and adder 34
1 multiplied by the output of envelope generator 350
Do calculations. 343 is a D/A converter. 3
44 is an amplifier, and 345 is a speaker. 14th
To explain the operation in the diagram, a time function is generated by pressing a key.
A device 330 generates a time function (t). L/LG
The converter 331 converts the time function (t) into log
(t). On the other hand, as mentioned above, the waveform memo
The memory 310 and waveform memory 320 are given by equation (1).
The waveform logW at the frequency₁,logW₂Output. late
The output of adder 311 is logW₁+log(t), subtraction
The output of the device 321 is logW₂−log(t),
The output of LG/L converter 312 is W₁×(t),
The output of LG/L converter 322 is W₂/(t)
becomes. Therefore, the output of adder 341 is W₁×
(t)+W₂/(t), and the multiplier 342
The envelope generated by the envelope generator 350
the D/A converter 343,
A musical tone is output from the speaker 345 via the amplifier 344.
Output. (Problem to be solved by the invention) However, in the conventional configuration as described above, 2
It only changes the waveform mixing ratio over time.
So, for example, the tone of a musical instrument has a distinctive characteristic in the rising part.
However, with two-wave mixing, there is a subtle change in tone at the rising edge.
It is simply impossible to reproduce. The present invention
In view of the above problems, we have developed a method to improve the subtlety of the rise of musical instrument sounds.
In order to be able to reproduce even the most significant tonal changes along with the stationary part.
The purpose is to provide an electronic musical instrument with a (Means for solving problems) In order to solve the above problems, the electronic musical instrument of the present invention
is the waveform data of multiple periods at the rising edge of an instrument sound.
The first waveform is the waveform of one period of the stationary part of the musical instrument sound.
The shape data is the second waveform, and the sound corresponding to the first waveform is
The time change characteristics of the quantity are taken as the first envelope, and the
The first parameter is the parameterized one envelope.
time change of the volume corresponding to the second waveform.
The second envelope is the second envelope.
The second parameter is the parameterized version of
When the first waveform, second waveform, first parameter,
A data bank that stores the second parameter and a data bank that stores the second parameter.
Get the first and second parameters from the tab bank.
At the same time as reading, the first and second parameters
Restore the first and second envelopes from the
The original envelope forming means and the data bank
The first waveform is read out sequentially and multiple cycles of the first waveform are read out.
The waveform data of the last cycle of the waveform data of the period is repeated.
Read it repeatedly and multiply it by the first envelope to get the first envelope.
1 means for creating data; Repeatedly read the second waveform from the data bank
and multiply it by the second envelope to get the second data.
means for creating the data, and adding the first data and the second data.
It consists of a means for calculating and creating musical sound data.
The final waveform of the rising part of the instrumental sound has different tones.
You can also add sound to prevent the tone of the stationary part from becoming monotonous.
It is. (effect) With the above-described configuration, the present invention enables the user to make a reservation by pressing a key.
The first waveform records the rising part of the musical instrument.
from memory and repeat its last waveform.
Repeatedly read out the first waveform and second waveform.
The product of each independent envelope is mutually
Since the musical tone is created by adding the
Subtle changes in the rising part of the sound of a natural instrument are the steady part.
It can also be reproduced in
It is possible to prevent the tone of the steady-state part from becoming monotonous.
can. (Example) An embodiment of the present invention will be explained below based on the drawings.
Ru. FIG. 1 shows an information processing device according to the present invention as an electronic musical instrument.
FIG. This first figure
To explain, 1-1 is a keyboard. 1-2 is a tab
of the musical tones output from this electronic musical instrument.
This is an operation section for instructing tone selection. 1-3 is effective
It is a switch that controls various effects on musical sounds.
For example, you can control effects such as vibrato and tremolo.
This is a switch that instructs to turn on and off. 1-4 is ma
It is an icon (microcomputer), for example
Equivalent to Intel's microcontroller 8049. 1-5
is a musical tone generating section, and is given by microcontroller 1-4.
Waveform calculation and frequency calculation are performed based on the control signal
conduct. 1-6 is a data bank, which is a musical tone generator.
Waveform data and envelope data used in 1-5
ROM (read-only memory) where the data is stored
It is. 1-7 is a filter, which is a musical tone generator 1
-5 to suppress the aliasing noise of the musical tone signal output from
Remove. 1-8 are speakers. Next, we will explain the operation of the electronic musical instrument shown in Figure 1A.
Ru. Microcontrollers 1-4 have instructions pre-written internally.
In accordance with the order, keyboard 1-1, tablet 1-2,
The status of the output switches 1-3 is sequentially searched. Also ma
Icon 1-4 is the ON/OFF key on keyboard 1-1.
The code of the key being pressed based on the OFF state
divided into multiple channels of musical tone generators 1-5.
At the same time, the tablet
depending on the status of switch 1-2 and effect switch 1-3.
Send control data. Musical tone generator 1-5 smell
In this case, the assignment signal sent from microcontroller 1-4 is
and other control signals to internal registers.
data bank 1- based on these signals.
6. Enter the necessary waveform data and envelope data.
Musical tone signals are synthesized while being read. this musical tone
The musical tone signal synthesized in the generating section 1-5 is
is sent to speakers 1-8 through routers 1-7.
Generates musical sounds. Figure 1 (b) shows the musical tone generator 1- from the microcomputer 1-4.
The timing diagram for transferring data to 5 is shown below.
vinegar. Also, Table 1 shows musical sounds generated from microcontrollers 1-4.
The contents of data sent to section 1-5 are shown. Table 1
, NOD is note octave data.
, note data ND and octave data OCT and
It consists of key-on data and key-on data. The specifics
Table 2 shows the bit configuration of NOD.
Yes, Table 3 shows the correspondence between note data ND and note names.
is shown, and Table 4 shows the octave data OCT
The correspondence between the range and the range is shown. In other words, if a musical tone is generated
6th octare of note G# for parts 1-5
B sound (hereinafter abbreviated as G#6) from channel 1
When you want to output, use the address in Figure 1 B.
00000001 and 10011110 as data to microcontroller 1
-4 will be sent. Then the PDD
This is data that is used to shift the tuning.
It is 8bit data. PDD is displayed in two's complement notation.
The variable range is -128 to +127, 256 ways.
It is. RLD is release data, after key off
This is 4-bit data that controls the attenuation characteristics of .
VOL is the volume flag, and this bit
When set to “1”, it corresponds to the volume data VLD described later.
The output level of the musical tone signal from the musical tone generating section 1-5
This makes it possible to control the DMP is a damper
flag and for piano type envelopes
A flag that causes the decay after key-off to be rapid.
function, and functions when DMP=1. SOL is SO
This is a low flag and has the same note name as other channels.
occurs when the channel is assigned.
the current musical tone and the musical tone about to occur.
This flag is used to select whether or not to match the phase characteristics.
When SOL=1, phase matching is canceled.
do. TAB is tablet data, as shown in Figure 1.
The data specified by tablet 1-2 in
data is included in this 5 bit. PE is pitch extend
Channels that set this bit to “1” with flags
requires pitch extension. VLD is boli
Youum data, and the volume flag mentioned above.
The musical sound output from the channel along with the VOL
Control the level with 8bit precision. Furthermore, these
All series of data are set independently for each channel.
It can be determined. Next, the calculation sequence in the musical tone generator 1-5 is
Let me explain about this. Tables 5 and 6 show the calculation system of musical tone generator 1-5.
- indicates the sequence. In the main musical tone generating section 1-5
processes more data in shorter computational cycles
In order to perform the operation sequence is the initial mode,
It has two modes: normal mode, and the above
Both modes are long sequence and short, respectively.
Divided into sequences. Also, the initial
Doshoto sequence and normal moderon
There are two sequences, EVEN and ODD, respectively.
It has a state. In the initial mode, microcontrollers 1-4 generate musical sounds.
When commanding section 1-5 to generate a new musical tone
From the microcomputer 1-4 in the musical tone generator 1-5
Various registers etc. for the specified channel
This mode is used to perform initial settings and is a long sequence.
The shot sequence was started twice.
Then enter normal mode. This initial mode
Once for two shot sequences in
Shooting sequence where the first eye is ODD and the second time is EVEN.
It becomes After this initial mode ends, the normal
Move to mode, but after 6 shot sequences
There will be one long sequence. In this embodiment, two independent systems are provided for each channel.
Multiplies a standard waveform and two independent envelopes.
It has become possible to match it, and it has become even more precise.
It also has various adjustment functions, but these calculation processing
A large amount of performance is required to time-share eight channels.
Calculation steps are required. So in a short cycle
Short sequence of things that need to be calculated
and those with low calculation frequency, that is, long cycles.
A long sequence is one that can be operated on by
Ru. and long sea during shoot sequence
Improving the efficiency of calculations by inserting sequences
ing. Short sequence, long sequence in Figure 1
The timing diagram is shown below. As shown in Figure 1 C.
11 times of shot sequence (0) to (10)
The long sequence consists of slots.
Consists of 9 time slots (11) to (19)
There is. Each time slot is 250ns and 4
Divided into two non-overlapping phases of ψ1 and ψ3
The whole system works together with the clock.
Ru. The relationship between short and long sequences
If the short sequence starts from channel 0,
1 yan for every 8 repetitions up to yannel 7
Contains a long sequence of channels. Therefore, for example
Channel 3 shot sequence is 11×8+9
Long sequence once every 97 time slots of
The slot is divided once every 776 time slots of 97 x 8.
It will appear in Furthermore, normal mode
There are two types of long sequences: EVEN and ODD.
Since there is a time slot of 776×2,
The system operates in cycles. Next, perform individual calculations based on Tables 5 and 6.
Explain the sequence. As mentioned above, easy
The sound generating section 1-5 is activated by pressing a new key.
Now it starts with a long sequence.
From the initial mode long sequence
Explanation will be provided for each time slot. Addition section (13) PDD+PED →PDR (15) 0 →TR1 (16) 0 →TR2 (17) 0 →ZR1 (18) 0 →ZR2 What time slot (13) means is:
Contents of register PDD and register PED
Add the contents of the data and store it in a register called PDR.
That is to say. Time slot (15) ~
(18) are the records TR1, TR2, ZR1, ZR2.
This means writing 0 to the register. Data bank reading section (12) WTD→HAD→HAD (14) HAD→CONT→CONT, DIF1 (16)～(17) HAD→STE→EAR1 What these mean is that the data on the far left
(For example, if it is a time slot (14), it is called HAD.
data) as the address to data bank 1-6.
Read out the data CONT written in the center,
Stored in the registers CONT and DIF1 with the names on the far right.
It means paying. Initial mode sequence Addition section (1) PDR+JD L.B; 0→ER2/1 (3) ORG+OCT+1→WE2→ΔWAR (4) D.B＋EAR1→EAR2 (6) 0 →WR1 (8) 0 →ER1 (9) 0 →WE2 (10) 0 →WE1,WR2 0→ER2/1 in time slot (1) is a
ER2, 2 at the first start sequence, that is, ODD.
At the time of EVEN, the register ER1 is set to 0.
means to write. Also, L.B means PDR
+JD operation result is stored in the L buffer without storing it in the register.
It is sent to the multiplier (described later) via the
means. In time slot (3),
After storing the calculation result in a register called WE2,
This means to decode and store it in ΔWAR.
D.B in time slot (4) is the data described below.
Register the value obtained by the bank read section.
Send to the adder via the D bus (described later) without going through the
It means to do. Multiplication section (4)～(6) C.B×CN1→FR The above C.B registers the result obtained in the addition section.
This means inputting directly to the multiplication section without going through the star.
In this case, the time slot (1) is obtained.
means the calculated result of PDR+JD. Data bank reading section (1) HAD→ΔSTE→A.B. (3)～(4) EAR1/2→E1/2→ΔT1/2, ΔE1/
2, ΔZ1/2 (6)〜(7) HAD→STW／ΔSTW→STW／WAR Here, A.B. of time slot (1) is the data base
The value obtained by reading the link is stored in a register, etc.
It is meant to be input directly to the A input of the adder without going through the
Taste. Also, STW/of time slots (6) to (7)
ΔSTW→STW/WAR is short sequence
At the first ODD, read the data STW.
and store it in a register called STW, and immediately execute it the second time.
At EVEN, read out the data ΔSTW.
This means that it is stored in a register called WAR.
Ru. Next, the normal mode will be explained. Normal mode shot sequence In Table 6, the places marked with * are no
The first shoot after a toklock occurs
The calculation is performed only by the
Calculate the flags that control the behavior of the request flag CLRQ
I will call it. Addition section (1) WE2＋WE1 →L.B・ (2) STW+WAR →D.B., B.B. (3) ZR1＋ΔZ1 →ZR1 (4) DIF1＋C.B.→D.B. (5) ER1＋ΔE1＋Ci →ER1 (6) ZR2＋ΔZ2 →ZR2 (7) WAR＋ΔWAR →WAR＊ (8) ER2＋ΔE2＋Ci →ER2 (9) FR＋CDR →CDR＊ Here, L.B. of time slot (1) is the calculation result
is input directly to the multiplier without going through a register.
means. D.B. and B.B. of time slot (2) are the same.
The calculation results are directly transferred to the data bank reading section and
This means inputting to the B input of the adder. Thailand
C.B. in Muslot (4) is the calculation result of the addition section
This means inputting directly without going through a register.
In this case, STW at time slot (2)
The calculation result of +WAR is input. Also, D.B.
The calculation result is directly input to the data bank reading section.
It means to force. Time slots (5) and (8)
Ci at time slots (3) and (6), respectively.
It means to add the carry of the operation
It's the taste. Multiplication section (1)～(3) WR2＋ER2→WE2＊ (4)～(6) C.B.×CN→(DAC) (7)～(9) WR1×ER1→WE1＊ Here, the C.B. of time slots (4) to (6) are additions.
Input the output of the section directly to the multiplier section without going through a register etc.
It means to do. In this case, the time slot
This corresponds to the calculation result of WE2+WE1 in (1). Ma
(DAC) means that the result of this calculation is
Indicates input to a DA converter (described later). Data bank reading section (4)～(5) C.B.→W1→WR1＊ (7)～(8) C.B.→W1→WR2＊ Here, C.B. of time slots (4) to (5) is the addition section.
Input the calculation results directly to the data bank reading section.
and set it as the address of data bank 1-6.
In this case, the time slot in the adder is
This corresponds to the calculation result of STW + WAR in (2). Ta
Time slots (7) to (8) C.B. are also time slots.
Compatible with the calculation result of DIF1 + (STW + WAR) in (4)
I guess. long sequence Addition section (13) ΔT1/2 + TR1/2 →TR1/2 (14) PDR＋JD →L.B. (15) ΔEAR1/2+EAR1/2+Ci →EAR1/2 (16) PDD+PED →PDR Here, the L.B. of time slot (14) is the addition
The calculation result of the section, that is, the value of PDR + JD, is transferred
This means that it is directly input to the multiplication section. Thailand
The Ci of Muslot (15) is the Ci of Time slot (13).
Carry that occurs as a result of calculation is
means. Multiplication section (16)～(18) CN＋C.B.→FR Here, C.B. registers the operation result in the addition section.
This means inputting directly to the multiplication section without going through the star.
However, in this case, the adder time slot (14)
The calculation result of PDR+JD is input. Data bank reading section (14)～(15) EAR2/1→E2/1→ΔT2/1,
ΔE2/1, ΔT2/1 Here, 2/1 means the odd number of times, i.e.
2 for ODD (e.g. E2 for E2/1), even number
At the time of EVEN, it becomes 1 (E1)
means read different data with EVEN, ODD
This means storing it in another register. Figure 2 shows the musical tone generator 1-5 in Figure 1A.
FIG. First, use this diagram to create each block.
To explain the outline of the function, 2-1 is the master clock.
Here, we use f=8.00096MHz.
I am using it. 2-2 is a sequencer (hereinafter referred to as SEQ)
), and the clock is clocked by master clock 2-1.
The frequency of the tsuku signal is divided, and the entire musical tone generating section 1-5
sequence signal (hereinafter referred to as SQ signal) and each
Generates seed control signals. 2-3 is microcomputer interface
-FACE Department (hereinafter referred to as UCIF), and the
Microcontrollers 1-4 can easily process the various data shown in the table.
The sound is transmitted asynchronously with the sound generator 1-5, but this
SQ generated by SEQ
This is a circuit that synchronizes with the signal. Further flag Kon
Initial mode, normal mode
Generates a flag INI that instructs mode switching. 2
-4 is the comparison register section (hereinafter referred to as CDR).
register CDR shown in the above calculation sequence.
Sequentially divide the 8 channels and the master clock.
Compare the obtained 10-bit frequency divided signal and select 8 channels.
The notebook clock and calculation request flag CLRQ for
Occur. 2-5 is random access memory section
(hereinafter referred to as memory) in the musical tone generator 1-5.
Stores the results of various operations performed. 2-6 is the frame
This is the Ludder Department (hereinafter referred to as FA), and it is a
Built-in 16-bit full adder for adding data.
There is. 2-7 is the multiplication part (hereinafter referred to as MPLY)
can be, (2's complement 12 bits) x (absolute value 10 bits) It has a multiplier that performs calculations. 2-8 is digital
A digital analog converter (hereinafter referred to as DAC)
Yes, the digital output from MPLY2-7
Convert musical sound data to analog musical sound data.
2-9 is an analog buffer memory section (hereinafter referred to as ABM).
), the machine cycle frequency is calculated from DAC2-8.
The musical sound data generated in the period is emitted from CDR2-4.
Conversion to pitch synchronization using generated note clock
I do. The functions and configuration of ABM2-9 are disclosed in Japanese Patent Application Publication No. 59
− Analog buffer shown in Publication No. 214091
It is similar to memory. 2-10 is input/output time
It is a data bank (hereinafter referred to as I/O).
1-6, and sends the address signal to
Waveform data and envelope data corresponding to the
Read data as necessary
Perform data conversion. 2-11 is the matrix
Ituchi Department (hereinafter referred to as MSW), UCIF2
-3, connected to CDR2-4, memory 2-5
Horizontal bus lines (HA, HB, HC, HD,
HE, HL buses) and FA2-6, MPLY2-
7. Vertical bar connected to I/O2-10
line (A, B, C, D, L buses) and
This is a circuit that connects according to the SQ signal. these
The calculation sequence shown in Tables 5 and 6 depending on the circuit.
It is the one that executes the steps. Next, each block will be explained. Figure 4 is a detailed diagram of SEQ2-2 in Figure 2.
It is. 4-1 is a counter and a master clock
The various timing signals shown in Figure 1C are
generate a number. TS is the time in Figure 1 C
This is a signal representing the lot, and CHC is the channel control signal.
channel number in Figure 1 C.
This is a signal representing EV is in the calculation sequence.
These are signals representing ODD and EVEN, and EV=0 is
ODD, EV=1 means EVEN. 4-2 is
It is SQROM (sequence ROM). SQROM4
-2 address input has a signal representing the time slot.
No. TS and flag INI are input, and these
each time slot based on the input.
Generating seed control commands. 4-3 is a logic gate
The output from SQROM4-2 is
Further control is performed using the calculation request flag CLRQ, etc.
SQ signal (performance information, effect switches 1-3, etc.)
As shown, each functional block is assigned to each time slot.
A signal that instructs how to operate in each case;
Inside, abbreviated as SQ) is generated. FIG. 5 is a detailed diagram of UCIF2-3. Figure 5
5-1 is a latch, and in Fig. 1, 5-1 is a latch.
A/D0~7 given by microcomputer 1-4
Latch by ALE. The relationship between A/D0~7 and ALE
The person in charge is as shown in Figure 1B, so latch 5
-1 has the addresses shown in Table 1 latched.
be done. 5-2 is a latch, and microcomputer 1-4
A/D0 to 7 given by more latches.
do. The relationship with A/D0~7 is shown in Figure 1B.
As shown in Table 1 for latch 5-2,
The data will be latched. 5-3 is rat
and is controlled by the latch 5-1.
Latch the output. Write the address in two stages like this
The reason for this is that the ALE latches periodically, regardless of the
This is because it becomes “1”, and the address is set like this.
A new design is achieved by latching in two stages.
Latch 5-3 until data is written.
Address and data are stored in 5-2 respectively.
It will be. 5-4 is 8 bits per word.
RAM, A is address input, OE is output control
control terminal, and data terminal D is connected to the HE bus.
It is. Here, when OE=1, given by A input,
Outputs the data of the received address from the D terminal.
Ru. Also, WE is a write control terminal, and when WE=1
At the same time, the data given to the D terminal is given to the A input.
Write to the given address. OE、WE is SQ credit
It is controlled by the number. RAM5-4 has the first
Various data shown in the table (NOD, PDD, RLD,
VOL/DMP/SOL, TAB/PE, VLD) and CO
control data CONT (written from data bank)
It's crowded. (details will be described later), pitch data register data
Each data PDR is stored for 8 channels.
There is. 5-5 is a selector, and microcomputer 1-4
and the address specified by the SQ signal.
selectively outputs the response using another SQ signal, and
This is given to the A input of 5-4. 5-6 is faith
It is a signal processor, connected to the HE bus, and
It takes in data and generates various flag signals. Ma
Release date sent from microcontroller 1-4
16 types of release errors depending on the data RLD4 bits.
Generates envelope data and sends it to the HE bus
Ru. 5-7 is a gate, which responds to the SQ signal.
The output of Tsuchi 5-2, that is, the output from microcomputer 1-4.
Send data onto the HE bus. Next, the operation of UCIF2-3 will be explained. The data shown in Table 1 is the type shown in Figure 1 B.
Assuming that it is given from microcontrollers 1-4 at the timing,
If the address is 05₁₆, the data is 89₁₆In other words, Chiyanne
If you instruct key 5 to press key F#1, first
The address is locked in latch 5-1 by the ALE signal.
The latch 5-2 is then connected to the latch 5-2 by a signal.
At the same time the data is latched, the latch 5-3 is connected.
The dress is latched. Then at a predetermined timing
selector 5-5 selects the output of latch 5-3.
At the same time, gate 5-7 opens and RAM 5-4
A write signal is given to the WE of. this write
Latch 5-2 is latched on the HE bus by the signal.
The data that was written, that is, the data that microcontrollers 1-4 try to write
data i.e. 89₁₆is given, RAM5-4
The A input is 05, which is the output of latch 5-3.₁₆gave
Therefore, address 05 of RAM5-4₁₆to the address
89₁₆The data will be written. Do it like this
The various data shown in Table 1 are written to RAM5-4.
It gets sucked in. As shown in Table 1, RAM5-4
Flags such as VOL flag and PE flag are written in
These flags are included in the HE bus.
It is sent to the signal processor 5-6 via the
I've been using it since I got it. FIG. 6 is a detailed diagram of CDR2-4. 6-1
is a 10-bit frequency divider that uses the master clock as input.
It is. 6-2 is RAM with comparator (hereinafter referred to as CDRAM)
It is called. ), 8 words with 13 bits per word
has. The top 10 bits of each word are compared.
A frequency divider 6 is provided with a frequency divider and is input from terminal T.
A comparison is made with the frequency division data at -1, and the 10-bit
When all the tests match, a match pulse is output from terminal C.
Output. The functions of OE, WE, A, and D are as described above.
It is the same as RAM5-4. 6-3 is a decoder
Yes, the relationship between A input, EN input and D output is shown in Table 8.
As shown below. 6-4 to 6-11 are RS La
When a positive pulse is applied to the S input, the Q output
When the force becomes “1” and a positive pulse is applied to the R input, Q
Output becomes “0”. RS latch 6-4 is a change
channel 0, RS latch 6-5 is channel 1,...
A coincidence pulse of is applied to S. 6-12 is sele
It is a controller, and the channels are
One of them is transmitted by the channel code CHC3 bit.
Select the number and output from D. 6-13 is latch
According to the SQ signal, the output of selector 6-12 is
Latch power. 6-14 is an AND gate. Next, regarding the operation of CDR2-4 shown in Figure 6.
explain. Frequency divider 6-1 divides the master clock
and sends the 10-bit frequency divided output to T of CDRAM6-2.
give to input. Each word of CDRAM6-2 has
Contains arbitrary values, but the top 10 bits of these values
When the output value matches the output value of the frequency divider 6-1,
Output the matching pulse from the C terminal. CDRAM6-
The A input of 2 is a signal representing CHC, that is, a channel.
has been entered, so each word has its own channel.
Since it is compatible with all channels, it is possible to
generates a pulse. This coincidence pulse is
is input to RS latches 6-4 to 6-11.
Therefore, the channel corresponding to the coincident pulse is
The Q output of the RS latch is set to "1".
One of the Q outputs of RS latches 6-4 to 6-11
Selector 6 according to channel code CHC
-12 are sequentially selected and locked in latch 6-13.
be touched. The output of latch 6-13 is an AND gate
6-14, so currently selector 6
The Q output of the RS latch selected by -12 is “1”
Then, the SQ signal applied to AND gate 6-14
Depending on the number, the corresponding channel of the D output of the decoder 6-3
When the channel becomes “1”, the Q output of the above RS latch becomes
Reset to “0”. FIG. 7 is a detailed diagram of the memory 2-5. Figure 7
In, 7-1 to 7-4 are RAM, OE,
Each function of WE, A, and D is the same as RAM5-4 mentioned above.
It is the same. Here, RAM7-1 has WAR,
EAR1, ΔZ1, ΔE1, WE1, EAR2, ΔZ2, ΔE2
Each register is WR2, ZR in RAM7-2.
1, ΔT1, FR, ΔWAR, ZR2, ΔT2
The register is ER1, TR1, DIF in RAM7-3.
1, DW1, ER2, TR2, STW, TAB′,
Each register of HAD is stored in RAM7-4, NOD′,
Each WE2 and VLD' register has 8 channels.
channels are stored. Note that NOD′, TAB′,
VLD′ is NOD, VLD in RAM5-4 mentioned above
This is the data written. 7-5 is 1 w
It is a ROM with 10 bits and 13 words, as shown in Table 5.
Note person in the calculation sequence shown in Table 6
A number of CNs are memorized. Here Q is the output and A is
Address input, OE is output control terminal, OE=
1 outputs the ROM contents to Q, and when OE=0
Q = high impedance. note coefficient
The values of CN are shown in Table 7. In addition,
The 10-bit output of ROM7-5 is the lower part of the HD bus.
Connected to 10 bits. 7-6 is a signal processor
, ND from NOD′ stored in RAM7-4
(note data) and OCT (octave data)
Read these data and based on PE flag
A circuit that generates pitch detuned data PED,
Also, read out the data in register WE2 and decode it.
It is equipped with a decoding circuit to read the data. FIG. 8 is a detailed diagram of FA2-6. In Figure 8
, 8-1 to 8-8 are latches, and SEQ
It operates using the signals ψ1 and ψ3 generated by 2-2.
8-9 is an adder, and the value given to the A input and
The value given to the B input (both 16 bits) and the
-Adds the value given to input Ci, and calculates C and
Output from Co. Co is the carry resulting from the operation.
– is the output. 8-10, 8-11 are bit processing
This circuit is based on latch 8-1 and latch 8-2.
This is a circuit that performs bit manipulation of the output. 8-12 is
It is a logic gate, and the latch 8-
Forcibly set the output of 6 to “1” or “0”.
Alternatively, if you output it as is, the following operation will be performed. 8
-13 is RAM, its size is 1 word 9
It consists of 12 words in bits. A, D, WE,
Each function of OE is the same as that of the RAM 5-4 described above.
The D output 9 bits are connected to the lower 9 bits of the C bus.
It is. RAM8-13 are phase aligned (described later)
This is for reading individual waveform data of 12 notes.
Performs phase management of the protruding address (WAR). Figure 9A is a detailed diagram of MPLY2-7. No.
In Fig. 9, 9-1 to 9-9 are latches. child
Here, latch 9-3 contains bits 0 to 3 of the L bus.
9, but latch 9-5 has bits 9 to 9 of the L bus.
12 is connected. 9-10 is an encoder
be. The input/output relationship is as shown in Table 9.
Ru. 9-11 is a shifter, input from I
The 16-bit signal follows the control signal input to C.
Shift and output from O. The contents of the shift are the 10th
As shown in the table. 9-12 is bit processing time
The latch 9-3 outputs in response to the SQ signal.
Performs bit processing of the signal. 9-13 is a decoder
Assuming input A and output D, the relationship is shown in Table 11.
It is a cage. 9-14 is a selector and enters C.
If C=1, then A, depending on the input SQ signal.
If C=0, select the 16 signals input to B.
Select and output from Y. Note that the lower 11 bits of A input
is connected to GND (ground potential) (i.e.
“0” is given). 9-15 is shifter I
The 14-bit signal input from C is input to C.
It shifts according to the control signal and outputs from 0. Schiff
The contents of the list are shown in Table 12. 9-16
is a multiplier, and the A input is 12 according to this complement representation.
Bit, B input is 10 bits of absolute value and output is 2 bits.
It is 14 bits with complement representation. Normally 12 bits
Performing a 10-bit operation yields a 22-bit result.
However, the 14-bit output of multiplier 9-16 is of course 22-bit.
These are the top 14 bits of the total. Therefore, the multiplier
The input/output relationship in 9-16 is as follows:
become. C=A×B/256 In addition, multiplier 9-16 in MPLY2-7
uses the following technique to further simplify the circuit.
I'm there. Normally, when configuring a multiplier, a 2's complement value of 12 bits is used.
A multiplier with bits x absolute value of 10 bits has 116 adder sets.
22-bit accurate arithmetic results can be obtained.
However, in this system, the 22-bit
Only the top 14 bits of the bits are used. That is,
In this example, the output of the lower 8 bits is not used.
The calculation error due to the omission of the adder cell is in the upper 14 bits.
Addition for lower 7-bit operations that does not affect the LSB of
All cell cells are omitted. Therefore, this multiplier 9
-16 has 28 adder cells for lower bit operations.
The configuration is as shown in Figure 9 (b), with the main part omitted.
Ru. In Figure 9B, similar cells are omitted within the broken line.
I wrote it down. Also, each block is a full adder.
input is A, B, Ci (carry input), output is sum
S and Cary Co. FIG. 10 is a detailed diagram of I/O2-10. No.
In Figure 10, 10-1 to 10-8 are latches.
Ru. Here, the latch 10-3 is a latch with a set
The latch input is connected to bits 7 to 9 of the D bus.
It is connected. 10-9 is the shifter selector,
Switching between A input and B input using C input, and switching between A input and
Performs a 1-bit shift. 10-10 is a bit processing circuit, and SQ signal
Force the lower 3 bits to “1” or
This is a circuit that sets it to “0”. 10-11 is a decoder
The relationship between input I and output D is shown in Table 13.
It is a cage. The A input of decoder 10-11 is
Bits 12 to 15 of the output of 10-7 are given.
It is being 10-12 is a selector, and C input
Which signal is being given to A or B depending on the force
Select one and output from Y. 10-13 is
It is a lid, and depending on the input of control terminal C, the output from I is
Shifts the input and outputs it from O. 10-14 is
It is a noise circuit, and the input depends on the noise flag NA.
Add noise to the force data. FIG. 11A is a detailed diagram of MSW2-11.
The part surrounded by a circle is the switch, and specifically the part
As shown in Figure 11B, it is composed of Nch MOSFETs.
When the SQ signal becomes “1”, the MOSFET is
When turned on, the vertical line and horizontal line become conductive.
data is transferred. In this MSW2-11
In order to speed up the data transfer,
ψ1 signal for each time throttle to all bus lines.
Transfer data after precharging by issue.
is being carried out. This switch is an Nch MOSFET
of the transferred data.
The “1” level is the threshold voltage of the MOSFET.
This is to prevent the vehicle from falling. Figure 11
Figure 11 shows the screen used in MSW2-11.
This is an example of the Itchi pattern, where the points of intersection are surrounded by circles.
The locations are connected via a switch. In this example
For convenience, we will explain the case where each bus is 8 bits.
Ru. Figure 11C shows bn and an(n) by the switch.
=0 to 7) are connected. Figure 11 D
is the four values b0 to b3 and “0” by the switch.
It is designed to write to the vertical bus.
Ru. Figure 11 E is b0 to b3 to a0 to a3, c
4 to c7 are written to a4 to a7
, and as a result, it appears separately on the two sets of buses.
data can be mixed and transferred to other buses.
It has been made possible. Figure 11
Converts the target position and transfers from bus to bus.
Therefore, I decided to arrange the switches like this.
The upper and lower 4 bits of data on the bus in the more horizontal direction are
change the position and transfer it to the vertical bus. Figure 11
Figures 1 to 11 show the circuit for setting constants to the bus.
This is an example of the route shown in Figure 11.
The circuit in Figure 11 is connected to the bus 10101010
A.A.₁₆This is a circuit to set. This is a switch
The parts without , a7, a5, a3, a1 are like this
By precharging just before the switch opens
Anything with “1” written is retained as is.
It depends. Figure 11 is determined by the flag TO.
It is designed to change the value of a number, and if TO=0
ba00₁₆is written to the bus and if TO=1 then EB₁₆
is written to the bus. Figure 11 C - Figure 11 Li
Install the switch shown in MSW2-11 according to the application.
By placing and selectively opening and closing, any bus
Bits that require data transfer from to any other bus
This makes it possible to include For example, HA bus?
to A bus, from HB bus to B bus, from C bus
SW when you want to transfer data to the HC bus at the same time
1, SW7, and SW13 should be turned on at the same time.
Also, data on the C bus is transferred to the L bus and D bus.
When necessary, turn on SW28, SW29, and SW30.
If so, C bus → HL bus → L bus and D bus
Data is transferred over the road. In addition, in MSW2-11, data transfer
is carried out at the timing shown in FIG.
In other words, in the section of ψ1=1, the vertical and horizontal bass lines are
Perform a pre-charge of in, and from the falling edge of ψ1
Data is transferred in the interval up to the falling edge of ψ3,
It latches at the falling edge of ψ3. Here, the standing of ψ3
The section from the descent to the rise of ψ1 is a latch operation.
This is the margin for stable operation. Next, data banks 1-6 will be explained. de
Data banks 1-6 store four types of data.
ing. They are (1) header address data, (2) header address data,
Tsuda data, (3) waveform data, (4) envelope data
It is ta. Here, the header address data is
Indicates at which address the data is stored
The data is 8 bits, and the header data is the waveform data.
address where the data and envelope data are stored.
8 bytes of data representing the resources and their attributes
It is. Next, we will explain the above four types of data in more detail.
I will clarify. (1) Header address data (HAD) This data is stored in each tablet, each octave, each
Address the note data assigned to each 3 keys.
Data that indicates the address of the header data as a
be. Table 14 shows the storage location of header address data.
As shown below. Tabs from bit 9 to bit 5
Set data TAB, bit 4 to bit 2
Turb data OCT, bits 1 to 0 are no.
The upper 2 bits of the data ND, the remaining bits are
All contain "1". TAB here,
The 10 bits consisting of OCT and ND are called WTD.
Each of them is shown in Table 1.
Not even. Header by header address data
The data address is shown in Table 15 and the bit
Header address data is entered in bits 10 to 3.
All upper bits are "1". Also, the lower bit
Enter data from 000 to 111 in Tuto 3. (2) Header data (HD) Header data is stored at the addresses shown in Table 15.
One word is 8 bits stored, so 8 words of data are stored.
The contents of each of the 8 words are shown in Table 16.
It is. In Table 16, CONT is the control
This is the header data and is indicated by this header data.
Displays the attributes of waveform data and envelope data.
vinegar. E1' is one of two types of envelope data.
On the other hand. The other envelope data E
The start address of 2' is given by STE + ΔSTE.
It will be done. W1 and W2 are two types of waveform data.
The start address of W1 is STW + ΔSTW.
Given. Note that CONT is configured as shown in Table 17.
The meaning is as follows.
Ru. P/O: The musical tone based on this header data is piano type.
Envelope or organ type envelope
A flag indicating whether the rope is attached,
If P/O=1, it means that it is piano type.
Taste. ORG: Which range does the musical sound data originally belong to?
This is 3-bit information that indicates whether the
The correspondence between ORG and range is shown in Table 18.
It is. Therefore, the waveform data is actually one cycle.
How many samples do you have as
It is also information that indicates. W8: Whether the waveform data is 12-bit precision or 8-bit
Indicates whether it is accurate or not. If W8=1 then 8
Bit precision. When W8=1, the waveform
4 bits “0” are added to the lower part of the data.
The amplitude level of the waveform is now maintained.
It's on. PCM: Rising part of waveform data W1 when PCM=1
Indicates that is PCM. NA: Used when superimposing a noise signal on a musical tone signal.
This is a 2-bit signal used. (3) Waveform data (W1, W2) As mentioned above, the musical tone generator 1-5 generates waves.
12-bit and 8-bit format data
Two types are used. sold here
When you think about ROMs, most of them are 1 word.
8 bits or less, 1 word
12 bits are rare. Therefore, the present invention
The waveform is stored in ROM as shown below.
That is, in the case of 8 bits, STW and ΔSTW
Store one word at a time from the address determined by
However, in the case of waveform data of 12 bits per word.
In this case, as shown in Figure 12, the upper 8 bits are
Starting from the address indicated by STW + ΔSTW
The following is stored, but the lower 4 bits are STW+
Shift the value of ΔSTW to the right by 1 bit and put 1 in the MSB.
The lower 4 bits and the upper 4 bits of the entered address
Two words are stored sequentially. For example, if
Address 0444₁₆The upper 8 bits of the waveform data in
The location of the lower 4 bits of is address 1222₁₆top of
It is 4 bits, so the address is 0445.₁₆Nitsu
The address is 1222₁₆The lower 4 bits of
become. (4) Envelope data (E1', E2') Envelope data consists of 1 word with 16 bits.
The data format is shown in Table 19.
It is a cage. ΔT is envelope address update
This is the data that determines the interval. S is for envelope
This is a flag indicating the slope (increase or decrease). Z
is a flag indicating the magnitude of the slope of the envelope.
and DATA is its size. Shown in Table 19
The data is determined by STE and ΔSTE shown in Table 16.
stored in the data bank according to the specified address.
ing. The data bank is structured as described above.
gives a change in tone for every three keys next to each other.
On the other hand, within the same octave,
If you have the same header address data
Waveform data, envelope data, header data
You can obtain musical tones with the same timbre without increasing the timbre. Ma
In addition, arbitrary waveform data in each header data,
Envelope data can be specified, so fewer waves can be created.
Even if it is shape data and envelope data,
It is also possible to generate various musical tones by combining them.
It is. Next, the initial sound when the key is pressed in the musical tone generator 1-5 is
dial processing, note clock generation method, envelope
Waveform generation method We will now explain how to generate waveforms. (1) Initial processing During initial processing, musical tones are generated by pressing keys.
Initial settings of various registers are performed when generated.
Ru. The calculation sequence starts from the initial mode by pressing the key.
It starts with a long sequence of codes, so
In the accounting department, PDR first appeared in time slot 13.
period is set. To explain this operation in more detail,
Figure 5: PDD is read from RAM5-4 and HE
Data gets on the bus. At the same time, Fig. 7 signal processor 7
-6, the PED is given to the HD bus, and the first
In Figure 1 A, SW21 and W17 are turned on and PDD
is on the A bus, and PED is on the B bus. This data
Added at FA2-6 shown in Figure 8
The calculation result is placed on the C bus. This calculation result is SW2
Take the HE bus through 3 and find it at RAM5-4.
Stored in register PDR. Note that this calculation
, the actual transfer of PDD and PED to FA2-6 is
The time slot in which the PDD + PED calculation is performed
1 time slot before the PDR of the calculation result.
Storing to is 1 time when PDD + PED calculation is performed.
This is done after the slot. Regarding the addition operation below,
All are similar. Then the time slot
(15) to (18) TR1, TR2, ZR1, ZR2
“0” is written to. This operation is applied to TR1.
Regarding the case of writing “0”, the time
MSW2-11 in Figure 11 A in slot (15)
At this point, SW33 and SW13 are turned on. SW3
3 has the configuration as shown in Figure 11.
“0” is given to the At the same time SW13 is on
Therefore, the data on the C bus is given to the HC bus.
and the register in RAM7-3 shown in Figure 7.
“0” is written to data TR1. On the other hand, in the data bank reading section, the following
It behaves like this. The following explanation focuses on Figure 10.
Ru. By WRD composed of TAB, ND, OCT
The header address data HAD is read out.
Note that the initial mode that performs this initial processing is
In the mode, latch 10-3 is activated by the SQ signal.
It is set to 111. This data is I/O2
Table 15 by shifter 10-13 in -10
The data is converted to the format shown in
RAM7-3 register via bus SW15 and HC bus.
stored in the star HAD. At the same time as this operation,
Header address data read from data bank
Data HAD is latch 10-8, latch 10-6.
They are latched one after another and the shifter selector 10-9
The data is formatted as shown in Table 15.
is switched and latched in latch 10-4. Latsuchi
10-4, first the bit processing circuit 10
-10 gives 000 to the lower 3 bits.
Control data CONT is data bank 1-
6 and latched via latch 10-8.
It is latched to the upper 8 bits of 10-7. Conte
Roll data CONT is selected by selector 10-12,
Lid 10-13, noise circuit 10-14, latch
The register of RAM5-4 is accessed from the D bus via 10-2.
Stored in star CONT. On the other hand, latch 10-
The upper 4 bits of 7 are connected to decoders 10-11.
16 bits according to the truth table shown in Table 14.
You can obtain the following data. However, at this time, decoding
The C input of the data card 10-11 is "1". Se
Rectors 10-12 select this decoder output
Then, shifters 10-13 shift 6 bits to the right and output
Strengthen. Here, the output of this shifter 10-13 is
Considering this, decoder 1 from latch 10-7
The data input to 0-11 is P/O and
ORG3 bits. Now decoder 10-11 C
Since the input is “1”, the decoder 10-11
Output is determined by ORG3 bit only. Therefore de
The output of coder 10-11 is transferred to 6 by shifter 10-13.
The values shifted to the right by bits are the values shown in Table 18.
Ru. This value is the noise circuit 10-14, latch 10
-2 to the D bus, MSW2-11
In the RAM7-3 register via SW15
data is stored in data DIF1. Next, bit processing is performed on the output of latch 10-4.
Circuit 10-10 sets 001 to the lower 3 bits, then
Give 010 to the upper and lower STE of the header data.
8 bits of each position are read out. This STE value is
Rector 10-12, shifter 10-13, noise times
route 10-14, to D bus via latch 10-2
given, through SW5 in MSW2-11
and stored in register EAR1 of RAM7-1. Next, enter the shoot sequence. Shyoto Sea
The kens are executed twice. in time slot (1)
PDR and JD are added, where JD is a constant.
Turn on SW32 in MSW2-11.
It is obtained by SW32 is shown in Figure 11
It is structured like this, JD = 45B₁₆Tonatsutei
Ru. Multiply this addition result by the note coefficient CN.
Combine them to get FR. Describe this series of yen calculations in detail.
Then, PDR + JD is calculated at time slot (1).
The result is placed in time slot (2) as described above.
and is given to the C bus. Now to MSW2-11
SW28 and SW29 turn on, and C bus → HL
Data is transferred in the order of bus → L bus, and
Latch MPLY2-7 in latch 9-1.
be done. In the next time slot (3), Fig.
CN according to note data ND from ROM7-5 of
The value of is read and applied to the HD bus. this
The value is L through SW19 in MSW2-11
Latch 9-3 of MPLY2-7 given to bus
is latched to. The output of latch 9-1 is output from shifter 9
-11 to latch 9-2 to latch 9-3.
The output is sent to latch 9-4 via the bit processing circuit.
and latched. Therefore, Latch 9-2 has PDR.
+JD value is latch 9-4, CN value is latch
It has been checked. Then multiplier 9-16 (PDR
+JD) and CN and output it via shifter 9-15.
The signal is sent to latch 9-8 and latched. In addition
In these series of operations, the shifter 9-11,
The bit processing circuit 9-12 and shifter 9-15 are data
It operates to allow data to pass through. That is, encode
“1” is given to the C input of D9-10.
Ru. The value of latch 9-8 is MSW2-1 from the L bus.
1 to register FR of RAM7-2 via SW9.
Stored. Therefore, in time slot (2),
ORG+OCT+1 is calculated. In this calculation
Therefore, the operation of +1 is according to the logic in FA2-6 in Figure 8.
This is done by gates 8-12. In other words, the corresponding tag
Imslot forces logic gates 8-12
If “1” is output, latch 8-5 will latch “1”.
and gives “1” to the Ci input of the adder.
Ru. The meaning of this operation is as follows.
Ru. In other words, ORG determines which range the waveform data is originally in.
Click the value indicating whether it belongs (let's say this is N)
This is also shown using the reverse logic of Turb Data OCT.
It is. The relationship between OCT and ORG and the number of waveform samples
The details are shown in Tables 18 and 22. Therefore, ORG+1 is -
It will represent N. In other words, ORG+OCT+1=OCT−N That is, this is currently trying to occur.
The tonal range of the musical tone signal and the actual use
The difference between the original range of the waveform data, that is, the octa
This value indicates the amount of shift. In other words, the original waveform
How many octaves higher should the sound be read?
show. This value is temporarily stored in register WE2 of RAM7-4.
and then decoded by the signal processor 7-6.
is written and stored in register ΔWAR of RAM7-2.
It will be done. The value of ΔWAR for the value of ORG + OCT + 1
is shown in Table 20. Below, time slot (4) is EAR2, time slot (6), (8),
(9), (10) WR1, ER1, WE2, WE1, WR2
The initial settings for each register are performed. On the other hand, in the data bank reading section,
The header stored in RAM7-3 with the long sequence
Read the Tsuda address data HAD, D bus →
Through latch 10-1 → shifter selector 10-9
bit processing circuit 1.
Enter 001 in the lower 3 bits of 0-10 to enter the data.
Read the ΔSTE of header data from the bank. child
The value is latch 10-7 → selector 10-12 → switch.
Lid 10-13 → Noise circuit 10-14 → Latch
10-2 to the D bus, MSW2-
A bus via SW26 and SW30 at 11
is input to FA2-6 and added to EAR1.
Ru. Then store in register EAR1 of RAM7-1
STE (envelope data E1′ star)
address) is read out, and the D bus → latch 10
-1→Latch 1 via shifter selector 10-9
Latched at 0-4. The output of latch 10-4 is
“0” is set to LSB by bit processing circuit 10-10.
“1” is then entered and shown in Table 19.
Read the 2-byte envelope data exactly as shown.
put out. This value of 16 bits latches to latch 10-7.
be done. According to the output of latch 10-7, the first
ΔT1, ΔE1, ΔZ1, 2 in short sequence
ΔT2, ΔE2, ΔZ in the second shot sequence
Generates a value of 2. First, to the decoder 10-11
indicates that the upper 4 bits of latch 10-7 are input.
However, the top 4 bits of the latch 10-7 are shown in Table 19.
Contains the value of ΔT shown in . Therefore deco
Readers 10-11 decode ΔT according to Table 13.
and outputs to selector 10-12. Selector 1
At 0-12, at this time C=1 and B input
The force is selected and output to the shifter 10-13. This center
Rector 10-12 output is shifter 10-13, noise
No bit manipulation is performed in the bit circuits 10-14.
to the D bus through latch 10-2 without being
Given, SW10, HB in MSW2-11
Data is stored in register ΔT1 of RAM7-2 via the bus.
will be paid. ΔE1, ΔZ1, ΔE2, ΔZ2 are the 19th
According to Z, S, DATA shown in the table
Bit operations are performed in shifters 10-13, and each record is
stored in the register. What kind of bit operations are performed?
As shown in Figure 13,
Ru. Depending on the value of Z in Table 19, the data format
- indicates that the mats are different. Next, read ΔSTE from data bank 1-6.
As in the case of register HAD from RAM7-3.
Read the value, latch it to latch 10-4, and set the bit.
The header address data is processed by the address processing circuit 10-10.
The first initial mode for the lower 3 bits of HAD.
100, then 101, second initial mode
In the code, set the data by giving 110 and then 111.
Read STW and ΔSTW from tabank 1-6,
STW is the register STW of RAM7-3, ΔSTW is
Store in register WAR of RAM7-1. The above completes the initial settings for all registers.
Complete. (2) How to generate a note clock First, note clock used in musical tone generator 1-5.
Explain the principle of generation of Tsuku with Figure 3.
do. In Figure 3, 3-1 is a frequency divider and
Divide the frequency of the master clock input to the child CK,
A 10-bit frequency divided output is output from Q. 3-2 is
The comparator compares the A input and B input, and A=
When it becomes B, Q outputs "1". 3-3
is a flip-flop, and at the rising edge of the CK input
It takes in the signal given to the D input and outputs it from the Q.
Ru. 3-4 is an adder, which calculates the sum of A input and B input.
is output from C. 3-5 is the B input of adder 3-4.
This is a constant circuit that inputs a constant M for force. 3
-6 is an RS latch, and a positive pulse is applied to the S input.
When it enters, Q=1 and a positive pulse enters the R input.
and Q=0. 3-7 is a delay circuit,
Delays the input signal and outputs it. 3-8 is AND
It is a gate. Next, the operation shown in FIG. 3 will be explained. First, RS Ratu
Assuming that the Q output of Q3-6 is "0",
The output of AND gate 3-8 is always “0”.
The Q output of flip-flop 3-3 is constant.
Ru. On the other hand, the frequency divider uses the frequency division of the master clock.
000₁₆from 3FF₁₆Outputs a 10-bit Q that repeats
Ru. Suppose that the output of flip-flop 3-3 is N.
Of course, if it is 000₁₆≦N≦3FF₁₆Because it is
There will always be a moment when the Q output of frequency divider 3-1 becomes N.
exists, and in this case, the Q output of comparator 3-2 is
A matching pulse is output. Then this matching pulse
Since it is in the S input of RS latch 3-6, RS
The Q output of latch 3-6 becomes “1” and the write pulse
signal is output from AND gate 3-8. pretend
The D input of the pop-flop 3-3 is connected to the adder 3-4.
Since C output is given, the value of N+M is written.
be caught. At the same time, the write pulse is delayed
Q output of RS latch 3-6 after being delayed by circuit 3-7.
Set the force to “0”. For this reason, the flip-flop again
The Q output of 3-3 is constant, but the value varies from N to
It has changed to N+M. Therefore, next is the frequency divider 3-1.
Generates a match pulse when the Q output becomes N+M.
That will happen. By repeating this, the comparison
The output value of the frequency divider 3-1 is N, N+M,
A pulse is generated when N+2M... Two
Therefore, the frequency divider 3-1 counts the master clock M times.
A match pulse will be generated each time the signal is hit.
Also, N+nM>3FF₁₆In the case where
The output of adder 3-4 is N+nM after overflow.
−3FF₁₆In order to
A coincidence pulse is generated when the number of times is counted.
Needless to say. In other words, this comparator 3-2
Use the coincidence pulse as the note clock and change the constant M
You can get notebook clocks with various periods by
Therefore, the frequency is (period of the master clock)
wave number) ÷M. Also, the Q output of SR latch 3-6
The force corresponds to the calculation request flag CLRQ. The above is the notebook clock generation method according to the present invention.
It is the principle. Next, in the musical tone generating section 1-5 shown in FIG.
Details of the calculation sequence for generating a note clock
explain about. A key is pressed on the keyboard 1-1, and the microcomputer 1-4
instructs the musical tone generator 1-5 to generate a musical tone.
, the operation sequence is initialized as described above.
Start with mode long sequence. Thailand first
In Muslot (13), PDD+PED→PDR…(2-1) Next, enter the shoot sequence and time slot.
With Tsuto(1)…(6) PDR＋JD→L.B.…(2-2) C.B.×CN→FR…(2-3) calculations are performed. Then go to normal mode
and in the time slot (9) of the short sequence. FR+CDR→FR…(2-4) Long sequence time slot (14)~
(18) in PDR＋JD→L.B.…(2-5) C.B.×CN→FR…(2-6) PDD+PED→PDR…(2-7) calculations are performed. Here, PDD is shown in Table 1.
PDD, that is, pitch detune data,
PED is the aforementioned pitch extend data.
JD is a constant and 1115_Ten(45B in hexadecimal)
The value has been set. Note coefficient CN is assigned
The value is determined by the pitch name, and the value is determined by the pitch name and CN.
The relationships are shown in Table 7. Theory of Tables 5 and 6
As mentioned above, operations (2-2), (2-3)
And calculations (2-5) and (2-6) are as shown below.
Can be expressed. (PDR+JD)×CN→FR…(2-8) Here, PDR is PDD + PED, so it is calculated
(2-8) is (PDD+PED+JD)×CN→FR ...(2-9) becomes. The value of this FR is shown by calculation (2-4).
Accumulate in CDR. As mentioned above, this accumulation is
Occurs once every time a note clock occurs.
Therefore, if the initial value of CDR is N, the value of CDR is N,
It changes as N+FR, N+2×FR,... this
The upper 10 bits of CDR and the master clock are
Compare the 10-bit frequency-divided signal obtained by the next frequency division,
Since we are trying to generate a matching pulse, the actual
for, Comparison with N/8, N+FR/8, N+2×FR/8,... The top 10 bits of the CDR are the third
Corresponds to flip-flop 3-3 in the figure, and FR/8 is the This corresponds to the value M of the constant circuit 3-5 in FIG. Therefore above
If you perform the calculations (2-1) to (2-7) below, you will get a constant cycle.
The periodic note clock is obtained, and its frequency is (Master clock frequency)÷FR/8. (3) Waveform generation method Waveform generation shown in Figure 1 Musical sound generation section 1-5
The production method can be broadly divided into the following five steps.
Namely: Address generation Read waveform data from data bank 1-6
Generates an address when accessing. Waveform readout Downloads the waveform data specified by the address above.
Read data from data banks 1-6 and control
Performs bit processing according to data CONT. envelope multiplication 2 wave mixing CN multiplication Each step will be explained in detail below. Address generation Header data is initialized by pressing a key.
STW (start address of W2), ΔSTW (W
1 word count), DIF1 (number of samples included in 1 waveform)
number of pulls) is stored in registers STW, WAR, and DIF1.
The register ΔWAR is determined by the calculation.
Ru. In normal mode based on these data
The address is generated, but the following processing
If the waveform data has a PCM part (PCM=
1) and without it (PCM=0), address generation occurs.
They are different, so when there is a PCM part and when there is no PCM
I will explain it separately. If there is no PCM section As shown in Table 6, at time slot (2),
Find the sum of STW and WAR, and use this sum to
Read waveform 1 from data bank 1-6 and
Add DIF1 to the above sum at imslot (4)
In other words, the value of STW + WAR + DIF1 is
Waveform 2 is being read from links 1-6.
Here, STW is the start address of waveform 2,
WAR includes ΔSTW, which is included in waveform 1, as an initial value.
Contains a negative number for the number of words to
ΔWAR is accumulated in step (7). Therefore STW+
The value of WAR is calculated sequentially from the first address of waveform 1.
It is a value that increases with each value of ΔWAR. Also, ST
+WAR+DIF1 value is this value plus DIF1
Therefore, from the start address of waveform 2
It is a value that increases every ΔWAR. here,
ΔWAR is a value representing the reading skip of the waveform
Therefore, as described above, for waveform 1 and waveform 2,
address can be generated. In addition, in the main musical tone generating section 1-5, the PCM
section is absent, solo flag SOL = 0, and
Phase alignment when no quarter shift is performed
conduct. The phase matching method is based on the calculation sequence
When changing from normal mode to normal mode
RAM as the calculation result in the first time slot (7)
Data whose address is the homophone name in 8-13
Store 9 bits in WAR. RAM8-13
The output is 9 bits, but the C bus is precharged.
Therefore, the total 16 bits are smaller than the aforementioned 9 bits.
“1” is entered in the upper 7 bits. After the second time
The calculation results of Imslot (7) are shown in Table 6.
is stored in WAR and also in RAM8-13.
is updated to a register whose address is the homophone name in
It will be done. By doing this, other channel
If a tone with the same note name has already been generated in the
Even if the register WAR in that channel
A musical tone is generated from this value via RAM8-13.
In the register WAR of the channel you are trying to
The phase between these two channels to be given
It becomes possible to match. Here, the calculation of time slot (7) is WAR + △
Let's talk about WAR. When WAR＋ΔWAR≧0, it has nothing to do with the range.
As a result of the operation, -512 is sent to the C bus._Ten(FF00₁₆) is given
available. If there is no octave shift
Since ΔWAR=1, the value of register WAR is
It will repeat with a period of 512. Multiple channels that generate the same note due to the above
The register WAR for each file is always the same.
The same note occurring in different channels
The phases of the waveforms match perfectly, and the phase
alignment is achieved. Next, the calculation STW + in time slot (2)
Let's explain WAR in more detail. Data is read from register STW of RAM7-3.
The HC bar as shown in MSW2-11
by clock φ3 via bus, SW11, and A bus.
It is latched by latch 8-1 of FA2-6. simultaneous
The value of register WAR in RAM7-1 is set to HA bus,
SW2, FA2- by clock ψ3 via B bus
It is latched by the latch 8-2 of No. 6. Latch 8-1
The output of
Latched by clock ψ1 without being subjected to
It is latched at 8-3. On the other hand, the output of latch 8-2
The power is applied to ORG in the bit processing circuit 8-11.
As input, bit processing is performed as shown in Table 21.
After that, it is latched to latch 8-4 with clock ψ1.
It will be done. Adder 8-9 connects latch 8-3 and latch 8-
Add the outputs of 4, latch 8-7, latch 8-8
to the C bus. Bit processing circuit 8
-11, the above bit processing can be performed.
As a result, the register WAR changes with a period of 512.
Despite the fact that it is
It will change at regular intervals. for example,
If ORG=5, OCT=2, octave shift
As mentioned in the initial processing section,
ΔWAR=1. Also, from Table 21, the WAR bit
Since slots 7 and 8 are always 1, the time slot
Assuming STW′=0, the calculation result of (2) is −10, −9,…−1, −128, −127,… −1, −128… Thus, it repeats in 128 cycles. Also,
If ORG=4, OCT=5, octave shift
Therefore, ΔWAR=4. Also, according to Table 21
Bits 6, 7, and 8 of WAR are always 1, so
As -40,...-8,-4,-64,-60,-56... -4, -64,... This means that it repeats in 16 cycles. When OCT=2, the repetition period is 128,
The repetition period is 16 when OCT=5.
The desired waveform points are obtained from Table 22.
It is shown that. Also, when ORG=4 and OCT=5, WAR is 4
As shown in Table 18, the wave
Data with 64 shape samples, 1 point for every 4 samples
By obtaining the octave of the original waveform data
This shows that you can go up two octaves.
Ru. If there is a PCM section If there is a PCM section, address generation is done by the PCM section.
performance in time slot (2) compared to the case without
The calculation is different, but the other things are the same. In time slot (2), the performance of STR + WAR is
calculation is performed. Namely: Data is read from register STW of RAM7-3.
Extracted, via HC bus, SW11, A bus
The clock ψ3 locks the latch 8-1 of FA2-6.
be hit. At the same time, the RAM7-1 register
The value of WAR is transmitted via the HA bus, SW2, and B bus.
It is latched by latch 8-2 of FA2-6. here
The output of the latch 8-1 is sent to the bit processing circuit 8-1.
0, the output of latch 8-2 is sent to bit processing circuit 8-1.
1, but both outputs undergo bit processing.
sent to latch 8-3 and latch 8-4 without being
and are added by an adder 8-9. Now, consider the value of register WAR
If there is no PCM section, register WAR will contain the first
The negative number of samples included in one period of the waveform as a period value.
number is written, but if there is a PCM part,
Used as the PCM part as the initial value of register WAR
A negative number of all samples of the waveform will be written.
Ru. Therefore, the calculation result of time slot (2) is data
PCM part start address of waveform 1 in banks 1-6
The value increases sequentially by ΔWAR from the response.
The end of the PCM section is detected at the time slot (7).
Check that WAR+ΔWAR≧0 in the calculation.
The address generation at the end of the PCM section is done by
It is exactly the same as without the PCM section, and the bit processing
Bit processing is performed by the logic circuit 8-11. In addition, the address calculation in the musical tone generator 1-5
is 16 bits, but the address signal is 16 bits.
Of course, there may be cases where this is not sufficient. So, the book
In the musical sound generation section 1-5, the tablet data
The address space is expanded using the upper 3 bits of TAB.
It is now possible to stretch. to I/O2-10
The latch 10-3 is the latch for address space expansion.
and the tablet data is stored in latch 10-3.
The upper 3 bits of TAB are latched. Namely: When you enter the initial mode by pressing a key, the RAM
The tablet data stored in 5-4 is MSW2
-11 to register TAB' of RAM7-3.
Stored. Then when you enter normal mode,
The value of register TAB' of RAM7-3 is read,
In I/O2-10 via MSW2-11
It is latched by latch 10-3. In this way
Although the internal calculation is 16 bits, the address is 19 bits.
access space. Waveform readout Waveform readout is performed at time slots (2) and (4).
This is done based on the address given. time slot
The calculation result from step (2) is sent to the C bus, SW28, and HL bus.
I/O2-10 via bus, SW30, and D bus.
It is latched by latch 10-1. First, latch 1
0-1 output is shifter selector 10-9, latch
10-4, the bit processing circuit 10-10
Latched by 10-5 and then latched by 10-3
Read data banks 1-6 along with the data
Then, the output of data bank 1-6 is latched 10-8.
is latched to. Then, the output of latch 10-1
is shifted to the right by 1 bit using shifter selector 10-9.
is added, “1” is added to the MSB, and the latch 10-
It is latched at 4. The output of latch 10-4 is bit
to latch 10-5 via gate processing circuit 10-10.
latched, and with the data by latch 10-3.
Read data banks 1-6 to
The output of 1-6 is latched into latch 10-7.
At this time, the upper 8 bits of latch 10-7 are
Since the output of 10-8 is given, the previous data
It is latched with the values in data banks 1-6. child
Now, the lower 8 bits of latch 10-7 are latched.
The data is as described in the data bank section.
Equivalent to 2 words of the lower 4 bits of a 12-bit waveform.
Ru. The output of latch 10-7 is output to selector 10-12.
is applied to shifters 10-13 via
The latch is shifted 4 bits to the right and the latch 10-1
If the LSB of the output is 0, the lower 8 bits are also 4 bits.
If LSB = 1, the lower 4 bits are shifted to the right.
is output from shifter 10-13 without being shifted.
Ru. Here, in the control data CONT
When W8=1, that is, 8-bit waveform is specified,
In this case, shifters 10-13 set the lower 4 bits to “0”.
and output it. The output of shifters 10-13 is noise
D bus via circuit 10-14, latch 10-2
RAM7- through MSW2-11
3 is stored in register WR1. This value is the waveform
1 waveform data. to the address obtained by time slot (4)
The same process will be performed in any case. However, control
If NA=00 in role data CONT
In the noise circuit 10-14, a noise signal is generated.
Added. When AN=01, bit 9 is NA
When = 10, bit 10, when NA = 11, bit
9 and 10 are replaced with noise signals. this
In this way, the noise signal can be superimposed without using an adder.
are doing. This is the waveform data of waveform 2
It is stored in register WR2 of RAM7-2. envelope multiplication Create two types of waves, waveform 1 and waveform 2, as described above.
waveform data was obtained, but for this waveform data
Perform envelope multiplication. En for waveform 1
Perop writes a wave in register ER1 of RAM7-3.
The envelope for shape 2 is stored in the register of RAM7-3.
It's in Star ER2. Here, the envelope
, the envelope has a 4-bit exponent part.
Displays a 13-bit floating point number with a 9-bit mantissa.
It's on. Envelope multiplication is done twice for each channel.
However, each operation is similar, so
Performance of WR1×ER1 in imslots (7) to (9)
Explain about calculation. The data in register ER1 of RAM7-3 is MSW
Latch 9-3 of MPLY2-7 via 2-11
and is latched by latch 9-5. Latch here
9-3 contains the lower 10 bits of register ER1.
Bits 9-12 of register ER1 are set to 9-5.
is latched. Next, register of RAM7-3
WR1 data is MPLY via MSW2-11
It is latched by latch 9-1 of 2-7. Latch 9
The output of -3 is sent to the bit processing circuit 9-12.
The MSB of is set to “1” and latched to latch 9-4.
be done. That is, the latch 9-4 has the envelope
Hypothesis is latched. The output of latch 9-1 is
It is latched to latch 9-2 via lid 9-11.
Ru. At this time, SQ is input to the C input of encoder 9-10.
1 is given by the signal, and the shifter 9-1
00001 is given to the C input of 1. Therefore shifter
9-11 is the lower 12 bits of latch 9-1, that is, data.
Waveform data of waveform 1 read from data bank 1-6
12 bits are sent to latch 9-2. Multiplier 9
-16 is the data of latch 9-2 and latch 9-4
The 14-bit product is held in latch 9-7.
is selected and sent to shifter 9-15. On the other hand, latch 9-5 contains the exponent part of the envelope.
is latched, and dego is connected via latch 9-6.
The selector 9-1 decodes the
4 to the shifter 9-15 as a control signal.
It will be done. Therefore, the output of latch 9-7 is the envelope
shifted by the exponent of the
It will be latched. In this way, fixed-point
Multiplication of waveform data and floating point envelope
It will be done. The output of latch 9-8 is from the L bus.
RAM7-1 register via MSW2-11
Stored in WE1. Waveform data of waveform 2 and encoder
Multiplication of the envelope is done in the same way, RAM7-4
is stored in register WE2. 2 wave mixing As above, registers WE1 and WE2 are
The waveform is stored. In this step, WE1 and
Find the sum of WE2. In time slot (1)
This corresponds to calculation. CN multiplication Two-wave mixing is performed in time slot (1), but the main musical tone
In the generation part 1-5, ABM2-9 and fiber
Depending on the characteristics of routers 1-7, it may occur depending on the note name.
The sound pressure level generated may differ. for this
CN multiplication performs the correction. Correction here and here
Use the note coefficient CN as is as a coefficient for
ing. WE2+WE in time slot (1)
The calculation result of 1 is sent from the C bus to SW28, HL bus,
MPLY2-7 latch via SW29, L bus
It is latched at 9-1. On the other hand, memory 2-5
No from ROM7-5 according to note data ND.
The coefficient CN is read out, and the HD bus, SW24, L
Connect to latch 9-3 of MPLY2-7 via bus.
be hit. Here, WE1+WE2 is 16-bit data.
However, the A input of multiplier 9-16 is 12 bits.
Therefore, in MPLY2-7, perform the following processing.
There is. That is, the upper 5 bits of latch 9-1 are
input to the coder 9-10, and the encoder 9-10
inputs the data shown in Table 9 from both terminals A and B.
output. In other words, the data in latch 9-1
Determine how many bits the data actually has and respond to this result.
12 from latch 9-1 by shifter 9-11.
Take out the bit. For example, if the value of latch 9-1 is
3A26₁₆, this data is effectively 15 bits
Since it is data, shifter 9-11 is latch 9-1.
Take out the 12 bits below bit 14 and use shifter 9.
-11 output is 744₁₆becomes. In this way WE
Multiply the real part of 2+WE1 by the note coefficient.
and the original number of bits is restored by shifter 9-15.
Then, latch with latch 9-9. As described above, a multiplier with a small number of bits can be used.
When performing multiplication on data with a large number of bits.
Ru. The value obtained in this way is sent to DAC2-8.
Output and corrected to the specified cycle by ABM2-9
Output as a musical tone signal. By the way, in the main musical tone generating section 1-5,
As mentioned in Table 1, the instructions from the microcomputer
Switch CN multiplication to VLD multiplication by lag VOL
can be done. That is, in a long sequence
Therefore, the register VLD8 bit of RAM5-6 is
RAM7-4 registers via MSW2-11
Sent to LVD′. MSW2-11 when sending
Bit shift is performed at 8-bit data.
Shifted to the left by 2 bits and further set “0” to the lower 2 bits.
is added and converted to 10-bit data. this
Therefore, the number of bits in VLD is the same as the number of bits in CN.
Become one. The value of ROM7-5 is added to the value of WE2+WE1.
or by the value in register VLD′
The flag VOL in Table 1 determines whether VOL
If = 0, ROM7-5 sends data to the HD bus.
If VOL=1, RAM7-4 becomes HD bus.
Send data. By configuring as above, microcontroller 1
-4, the musical tone generator 1-5 outputs the musical tone signal.
It is now possible to change the level of the issue, and as shown in Table 1.
Amplitude modulation is achieved by sequentially changing the value of VLD.
It becomes possible to At least one of the speed and pressure with which you press the keys.
If you create a VLD based on the touch response device
Noh is realized. What is the touch response function?
The volume, tone, etc. change depending on the strength etc.
Ru. For example, on a piano, the harder you press the keys, the louder the volume.
Not only will the tone be brighter, but the tone will also be brighter, making it easier to hit weakly.
When I key the key, not only is the volume low, but the tone is also muffled.
Become something. The volume and tone change automatically depending on the strength of the keystrokes.
However, in the case of a piano, the keyboard changes after the key is pressed.
Even if you change the force with which you press the button, the sound quality is decreasing
cannot make any changes. Pi like this
In that case, only the strength of the keystrokes is the touch response function.
This feature is especially useful at the initial stage.
It's called Tutsi control. Generally, percussion instruments fall into this category.
belong to On the other hand, the trumpet is connected depending on the strength of the breath.
This sound quality can also be changed.
When playing by imitating the keyboard of an electronic musical instrument
Also, when a key is pressed while a trumpet sound is being generated,
Change the volume and tone by increasing or decreasing the strength
This is necessary. This feature is especially useful after-sales service.
-It's called touch control. Generally, stringed instruments
Wind instruments belong to this category. In the embodiment of the present invention, as described above, VOL
By performing VLD multiplication by the flag, each channel is
The volume can be controlled independently. As an application example, measuring the strength of keystrokes and
Create VLD values accordingly and transfer them from the microcontroller.
Different VLDs transferred for each keystroke
The volume of each sound will change accordingly. When the microcontroller transfers VLD, it responds to the value of VLD.
If you change the tablet data and transfer it, the book
The musical tone generator of the embodiment changes the volume according to the value of VLD.
As mentioned earlier, you can also change the tone.
This is clear from the functional description. Regarding this tone switching, VLD is 8-bit
Let's explain with an example. Table 23 shows the range of VLD values and their corresponding
An example of the strength and weakness name and tablet name is shown below. Every time VLD decreases by 1 bit, the volume decreases by 1/2.
It is 6 dB lower, which is the name of the musical term for dynamics.
assigned to each. Also, the strength is gorgeous
Since we need a tone, we need to tap waveform data rich in harmonics.
Assign this to bullet 0, and at a volume lower than MP.
Waveform data close to a sine wave is required because a mellow tone is required.
to assign multiple types of waves to Tablet 3.
Prepare shape data in a data bank. By doing this, the VLD will change depending on the strength of the keystroke.
At the same time, the tone is switched in four ways within the numerical range of
256 different volumes can be specified depending on the 8-bit VLD.
Wear. The above was the initial touch control.
However, similarly, depending on the amount of pressure on the key after the key is pressed,
and VLD that changes from moment to moment according to the value of VLD.
The microcontroller sends the tablet data to be converted into
The musical tone generator of this embodiment changes the key press pressure after the key is pressed.
The tone and volume can be changed moment by moment according to the
I can do it. The above is aftertouch control. (4) Envelope generation method Envelope generation in musical tone generator 1-5
The method is divided into the following three steps. That is, Address generation Reading envelope data envelope calculation Each step will be explained in detail below. Address generation Header data is set by initial setting by pressing the key.
STE (start store of envelope data E1')
address), ΔSTE (wax of envelope data E1')
registers EAR1, EAR2,
TR1, TR2, ΔT1, ΔT2 are initialized.
There is. Address calculations are performed based on these data.
It will be done. Address calculations are performed infrequently.
It is also possible to use a long sequence of calculation sequences.
I'm going. Furthermore, the odd number of long sequences
Perform address calculation of envelope data E1' by eye,
Address of envelope data E2' at even numbered times
Performing calculations. In the odd numbered long case, the time slot
In Tuto (13) ΔT1+TR1→TR1…(4-1) in time slot (15) ΔEAR1+EAR1+Ci→EAR1...(4-2) calculation is performed and the data bank is created using the value of EAR1.
1-6 is read. time slot
Ci of (15) is done in time slot (13)
This corresponds to the overflow caused by the accumulation of ΔT1.
Ru. Here, calculation (4-1) will be explained in detail. First, the value of register ΔT1 of RAM7-2 is HB.
bus, FA2-6 via MSW2-11
It is latched to the lock 8-1. At the same time, RAM7-3
The value of register TR1 is HC bus, MSW2-11
is latched to latch 8-2 of FA2-6 via
Ru. The output of latch 8-1 is sent to bit processing circuit 8-1.
0 forces bit 3 to “0” (bit
The reason why bit 3 is set to "0" will be explained later. ), Ratu
It is latched at 8-3. The output of latch 8-2 is
latch 8-4 via bit processing circuit 8-11.
Latched. Here, the bit processing circuit 8-11
In this case, processing such as bit conversion is not performed. La
The outputs of the latch 8-3 and the latch 8-4 are sent to the adder 8-
9 and added through latch 8-7 and latch 8-8.
and give it to the C bus via MSW2-11.
Store the addition result in register TR1 of RAM7-3
do. An overflow occurred in the addition result here.
In this case, “1” is output from Co of adder 8-9.
It will be done. This output is latched with latch 8-6, and
It is used when calculating the imslot 15. however,
This is for the case where the waveform data does not have a PCM part.
, and if the waveform data has a PCM part (fragment
(PCM = 1) until the PCM section is read.
Force TR1 to “0” as the calculation result
is input. Therefore, overflow due to accumulation of ΔT1
Finish reading PCM because no flow occurs
The value of EAR1 will not be updated until then. ΔT
1 is shown in Table 13 as mentioned in the initial processing section.
It is the value of the D output when C=0 in the register
TR1 is a 16-bit register, so for example
ΔT1=4000₁₆Then operation (4-1) is performed 4 times
register TR1 overflows and the
Ci of calculation (4-2) becomes 1 and the address is updated.
be exposed. Here, operations (4-1) and (4-2) are
This occurs once every two times in the sequence. Figure 1 C
A long sequence of the same channel as shown in
The period is 388 time slots, i.e. 1 time slot.
Since the lot is 250ns, it appears in a period of 97μs.
Therefore, calculations (4-1) and (4-2) are performed every 194 μs.
, ΔT1=4000₁₆address in 776μs if
The update will be performed. By the way, envelope data consists of 2 bytes.
Since the address has been updated, please update the address by 2.
Must be updated. time slot
In (15), update the address as follows
is going on. First, ΔEAR1 is a value determined by ΔT1.
ΔT1≠0008₁₆When ΔEAR1=0000₁₆in
Yes, ΔT1=0008₁₆When ΔEAR1=FFEB₁₆
=-21_TenIt is. This operation is performed in MSW2-11.
It will be held at SW31. SW31 is shown in Figure 11.
As shown in Figure 3, bit 3 of ΔT1
It is controlled by a flag T0 indicating the value. Temporary now
ΔT1≠0008₁₆Then, the A bus is set by SW31.
0000 to₁₆is from register EAR1 of RAM7-1
HA bus, B bus via SW2 of MSW2-11
is given the value of EAR1. These values are FA2−
It is latched by latch 8-1 and latch 8-2 of 6.
Ru. The output of latch 8-1 is sent to bit processing circuit 8-1.
0 to latch 8-3. Here,
Data conversion is performed in the output processing circuit 8-10.
It seems like there is no such thing. At the same time, latch 8-2
The output is given to the bit processing circuit 8-11, and the data
LSB of data is forced to “1” and latch 8-
Sent to 4. That is, in the bit processing circuit 8-11
1 can be added in advance. In addition, the latch 8-
Overflow due to operation (4-1) stored in 6
-flow is latched in latch 8-5. Therefore, la
Values of latches 8-3, latches 8-4 and latches 8-5
When adding , the value of latch 8-5 is “1”.
If so, “2” will be added to the value of EAR1.
Ru. On the other hand, if the value of latch 8-5 is "0",
The value of EAR1 remains incremented by 1, but
As mentioned in the section on serial processing, I/O2-10
Forcibly give “0” and “1” to the LSB in
Therefore, no inconvenience will occur. By the way, ΔT1=0008₁₆In the case of ΔEAR1
is FFEB₁₆(-21_Ten). Therefore, is it the value of EAR1?
et al21_Ten10 words earlier.
Rope data will be read. This is it
The envelope data address loops.
This resulted in a repeating envelope like a mandolin.
Rope can be raised. First, calculate (4-
In 1), the bit 3 is processed by the bit processing circuit 8-10.
The reason is that bit 3 is set to “0”.
is ΔEAR1=FFEB₁₆This bit is
0008 in register TR1 when performing an operation₁₆Do not add
This is to make sure that it is safe. ΔT2 at even numbered times of long sequence,
Calculate TR2, ΔEAR2, and EAR2 in the same way.
be exposed. Note that the calculations related to EAR1 and EAR2 are completely independent.
Because it is performed vertically, it is completely different from waveform 1 and waveform 2.
It is possible to generate a long envelope signal.
It goes without saying that Also, EAR1 or EAR
Regarding the repetition of 2, if the repetition period is different,
It is easy to tighten, so you can get various effects.
I can do it. Reading envelope data Reading envelope data is a long sequence.
the envelope of waveform 1 on even-numbered times.
the envelope data of waveform 2 at odd-numbered times.
Read data. Performed based on the values of registers EAR1 and EAR2
For information on how to read envelope data, see
This is exactly the same as described in the section on serial processing,
Read from data bank 1-6 at I/O2-10
While converting the format of the captured data,
Register ΔT1, ΔT2, ΔZ1, ΔZ2, ΔE1, ΔE
Store it in 2. envelope calculation By reading the envelope data, ΔZ1,
Data is stored in ΔZ2, ΔE1, ΔE2,
Also, by initial processing, ER1, ER2, ZR1,
An initial value is given to ZR2. to these values
Perform envelope calculations accordingly. The basis of envelope calculation is the time slot of the addition section.
(3), (5), (6), and (8). Time slot (3),
Calculate the envelope of waveform 1 using (5), and
The envelope of waveform 2 is determined by Muslot (6) and (8).
Calculate. Here, Ci of time slots (5) and (8)
is the overflow caused by the operations using time slots (3) and (6).
Although it is a bar flow, at time slots (3) and (6)
How the resulting overflow is time-stamped
Regarding whether it is added by lot (5) or (8), the address
The time slot for occurrence of
It is similar to . ER1 obtained in this way,
The value of ER2 is envelope data. By the way, envelope calculation can be done in various modes.
It's different. What are the various modes? 1 When the waveform has PCM and when it does not.
(PCM=1/0) 2 Case of piano-type envelope and organ-type envelope
For envelopes. (P/O=1/0) 3 When the damper flag is turned on and when it is turned off.
If. (DMP=1/0) There are three types. Each case will be explained below.
Ru. PCM=0 and P/O=0 The initial settings are for ER1, ER2, ZR1, and ZR2.
“0”, and when the key is pressed, the register
The envelope is set according to the values of ΔE1, ΔE2, ΔZ1, ΔZ2.
Perform rope calculations. When the key is released, the times
ΔZ1, ΔE1, ΔZ2 of lot (3), (5), (6), (8),
As the value of ΔE2, the signal processor 5- of UCIF2-3
Release data is generated from 6 and register ΔZ
1, used instead of the values of ΔE1, ΔZ2, ΔE2
It will be done. In addition, in this mode, the damper flag
The calculations are not affected in any way by DMP. PCM=0 and P/O=1 The initial settings are for ER1, ER2, ZR1, and ZR2.
“0”, and when the key is pressed, the register
The envelope is set according to the values of ΔE1, ΔE2, ΔZ1, ΔZ2.
Perform rope calculations. When the key is released, the damp puff
If lag DMP=1, register ΔE1,
Envelope according to the values of ΔE2, ΔZ1, ΔZ2
When the damper flag DMP=0,
This is the same as when PCM=0 and P/O=0. PCM=1 and P/O=0 Initial setting is EA1=1FFF₁₆,ER2=0,ZR
1=0, ZR2=0. The key is pressed,
Initial value when waveform 1 is reading the PCM section
is held, and after reading the PCM part, the register is
The envelope is set according to the values of ΔE1, ΔE2, ΔZ1, ΔZ2.
Perform rope calculations. When the key is released, waveform 1 becomes
UCIF regardless of whether or not the PCM part is read.
Release data by signal processor 5-6 in 2-3
Calculations are performed based on. That is, PCM=0 and
This results in the case of P/O=0. In addition, in this mode, the damper flag
Operations are not affected by DMP. PCM=1 and P/O=1 Initial setting is ER1=1FFF₁₆,ER2=0,ZR
1=0, ZR2=0. Damper flag DMP=
If it is 0, the key release time will be set once the key is pressed.
The calculation is performed regardless of the That is, waveform 1
When reading the PCM section, the register ER
1, ER2, ZR1, ZR2 retain their initial values,
After reading the PCM part, registers ΔE1, ΔE2,
Calculation is started according to the values of ΔZ1 and ΔZ2. da
If the amplifier flag DMP=1, PCM=1 and
This is exactly the same as when P/O=0. As mentioned above, you can use it freely depending on the various modes.
can generate an envelope signal. Ma
In addition, ΔE1, ΔZ1 and ΔE2, ΔZ2 are set completely independently.
The data can be specified in the address generation section.
In the time determined by ΔT1 and ΔT2,
Since it is updated, it is combined with the two types of waveform data mentioned above.
Various musical tones can be generated. (Effect of the invention) As described above, the present invention allows the instrument to be pressed in advance by pressing a key.
Make a note of the first waveform that records the rise of the sound.
and repeatedly read the last waveform.
The first waveform and the second waveform are independent of each other.
Multiply the envelopes and add things together
Since we are trying to make it a musical sound, it is similar to the sound of natural instruments.
Subtle changes in the rising part are repeated in the steady part.
Because it is possible to express the timbre after the onset of the musical note,
can be prevented from becoming monotonous.

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Claims (1)

[Scope of Claims] 1 Waveform data of multiple cycles of the rising part of the musical instrument sound is defined as a first waveform, waveform data of one cycle of the stationary part of the musical instrument sound is defined as a second waveform, and the time of the volume corresponding to the first waveform is defined as a first waveform. The change characteristic is a first envelope, the first envelope is parameterized as a first parameter, the time change characteristic of the volume corresponding to the second waveform is a second envelope, and the second envelope is parameterized. When there are two parameters, there is a data bank that stores the first waveform, second waveform, first parameter, and second parameter, and a data bank that reads the first and second parameters from the data bank. an envelope forming means for restoring the first envelope and the second envelope; and an envelope forming means that sequentially reads out the first waveform from the data bank and repeatedly reads out the last cycle of waveform data of the plurality of cycles of waveform data of the first waveform to restore the first envelope and the second envelope. means for multiplying to create first data; means for sequentially and repeatedly reading a second waveform from a data bank and multiplying it by a second envelope to create second data; and adding the first data and second data. What is claimed is: 1. An electronic musical instrument comprising: means for creating musical tone data using a musical instrument, and is characterized in that musical tones of different tones are added to the final waveform of the rising portion of the musical instrument sound to prevent the tone of the steady portion from becoming monotonous. 2 The first envelope and the second envelope are polygonal lines on coordinates where the time axis is linear and the volume axis is exponential, and the first and second parameters themselves have the time length of the polygonal line. The envelope forming means counts the time length of the first parameter and the time length of the second parameter, and reads the next data of the corresponding one of the first parameter and the second parameter from the data bank at each end point of the time length. An electronic musical instrument according to claim 1, characterized in that the electronic musical instrument comprises: