JPH023218B2 - - Google Patents

Description

[Detailed Description of the Invention] Technical Field of the Invention The present invention relates to a small office machine etc. equipped with a liquid crystal display, and in particular uses two basic clock signals having different frequencies by switching between displaying and arithmetic processing. This invention relates to a digital circuit that generates basic signals used to drive a liquid crystal display.

Technical Background of the Invention In small office equipment etc. equipped with a liquid crystal display, the frequency of the basic clock signal is kept low during display on the display to reduce current consumption and extend battery life, and during arithmetic processing. In order to speed up the processing speed, the frequency of the basic clock signal is set to a high state. In other words, the basic clock signal is switched and used during display and during calculation processing.
The effect of reducing current consumption and increasing processing speed will be greater if the ratio between the frequency being displayed and the frequency being processed is increased. Conventionally, the basic signal used to drive the liquid crystal display is obtained by dividing the two basic clock signals having different frequencies at a constant frequency division ratio.

Problems with the Background Art As mentioned above, in the past, the basic signal used to drive the liquid crystal display was obtained by dividing two basic signals with different frequencies at a fixed frequency division ratio. , the frequency of this basic signal is different during display and during arithmetic processing. On the other hand, the frame frequency at which the display contrast of the LCD display is best maintained is limited to a certain range, approximately 50Hz to 200Hz. Devices that require constant display have the disadvantage that the display contrast of the display deteriorates during arithmetic processing, and in the worst case, the display becomes almost invisible.

Purpose of the Invention Therefore, the purpose of the present invention is to switch and use two basic clock signals having different frequencies during display and during calculation processing, and to provide a display using a liquid crystal display during calculation processing. It is an object of the present invention to provide a digital circuit that has a high display contrast on a display device and can always display clearly even when the display is low.

Summary of the Invention In the digital circuit of the present invention, a ring counter circuit having two frequency division ratios is constructed by cascading multiple stages of binary counters and providing two feedback paths. Two basic clock signals with different frequencies that are switched during arithmetic processing are applied, and one input terminal of each gate is connected to the output of the binary counter of any stage mentioned above or the output of the binary counter of one or more stages. One switching gate circuit, to which an output is given and the other input terminal is given a control signal for switching each state during display and arithmetic processing, is inserted in the middle of the feedback path of the ring counter circuit. By switching a pair of switching gate circuits in response to the above control signal, the frequency division ratio in the ring counter circuit is selected in accordance with the frequency of the basic clock signal, and a constant frequency is always output from the ring counter circuit. It is designed to obtain a signal of

Embodiments of the Invention Examples of the invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram illustrating the configuration of a small gaming office machine in which a digital circuit according to the present invention is implemented.

Reference numeral 1 denotes an arithmetic processing circuit that performs various calculations and generates segment signals for display, and the segment signals generated here are applied to the display device 2.

Reference numeral 3 denotes a keyboard, from which key signals corresponding to key switches operated are applied to the arithmetic processing circuit 1.

Reference numeral 4 denotes a CR oscillation circuit composed of an inverter, a capacitor, and a resistor, which generates a basic clock signal CP1 of high frequency, for example, 200kHz, used during the arithmetic processing of the arithmetic processing circuit 1. The basic clock signal CP1 generated at 4 is applied to one input terminal of AND gate 5.

6 generates a basic clock signal CP2 of a low frequency, for example, half the frequency of CP1, that is, 100 kHz, used during display on the display device 2;
This is a crystal oscillation circuit composed of an inverter, a crystal resonator, a resistor, and a capacitor, and a basic clock signal CP2 generated by this oscillation circuit 6 is applied to one input terminal of an AND gate 7.

The other input terminal of the AND gate 5 is connected to a switching control signal L which is output from the arithmetic processing circuit 1 and synchronized with the switching of each state during display and arithmetic processing.
is applied via an inverter 8, and this control signal L is applied directly to the other input terminal of the AND gate 7. And the output of both AND gates 5 and 7 is
It is applied to a counter 10 via an OR gate 9. That is, the clock signals CP1 and CP2 are switched by the AND gates 5 and 7, and one of the clock signals CP1 and CP2 is applied to the counter 10 in accordance with the control signal L.

The counter 10 generates a pair of signals φ ₁ and φ 2 having mutually different phases and their opposite phase signals ₁ and ₂ by frequency-dividing the basic clock signal CP1 or _CP2 applied via the OR gate 9. . The signals φ ₁ and φ ₂ are supplied to the arithmetic processing circuit 1 as driving signals, and the signals φ ₁ , φ ₂ and ₂ are supplied to the liquid crystal drive signal generation control circuit 1.
given to 1.

The switching control signal L is also given to the liquid crystal drive signal generation control circuit 11, and this circuit 11 selects one of two preset frequency division ratios of the internal counter according to the switching control signal L. By selecting , a signal φ _L of a constant frequency is generated. The signal φ _L generated here is applied to the display device 2. The display device 2 divides the frequency of this signal φ _L to generate a number of common signals corresponding to the duty of the internally provided liquid crystal display, and uses these common signals and the segment signals to display a predetermined display. will be done.

FIG. 2 is a circuit diagram specifically showing the liquid crystal driving signal generation control circuit. 21-24 in the figure
are the outputs of each D-type flip-flop, respectively.
(Data) This is a binary counter configured by feeding back to the input terminal, and the output of the previous stage is connected in cascade so that it becomes the clock input of the latter stage, and the signal ₂ is used as the clock input of the binary counter 21 of the first stage. is given. Further, the Q output Q ₄ of the final stage binary counter 24 is applied to one input terminal of an AND gate 26 via an inverter 25 . The above first stage binary counter 21
Q output _Q1 and second stage binary counter 2
The two Q outputs Q ₂ are both coupled to a NAND gate 27 , and the output A of this NAND gate 27 is applied to one input terminal of an AND gate 28 .

Further, in FIG. 2, two clocked inverters 29 and 30 and one inverter 31 constitute a latch circuit 32 that latches the signal L, and the signal latched here is sent to the other input terminal of the AND gate 28. Directly given as well as inverter 3
3 to the other input terminal of the AND gate 26.

The output C of the AND gate 26 and the output B of the AND gate 28 are given to a NOR gate 34,
The output D of this NOR gate 34 is applied to a clocked inverter 35 which receives the signal _φ1 as a clock input. The output of the clocked inverter 35 is:
The clocked inverter 36 receives the signal φ ₂ as its clock input, and the output E of the clocked inverter 36 is applied to one input terminal of the clocked inverter 37 and the NOR gate 38, which receives the signal φ ₁ as its clock input. given to. The output of the clocked inverter 37 is given to an inverter 39, and the output F of this inverter 39 is
It is applied to the other input terminal of NOR gate 38 and one input terminal of NAND gate 40. The output of the NOR gate 38 is given to an inverter 41, and the output G of this inverter 41 is applied to the binary counter 2.
It is given to each reset input terminal of 1 to 24. Further, the signal φ ₂ is applied to the other input terminal of the NAND gate 40, and the output of the NAND gate 40 is applied to the inverter 42. The output of the inverter 42 is then given to the display device 2 as the signal φ _L.

That is, the circuit shown in FIG. 2 includes four stages of cascade-connected binary counters 21 to 24, and two feedback paths to the reset input terminals of each binary counter, namely an inverter 25 and a NOR gate 3.
4. A path consisting of clocked inverters 35, 36, clocked inverter 37, inverter 39, NOR gate 38, and inverter 41 and NAND
Gate 27, NOR gate 34, clocked inverters 35, 36, clocked inverter 37,
A ring counter circuit is formed by the inverter 39, the NOR gate 38, and the inverter 41, and by inserting a pair of AND gates 26 and 28 in the middle of each of the feedback paths, the ring counter circuit is One of the two frequency division ratios is selected. When a high frequency value is input as _φ2 , a large frequency division ratio is selected, and when a low frequency value is input, a small frequency division ratio is selected.

FIG. 3 is a configuration diagram of an example of a liquid crystal display provided in the display device 2 in FIG. 1. This display is constructed by arranging 32 unit elements in the vertical direction and 64 unit elements in the horizontal direction in order to play the game, and the duty of this display is the number of unit elements arranged in the vertical direction, In other words, it is 32.

Next, the operation of the circuit configured as described above will be explained in the fourth section.
This will be explained using the time chart shown in the figure. Note that the explanation will be based on negative logic in which a low level is logic 1 and a high level is logic 0. Also, C.P.
The ratio of the frequencies of CP1 and CP2 is assumed to be 2:1, and the ring counter will be explained using a frequency-dividing counter of 10 and a frequency-dividing counter of 5.
First, when performing arithmetic processing from the arithmetic processing circuit 1, this circuit 1 outputs a logic 0, that is, a high level switching control signal L. When the logic 0 signal L is input to the AND gate 5 via the inverter 8, the AND gate 5 is opened, and the high frequency basic clock signal CP1 is input to the counter 10 via the OR gate 9. Basic clock signal above
When CP1 is input, the counter 10 receives this signal CP
1 is frequency-divided to produce signals φ ₁ and φ ₂ with mutually different phases and these opposite phase signals ₁ and ₂ as shown in FIG.
Output sequentially. Therefore, at this time, the signals φ ₁ and φ ₂ are input to the arithmetic processing circuit 1, and as a result,
In the circuit 1, arithmetic processing is performed at a high processing speed.

On the other hand, when displaying using the display device 2,
The arithmetic processing circuit 1 outputs a logic 1, that is, a low level switching control signal L. The above low level signal L is
This AND by inputting to AND gate 7
Gate 7 opens and now the basic clock signal CP2
is input to the counter 10 via the OR gate 9. When the above basic clock signal CP2 is input,
The counter 10 divides the frequency of this signal OP2 to obtain a fourth
As shown in the figure, the signals φ ₁ and φ ₂ have different phases from each other.
Then, these reverse phase signals ₁ and ₂ are sequentially output.
Therefore, at this time, the signals φ ₁ and φ ₂ having half the frequency as described above are inputted to the arithmetic processing circuit 1, and as a result, the arithmetic processing circuit 1 achieves a reduction in current consumption.

Furthermore, the signals φ 1 and φ ₁ input to the arithmetic processing circuit 1,
Signals φ _{1 ,} φ ₂ , ₂ having the same frequency as φ 2 are input to the liquid crystal driving signal generation control circuit 11 . When the switching control signal L is logic 0, the output of the latch circuit 32 is at a high level, so the AND gate 26 is opened.
AND gate 28 is closed. As a result, the Q output _Q4 of the final stage binary counter 24 among the four stages of cascade-connected binary counters is transferred to the inverter 2.
5, is applied to two stages of clocked inverters 35 and 36 via an AND gate 26 and a NOR gate 34. Then, the output D of the NOR gate 34 is
The signal E is delayed by one bit of φ ₁ and φ ₂ by the two stages of clocked inverters 35 and 36, and this signal E is further passed through the clocked inverter 3.
7 and inverter 39, the signal F is further delayed by one bit. On the other hand, the four-stage binary counters 21 to 24 are reset by the output G of the inverter 41, which becomes low level at the same timing as the signal E.
24 is a decimal ring counter for the signal ₂ , and when the signal ₂ is divided by 10, it is reset and starts dividing the signal ₂ again.

Since the signal F has a logic with the signal φ ₂ in the NAND gate 40, the signal φ _L output from the inverter 42 has a pulse width equal to φ ₂ and is a signal obtained by dividing the frequency of φ ₂ by 10.

Next, when the level of the switching control signal L output from the arithmetic processing circuit 1 is logic 1, the latch circuit 32
Since the output of is at a low level, the AND gate 28 is opened and the AND gate 26 is closed. As a result, the Q output of the first stage binary counter 21
Output A of the NAND gate 27 to which Q ₁ and the Q output Q ₂ of the second stage binary counter 22 are combined.
is applied to two stages of clocked inverters 35 and 36 via AND gate 28 and NOR gate 34. And a 4-stage binary counter 21-2
4 is reset by the signal G, which goes low at the same timing as the output E of the clocked inverter 36, as described above, so the four-stage binary counters 21 to 24 perform a quinary ring function with respect to the signal ₂ . It becomes a counter, and when the signal ₂ is divided by 5, it is reset and starts dividing the signal ₂ again.

In addition, the signal D is transmitted to the two-stage clocked inverter 3.
5 and 36, the signal E is delayed by 1 bit of φ ₁ and φ ₂ , and this signal E is further delayed by 1 bit by the clocked inverter 37 and inverter 39, resulting in the signal F. Signal F
is logically connected to the signal φ ₂ in the NAND gate 40, so the signal φ _L output from the inverter 42 has a pulse width equal to φ ₂ and a frequency of φ ₂ by 5.
It becomes a frequency-divided signal.

In this manner, when the arithmetic processing circuit 1 performs arithmetic processing and when the display device 2 performs display, the liquid crystal drive signal generation control circuit 11 outputs a signal φ _L having the same frequency. Therefore, unlike in the past, the frequency of φ _L during arithmetic processing does not differ from that during display, so even when displaying during arithmetic processing, the display contrast on the display is simply displayed without performing arithmetic processing. The price can be increased in the same way as when doing .

Furthermore, as shown in Fig. 3 above, the duty is 32
When driving a liquid _crystal display of
~COM32 is created. At this time, the frame frequency is φ _L /32, which is the best frequency 50Hz mentioned above.
It can be set to a value within the range of ~200Hz.

Note that the present invention is not limited to the above embodiment, and the frequency division ratio of the ring counter circuit in FIG. 2 is not limited to the above-mentioned values, but can be set to various values as necessary. Needless to say, it is only necessary that the frequency of the signal φ _L during display and arithmetic processing matches the frame frequency of the liquid crystal display.

Effects of the Invention As explained above, according to the present invention, two basic clock signals having different frequencies are switched and used during display and arithmetic processing, and display is performed on the liquid crystal display during arithmetic processing. It is possible to provide a digital circuit that can increase the display contrast of a display device and always provide clear display even when the display is

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a configuration when a digital circuit according to the present invention is implemented in a small game office machine, and FIG. 2 is a circuit diagram specifically showing the liquid crystal drive signal generation control circuit in FIG. 1. , FIG. 3 is a block diagram of a liquid crystal display provided in the display device shown in FIG. 1, and FIGS. 4 and 5 are time charts for explaining the operation of the above embodiment circuit, respectively. 1... Arithmetic processing circuit, 2... Display device, 3...
Keyboard, 4...CR oscillation circuit, 5, 7...
AND gate, 6...Crystal oscillation circuit, 8...
...Inverter, 10...Counter, 11...Liquid crystal drive signal generation control circuit, 21-24...Binary counter, 25, 33, 39, 41, 42...
Inverter, 26, 28...AND gate, 27,
40...NAND gate, 32 ...Latch circuit,
34, 38...NOR gate, 35, 36, 37
...Clocked inverter.

Claims (1)

[Scope of Claims] 1. A liquid crystal display device equipped with a clock pulse supply source equipped with a control means for changing the clock frequency, a liquid crystal display element that performs display using a common signal and a segment signal, and when not in operation. A clock pulse with a low frequency within the operable range of the liquid crystal display element is supplied from the clock pulse supply source, and a clock pulse with a high frequency within the operable range of the arithmetic processing circuit element during operation is supplied from the clock pulse supply source to generate the segment signal. When the arithmetic processing circuit is not in operation, the low frequency clock pulse is supplied from the clock pulse supply source, and when the arithmetic processing circuit is in operation, the high frequency clock pulse is supplied from the clock pulse supply source, regardless of the input clock frequency. A basic signal that always generates a signal with a constant frequency that is low within the operable range of the liquid crystal display element, and supplies this signal to the liquid crystal display device as a basic signal for generating a common signal used in the liquid crystal display device. A digital circuit characterized by comprising a generator circuit.