JPH0232811B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to signal generators, and particularly to signal generators configured in ICs and LSIs.

Conventional configurations and their problems In recent years, ICs and LSIs with built-in complex circuits that generate and control multiple and diverse signals have become necessary, and the signal speed and timing must also be high-speed and highly accurate. is required.

FIG. 1 shows the configuration of a conventional signal generator. 1a
1b is a second address generation section that generates a second address signal; 2a is a first address generation section that is connected to the first address generation section 1a and outputted; a first address decoder section 2b that decodes the address signal of
3a is a second address decoder section that is connected to the second address generation section 1b and decodes the output second address signal; 3a is connected to the first address decoder section 2a and is designated by the first decode signal. A first read-only memory data cell section (hereinafter referred to as the first ROM data cell section), which outputs data according to the value written in the cell to be read, is connected to the second address decoder section 2b, and the first read-only memory data cell section (hereinafter referred to as the first ROM data cell section) A second read-only memory data cell section (hereinafter referred to as the second ROM data cell section) outputs data according to the value written in the cell specified by the decode signal 4; The read data output by the ROM memory data cell section 3a and the second
A mixer 5 is an output signal line of the mixer 4, which mixes the read data output from the ROM memory data cell section 3b.

The operation of the conventional signal generator configured in this way will be explained.

The first address generation section 1a and the second address generation section 1b generate address signals while transitioning in a predetermined order, and output the address signals to the first address decoder section 2a and the second address decoder section 2b. . The first address decoder section 2a and the second address decoder section 2b each decode the address signal, and the first ROM data cell section 3a,
Decode signals serving as cell selection signals are respectively output to the second ROM data cell section 3b. The first ROM data cell section 3a and the second ROM data cell section 3b each select a cell according to the decode signal and output a signal corresponding to the data value written in the cell to the mixer 4, respectively. The mixer 4 receives and mixes one or more output signals from the first ROM data cell section 3 a and the second ROM data cell section 3 b and outputs the mixed signal to the output signal line 5 . The signal output to the output signal line 5 is based on the address generation order and the first or second ROM data cell section 3.
Since it is determined by the data written in ROM data cells 3a and 3b, if you encode the signal you want to generate and write it in advance to the first or second ROM data cell part 3a or 3b, you can simply generate the address. You can get a signal that

However, in the above configuration, if the distance between the first ROM data cell section 3a and the mixer 4 is different from the distance between the second ROM data cell section 3b and the mixer 4, the output signal line of the mixer 4 5, there is a possibility that the output cannot be obtained at the correct timing. In particular, the first address generator 1a
In the case where the second address generating section 1b makes transitions using different clocks, the propagation delay time from the first address generating section 1a to the output signal line 5 and the time from the second address generating section 1b to the output signal line 5 are There may be a difference in delay propagation time. The propagation delay time occurring in the first address generation section 1a, the first address decoder section 2a, and the first ROM data cell section 3a is the same as that between the second address generation section 1b and the second address generation section 1b.
Since the propagation delay times occurring in the address decoder section 2b and the second ROM data cell section 3b are almost equal, the difference in the propagation delay time is
Data cell section 3a, second ROM data cell section 3
b and mixer 4. When a signal generator with the above configuration is configured in an IC or LSI, the first and second
The difference in propagation delay time becomes large due to the circuit delay between the ROM data cell sections 3a and 3b and the mixer 4, and the capacitance and resistance of the wiring. The larger the physical size of the first and second ROM data cell sections 3a and 3b, the larger the number of ROM data cell sections (not shown in the figure) in addition to the first and second data cell sections 3a and 3b. ) is mixed, the spatial distance between the first and second ROM data cell sections 3a, 3b and the mixer 4 becomes longer, a propagation delay time difference occurs, and the necessary signals cannot be generated correctly. It has its drawbacks.

OBJECTS OF THE INVENTION An object of the present invention is to provide a signal generator that can eliminate propagation delay time differences and correctly generate required signals.

Structure of the Invention The signal generator of the present invention includes a first address generation section that generates a first address signal, and a first address decoder section that is connected to the first address generation section and decodes the output address signal. a second address generation section that generates a second address; a second address decoder section that is connected to the second address generation section and decodes the output address signal; 2 address decoder section and outputs data specified by a first decode signal output from the first address decoder section and a second decode signal output from the second address decoder section. It is composed of a dedicated memory data cell section and a mixer that combines and outputs read data output from the read-only memory data cell section.

Further, the signal generator of the present invention provides a first clock signal between the mixer and the output of the read-only memory data cell section to which data specified by the first decode signal of the first address decoder section is output. A second latch that operates at A second latch operated by the clock is inserted to obtain an output synchronized with the first clock or the second clock.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of a signal generator in one embodiment of the present invention. 11a is a first address generation section that generates a first address signal; 11b is a second address generation section that generates a second address signal;
12a is a first address decoder section that is connected to the first address generation section 11a and decodes the output first address signal; 12b is a second address signal that is connected to the second address generation section 11b and outputted. A second address decoder section 13 is connected to the first address decoder section 12a and decodes the data corresponding to the value written in the cell specified by the first decode signal, and the second address decoder section 13 is connected to the first address decoder section 12a. a read-only memory data cell section (hereinafter referred to as a ROM data cell section) connected to the section 12b and outputting data according to the value written in the cell specified by the second decode signal;
A mixer 14 mixes read data output from the ROM memory data cell section 13.

Further, 21 is a first address line of the first address generating section 11a, and 22 is a first address line of the second address generating section 1.
1b is the second address line, 23 is the decode line of the first address decoder section 12a, 24 is the decode line of the second address decoder section 12b, and 25 is the decode line of the second address decoder section 12b.
A data line 26 of the ROM data cell section 13 is an output signal line of the mixer 14.

The operation of the signal generator of this embodiment configured as described above will be described below.

First, the first and second address generators 11
The addresses output from a and 11b to address lines 21 and 22 are decoded by first and second address decoders 12a and 12b, respectively, and the outputs are sent as decode signals to first and second decode lines 23, 24 respectively. The ROM data cell section 13 includes first and second
It receives the decode signal output to the decode lines 23 and 24 of the ROM data cell, selects the cell by using the decode signal as a selection signal of the ROM data cell, reads out the data, and outputs it to the data line 25. The mixer 14 synthesizes the data outputs of the data lines 25 to create a necessary output signal, and outputs it to the output signal line 26. Since the signal output to the output signal line 26 is determined by the address generation order and the data written to the ROM data cell section 13, the signal to be generated must be encoded and written to the ROM data cell section 13 in advance. If you do this, you can obtain the required signal just by generating an address.

The signal generator of this embodiment, which operates as described above, will be explained in more detail with reference to FIGS. 3 to 5.

3 is a detailed view of the main parts showing a part of FIG. 2 in detail, FIG. 4 is an explanatory diagram of the data cell showing the cells of the ROM data cell section 13, and FIG. FIG. 3 is a main part waveform diagram showing waveforms.

In FIG. 3, 21a and 21b are address lines of the first address generation section 11a, and 22a and 22
b is an address line of the second address generation section 11b;
23a, 23b, 23c, 23d are decode lines of the first address decoder section 12a; 24a, 24
b, 24c, 24d are decode lines of the second address decoder section 12b; 25a, 25b, 25c,
25d, 25e, 25f are ROM data cell section 1
Data lines 3, 26a, 26b, and 26c are output signal lines of the mixer 14, 14a, 14b, and 14c are gates forming the mixer 14, and 27 is one of the data cells forming the ROM data cell section 13.

As shown in FIG. 4, the data cell 27 shown in FIG. 4a is composed of a transistor 28, for example, as shown in FIG. 4b. The basic operation of the signal generator configured as shown in FIG. 3 is the same as the operation shown in FIG. 2 described above, but the ROM data cell section 13 will be explained in more detail using FIGS. do. The decode signals output from the first and second address decoder sections 12a and 12b are transmitted through decode lines 23a, 23b, 23c, and 23.
via d, 24a, 24b, 24c, 24d
It is transmitted to the ROM data cell section 13, and the data line 2
If there is a data cell 27 at the intersection with the data lines 5a to 25f, the logic level is set to "0" (or "1"), and if there is no data cell 27 at the intersection, the logic level is set to "1" (or "0") to the data lines 25a to 25f. Output to. For example, in the ROM data cell section 13 in FIG. 3, the data line 25a is connected to the decode line 23b and the decode line 23
This is an example in which the data cell 27 exists only at the intersection of the data line 25b and the decode line 24c, and the data cell 27 exists only at the intersection of the decode line 24c and the decode line 24d.
If the address lines 22a and 22b output signals at different timings, for example, the data line 25a and the data line 25b output signals at different timings, and the output signal line 26a of the mixer 14 outputs these combined signals. Ru. (As shown in FIG. 5.) However, since the data line 25a and the data line 25b of this ROM data cell section 13 are structurally arranged adjacent to each other, it is possible to wire the data line 25b with the same length and short. can. Therefore,
The difference in time delay between the two becomes small, and an output signal outputted to the output signal line 26a can also be obtained with a small delay.

As described above, according to this embodiment, by reducing the number of ROM data cell sections from a plurality to one and arranging the data lines output at different timings adjacently, the delay time of the plurality of data lines and the difference in delay time are reduced. signals can be obtained and the required signals can be generated at the correct timing.

Further, the first address generating section 11a is operated with the first clock, the second address generating section 11b is operated with the second clock, and the first address generating section 11a is operated with the first clock.
A first latch operated by the first clock is inserted between the mixer 14 and the output of the ROM data cell section 13, which outputs the data specified by the first decode signal of the address decoder section 12a. The output of the ROM data cell unit 13 and the mixer 14 output the data specified by the second decode signal of the second address decoder unit 12b.
By inserting a second latch operated by the second clock between the two clocks, it is possible to obtain an output synchronized with the first clock or the second clock on the output signal line 26, which is the output of the mixer 14. Can be done.

In the above embodiment, a signal generator configured using two sets of an address generation section and an address decoder section was explained as an example, but the signal generator is not limited to two sets and may be configured using more sets. The advantage of the signal generator according to the present invention becomes more apparent when a large number of sets are used.

Effects of the Invention As described above, according to the present invention, there is a first address generation section that generates a first address signal, and a first address that is connected to the first address generation section and decodes the output address signal. a decoder section;
a second address generation section that generates a second address; a second address decoder section that is connected to the second address generation section and decodes the output address signal; The read-only device is connected to the address decoder section and outputs data specified by the first decode signal output by the first address decoder section and the second decode signal output by the second address decoder section. It consists of a memory data cell section and a mixer that combines and outputs read data output from the read-only memory data cell section, and outputs the first decoded signal of the first address decoder section at different timings. Therefore, a data line for reading specified data from the read-only memory data cell section and outputting it to the mixer, and a read-only memory data cell section for reading the data specified by the second decode signal of the second address decoder section. By arranging the data lines read from and output to the mixer adjacent to each other, an excellent effect can be obtained in that the delay time and delay time difference between the plurality of data lines can be minimized.

Further, the signal generator of the present invention includes a first signal generator between the mixer and the output of the read-only memory data cell section to which data specified by the first decode signal of the first address decoder section is output. A second latch operated by a clock is inserted between the mixer and the output of the read-only memory data cell section, which outputs the data designated by the second decode signal of the second address decoder section. By inserting a second latch that operates with the second clock and configuring it to obtain an output that is synchronized with the first clock or the second clock, the output signal line that is the output of the mixer has the first This has the advantage of being able to obtain a signal that is synchronized with the clock or the second clock and has the minimum delay time and delay time difference between a plurality of data lines.

As a result, in a case where the length of the wiring is greatly affected by the amount of delay, it is possible to minimize the delay time and the delay time difference.
For example, in ICs, LSIs, etc., by incorporating the signal generator of the present invention into the ICs, LSIs, etc., it is possible to achieve the effect that they can be operated at high speed or designed with a margin.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional signal generator, FIG. 2 is a block diagram of a signal generator in an embodiment of the present invention,
3 is a detailed view of the main part of FIG. 2, FIG. 4 is an explanatory diagram of a data cell, and FIG. 5 is a waveform diagram of the main part of FIG. 11a...first address generation section, 11b...
Second address generation section, 12a...first address decoder section, 12b...second address decoder section, 13...ROM data cell section, 14...mixer, 21a, 21b...first address signal lines, 22a, 22b...second address signal lines,
23a, 23b, 23c, 23d...first decode signal line, 24a, 24b, 24c, 24d...
...Second decode signal line, 25a, 25b, 25
c, 25d, 25e, 25f...data line, 26
a, 26b, 26c...output signal lines.

Claims (1)

[Scope of Claims] 1: a first address generation section that generates a first address signal; a first address decoder section that is connected to the first address generation section and decodes the output address signal; a second address generation section that generates a second address signal; a second address decoder section that is connected to the second address generation section and decodes the output address signal; the first address decoder section and the first address decoder section; a first decode signal connected to a second address decoder section and output from the first address decoder section;
a read-only memory data cell unit that outputs data specified by a second decode signal output by the address decoder unit of the address decoder unit; and a mixer that combines and outputs the read data output from the read-only memory data cell unit. a data line for reading data specified by the first decode signal from the read-only memory data cell section and outputting it to the mixer; A signal generator having a data line arranged adjacent to the data line for reading designated data from the read-only memory data cell section and outputting the data to the mixer. 2. A first latch operated by the first clock is inserted between the mixer and the output of the read-only memory data cell section to which data specified by the first decode signal is output, and the second latch is operated by the first clock. A second latch operated by a second clock is inserted between the mixer and the output of the read-only memory data cell portion to which data specified by the decode signal is output, and the second latch is operated by the second clock. 2. The signal generator according to claim 1, wherein the signal generator is configured to obtain an output synchronized with a clock of 2.