JPH023540B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-speed, high-performance field effect transistor operating in the microwave region.

Field effect transistors (GaAsFETs) using GaAs have a large cut-off frequency, and have excellent low noise and high gain performance in microwave applications.
Widely used. On the other hand, in recent years, attention has been paid to the high speed performance of GaAsFETs, and attempts have been made to make them into logic integrated circuits. In order to simplify the circuit configuration and reduce power consumption, such integrated circuits must be constructed using normally-off FETs (no drain current flows when the gate voltage is zero). Furthermore, multilayer wiring is also required for high-density integration. A conventional microwave GaAsFET is a normally-on type, uses an n-type active layer as a channel layer, and operates by changing the thickness of the channel by a depletion layer of a shot gate. Normally-off integrated circuits use this conventional technique, but the active layer is made thinner so that at zero gate voltage, the gate depletion layer extends to the substrate and closes the channel, forming a normally-off FET. In consideration of multilayer wiring and fine patterning, a planar structure is usually adopted in which electrodes such as a source and a gate are formed on an active layer of uniform thickness. However, such a normally-off type FET has the disadvantage that the active layer is extremely thin and the GaAs surface between the source and gate is depleted, resulting in a very large source resistance. An effective method for reducing the source resistance is to adopt a so-called recessed structure in which the thickness of the source region of the channel layer 12 is thicker than the gate region, as shown in FIG. It's having a big effect. Here, 11 is a high resistance substrate, 13 is a gate shot electrode, and 14 and 15 are source/drain electrodes. However, this structure is not suitable for integration because of the large step difference on the element surface. Furthermore, even when the depth of the recess region is made shallow by forming a thin n ⁺ layer on the surface, there is a drawback that the gate withstand voltage decreases because the n ⁺ region is close to the gate. On the other hand, in order to improve the flatness of the device surface, if the gate 13 is buried in the channel layer 12 as shown in FIG. It is not possible to use this structure because the parasitic capacitance of is increased significantly.

As described above, the present invention provides a field effect transistor that enables a flattened structure and has a low source resistance, which is suitable for integrated circuits, particularly normally-off integrated circuits, which are difficult to apply with conventional structures. It is something.

The FET of the present invention basically has the structure shown in FIG. 3, in which a gate and source/drain electrodes are formed on a first semiconductor layer 22 serving as a channel layer on a high-resistance substrate, and outside the gate region. A second semiconductor layer 23 having a smaller electron affinity (the difference between the energy level of free electrons in a vacuum and the energy level of electrons in a conduction band) is formed on the first semiconductor layer 22 of the first semiconductor. It is something that

The present invention will be explained below with reference to the drawings, and its effects will also be described. An energy band along a cross section between the gate and source of the FET of the present invention (indicated by line A-A' in FIG. 3) and a cross section of the gate portion (indicated by line B-B' in the same figure). The diagrams are as shown in FIGS. 4a and 4b, respectively. However, this is n
This is the case with a channel short gate FET. The energy band diagram of the gate part (Fig. 4b) is
It is similar to a normal FET, and performs transistor operation by changing the thickness of the gate depletion layer. On the other hand, energy band diagram between source and gate (Figure 4a)
Then, due to the difference in electron affinity between the first semiconductor and the second semiconductor, the second semiconductor becomes depleted at the interface, and conversely, the electron density of the first semiconductor increases, resulting in an accumulation state. Therefore, the sheet resistance of the first semiconductor layer becomes small between the source and the gate, and the source resistance decreases. If the difference in electron affinity between the first semiconductor and the second semiconductor is ΔEc, in order for electrons to accumulate on the first semiconductor side at the interface, the effective donor density of the first semiconductor must be N _D1 , Second
Letting the effective donor density of the semiconductor be N _D2 , the following relationship exists.

N _D2 >N _D1 exp [−△Ec/kT] Here, k is Boltzmann's constant and T is absolute temperature. The larger N _D2 is, _the more △
The larger Ec is, the larger the amount of electrons accumulated on the first semiconductor layer side is. If the thickness of the second semiconductor layer 23 is controlled so that the entire layer is depleted, the region where electrons exist is limited to the first semiconductor layer 22, and the region where electrons exist is limited to the first semiconductor layer 22, resulting in a high donor density. However, the second semiconductor layer 23 becomes equivalent to an insulator, and a decrease in reliability such as a decrease in gate breakdown voltage can be prevented. Furthermore, if a semiconductor with a high donor density is used, the required thickness of the second semiconductor layer becomes thinner, so a structure similar to that of a planar FET is possible.

Furthermore, when ΔEc is large, electrons are accumulated on the first semiconductor side even when N _D2 is much smaller than N _D1 , so the structure shown in FIG. 5 is also possible. Here, the second semiconductor layer 23 completely covers the first semiconductor layer 22 and extends to the sides of the gate 24 . Unlike the case of FET shown in Figure 2, this
In FET, N _D2 ≪ N _D1 , so the second
The parasitic capacitance of the portion in contact with the semiconductor layer is small and poses no practical problem. (However, in this case, the gate 24 must also have a shot characteristic with respect to the second semiconductor layer 23.) In particular, if the second semiconductor layer 23 is completely depleted, the parasitic capacitance will be further reduced. Note that in this case, it is not necessary that N _D2 << N _D1 . Moreover, in this structure, the first semiconductor layer, which is the channel layer, is not exposed at all, so reliability is also improved. Figure 6 shows a structure in which the present invention is further developed and the effective donor density N _D2 and thickness of the second semiconductor layer are optimized to make the element surface completely flat, providing an optimal structure for integrated circuits. It is.

Furthermore, FIG. 7 shows that the present invention is of the reverse channel type
MISFET (Metal−Insulator−Semiconductor
FET, insulated gate field effect transistor). Here, 31 is a high resistance board,
32 is a p ^- first semiconductor layer, 33 is an n-type second semiconductor layer.
34 is a gate metal electrode 35, 36 is an n-channel ohmic source/drain electrode, and 37 is a gate insulating film. Here, the second semiconductor layer 33 is selected to invert the interface of the p ^- first semiconductor layer 32 and form a low resistance n-channel 38 with sufficient electron accumulation. This can be achieved by increasing ΔEc and increasing the effective donor density N _D2 . The transistor operation is performed by applying a positive voltage to the guard metal electrode 34 and inducing electrons on the surface of the p ^- layer 32 at the interface of the insulating film 37.
Here, if the second semiconductor layer 33 is entirely depleted as described above, the parasitic capacitance due to gate metal overlap can be suppressed to a small level. Further, according to the present invention, the gate region can be formed by growing the second semiconductor layer 33 over the entire surface and then etching away the second semiconductor layer in the gate region, without forming an n ⁺ region. Therefore, it is possible to simplify the process and miniaturize the gate by selective etching or the like.

Next, specific examples of the present invention will be described. The substrate 21 is a semi-insulating GaAs substrate on which a high purity n-type buffer layer with a carrier density of 1×10 ¹³ cm ⁻³ is grown, for example. On top of that, an n-type layer with an effective donor density of 1×10 ¹⁷ cm ^-3 is grown as a first semiconductor layer, and an n-type Ga _0.7 Al _0.3 layer with an electron affinity smaller than GaAs by about 0.4 eV is grown as a second semiconductor layer. As
The layer is grown, for example by liquid phase deposition. Next, the GaAlAs layer in the gate and source/drain regions is removed and, for example, an Al shot gate and an Au-Ge source/drain ohmic electrode are formed to produce the FET of the present invention. Normally-off type FET
In this case, the thickness of the channel layer is approximately 0.1 μm, and the layer density of electrons is 1×10 ¹² cm ⁻² . However, in a normal planar type, the layer density of electrons in the active layer between the source and gate is significantly reduced to about 2×10 ¹¹ cm ⁻² due to depletion of the GaAs surface. On the other hand, the present invention
In FET, the effective donor density of n-type GaAlAs is
If it is larger than 10 ¹¹ cm ^-3 , an electron accumulation layer is formed on the GaAs side of the interface, and the electron layer density N _sc of the GaAs active layer becomes 1×10 ¹² cm ^-2 or more. for example
Assuming that the effective donor density of the GaAlAs layer is 5×10 ¹⁷ cm ^-3 , which is easily obtained by normal crystal growth, N _sc is 2.5
×10 ¹² cm ^-2 , and the source resistance can be significantly reduced to less than 1/10 of the conventional one. At this time, the thickness of the depleted or effective GaAlAs layer is approximately 400 Å,
It is possible to form an FET with a small semiconductor surface step.

On the other hand, the effective donor density of n-type GaAlAs is 3×
10 ¹⁵ cm ^-3 and a thickness of 0.5 μm, the GaAlAs layer is completely depleted and the N _sc of the GaAs active layer is 1.1×
10 ¹² cm ^{-2 ,} which reduces the source resistance to a fraction of that of the conventional one, and by reducing the gate metal thickness to 0.5 μm, a completely flat device can be realized as shown in Figure 6.

Next, a specific example in which the present invention is applied to MISFET will be described. The substrate is semi-insulating GaAs, with an effective acceptor density of 1 × 10 ¹⁵ cm ^-3 as the first semiconductor layer of ^p-
Using GaAs, n-type Ga _0.7 Al _0.3 with an effective donor density of 4×10 ¹⁶ cm ^-3 and a thickness of 0.12 μm as the second semiconductor.
Uses an As layer. At this time, at the GaAs/GaAlAs interface,
The p ^- -GaAs layer is inverted, and the layer density of electrons is approximately 5×
An n-channel of 10 ¹¹ cm ^-2 is formed and
The GaAlAs layer is completely depleted, as shown in Figure 7.
FET can be realized.

In the above specific examples, GaAs and GaAlAs
Although the example has been described, it is clear that the present invention is also applicable to other compound semiconductors and their ternary and quaternary mixed crystals.

[Brief explanation of drawings]

Figures 1 and 2 show the conventional GaAsFET.
FIG. 3 is a cross-sectional view showing a structure for reducing source resistance.
11 is a high resistance substrate, 12 is a channel layer, 13 is a gate electrode, and 14 and 15 are source and drain ohmic electrodes, respectively. Figure 3 shows the present invention.
FIG. 2 is a cross-sectional view showing the basic structure of an FET. 21 is a high resistance substrate, 22 is a first semiconductor layer in which a channel is formed, 23 is a second semiconductor layer, 24 is a gate electrode, and 25 and 26 are source/drain ohmic electrodes. 4a and 4b are energy band diagrams along the line A-A' and line B-B' in FIG. 3, respectively. FIGS. 5 and 6 are cross-sectional views showing the structure of a flattened FET according to the present invention. 7th
The figure is a cross-sectional view showing a structure in which the present invention is applied to a MISFET. 31 is a high resistance substrate, 32 is a p ^- first semiconductor layer, 33 is an n-type second semiconductor layer, 3
4 is a gate metal electrode, 35 and 36 are source/drain electrodes, 37 is a gate insulating film, and 38 is an inverted n-channel layer.

Claims (1)

[Scope of Claims] 1. A gate and source/drain electrodes are formed on a first semiconductor layer on a high-resistance substrate, and the area on the first semiconductor layer excluding the region where the gate and source/drain electrodes are formed is A second n-type semiconductor which has a lower electron affinity than the first semiconductor and is depleted
A field effect transistor characterized in that a semiconductor layer is formed therein. 2 When the first semiconductor on the high-resistance substrate is n-type, the difference in electron affinity between the first semiconductor and the second semiconductor is △
Ec, the effective donor densities of the first and second semiconductor layers are N _D1 and N _D2 respectively, k is Boltzmann's constant, and T is the absolute temperature, N _D2 > N _D1 exp [−△Ec/kT]. A field effect transistor according to related claim 1. 3. The field effect transistor according to claim 1, wherein a p ^- type semiconductor layer is used as the first semiconductor on the high resistance substrate, and the gate has an insulated gate structure.