JPH0235603A - Method for correcting recording timing - Google Patents

Abstract

PURPOSE:To accomplish correction for recording timing appropriate for the case that code bit strings are in all the bit patterns by identifying the bit patterns over several bits before or after a bit '1' which is going to perform recording in the code bit string and selecting the correction quantity according to the identified pattern. CONSTITUTION:It is identified how the bit '0' and the bit '1' appear in a section from a (d+1)-th bit to a (d+1+mf)-th bit before the specified bit '1' which is going to perform recording in the code bit string or a section from a (d+1)-th bit to a (d+1+mr)-th bit after the above-mentioned bit '1'. The correction quantity is selected according to the identified way the bit '0' and the bit '1' in said sections appear. Thus, the correction quantity for recording timing appropriate for all the code bit strings can be selected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a recording timing correction method for correcting timing deviations that occur when reproducing data recorded in a digital magnetic recording device.

[Conventional technology]

A recording method for achieving high-density recording on magnetic media of digital magnetic recording devices such as magnetic disk devices is to divide a data bit string into a bit “1” and the next bit “1’.
There is a recording method using self-clockable NRZ modulation that converts into a code bit string containing a minimum of d bits (d is a natural number) and a maximum of d bits (k is an integer greater than or equal to d+1) bits "0" between the two.

This method is generally called the (a, k) run-length limited encoding method (hereinafter abbreviated as RLL code), and specifically, it is (2,7) RLL code (1,7) RLL code.
Code is good (known.

However, even with this recording method, as the recording density increases, pattern peak shifts caused by interference between bits become a problem. For example, the reproduced signal when recording is performed with the K signal recording current shown in FIG. 4(a) is the reproduced signal when recording is performed with the recording current shown in FIG. 4(b). Figure 4 (C)
The ratio signal shown in FIG. It is known that the reversal position of the ratio recording current shown in Fig. 4 (f) and the peak position of the reproduction signal shown in Fig. 4 (fl) are KPSI and PE12 in Fig. 4. A deviation of the indicated ratio occurs.

This phenomenon is called pattern peak shift, and causes data errors when the reproduced signal is restored to a bit string.

As a countermeasure for this pattern peak shift, Fig. 4 (g)
A method is used in which recording is performed by previously shifting the inversion position of the recording current in the direction opposite to the pattern peak shift direction.

The reproduced signal at this time is shown in Figure 4 (hl). Figure 4 (h
)K The peak position of the reproduced signal has been corrected to a predetermined position. This method is called recording timing correction.

A conventional example of recording timing correction for a recording method using an RLL code is JP-A-59-γ71i 07. JP-A-60-47213 etc. exist.

FIG. 5 is a circuit diagram of a conventional recording timing correction method described in Japanese Patent Publication No. 59-77607, and FIG. 6 is an explanatory diagram of its operation. fil is a shift register consisting of D-type flip-flops (hereinafter referred to as "D-FFJ") aO to a!J, (2) is a pattern identification circuit consisting of an AND circuit l2Il-■ and an OR circuit @, @, and (3) is a Delay circuit 011-(*, This is a timing correction circuit consisting of FFs (b) to (9) and an OR circuit (to).

(4) is a clock signal input, and (5) is an encoding circuit that converts a data word into a code word in which at least two bits "0" exist between bit "1" and the next bit "1'" (Fig. The code bit string input, C6) sent from (not shown) is (4)
This is a clock signal input with a phase lag. (7) is the corrected data output. I will explain the next IC @ work.

The code pid string (6) is set to D-FFH at the timing of clock (4), and is sequentially set to D-FF (II to D-F).
'F(lυ). On the other hand, by passing the clock (6) through the delay circuit can~(to), the phase-delayed clocks (6a), (6b), (6c) are obtained.D-FFQ5 and IFν09 is “1” and FF is “
0” (10101000!) Ant circuit 12+
177) The aS force is D-7 at the timing of clock 161.
1 [Yes] K is set. v-FFan, (19, and if 1 is 1' (no (NOOn) and circuit 0
0 output is D-FF (149 is 1″, D-IFt12
．． 61 and a't are "1" (XOOOlooO
O) The output of the AND circuit (TO) passes through the OR circuit @ and is set to FF (TO) at the timing of the clock (6a). D-FFfi3. Q! When 9 and aS are “great” (otootooto), the output of the AND circuit [yes] is D
-IrO2 and α scratches are 1" When D-FF'QII and aX5 are "0" (ooootooot) the output of the AND circuit passes through the OR circuit (to) and clocks (6b)
D-PIF (set to 3) at the timing of .

D-FIF (1!9 and 0s are “1”, D-FFg3
When is "0" (XOOOlooIO), the output of the AND circuit is set to D-FF@ at the timing of the clock (6C). The data sorted into the above [Yes] to @ are logically operated by an OR circuit (to) to obtain an output (7).

In other words, in this circuit, the sign bit string is (tootoo
x), the code bit string becomes (10
0010001) and (XOOOloooOO), the code bit string is (0100100) at the reference timing.
10) and the code bit string is (000010001), the code bit string becomes (xooot
ootO), the underlined bit "1" in the code bit string is recorded at a very late timing.

Further, FIG. 7 is a block diagram of a conventional recording timing correction method described in Japanese Patent Laid-Open No. 60-47213, and FIG. 8 is a diagram showing the relationship between the state of the shift register and the amount of correction. In FIG. 1, (1) is a 15-bit shift register 2 (3) is a delay circuit (301) to (510),
AND circuits (311) to (321) and OR circuits (3
22). (4) is the clock signal input, (5) is the data word (2,7) RLL
Code bit string input sent from an encoding circuit (not shown) for converting into code, [7] Data output after offset correction, (
101) to (105), (108) and (N1)
~(115) are the 1st to 5th bits, 8th bits, and 11th to 1st bits of the shift register f1+.
This is a 5-bit output.

Next, the operation will be explained. The shift register fll transfers the code bit string (5) to the first bit string at the timing of the clock (4).
The bits are sequentially shifted from the 5th bit to the 1st bit. The timing of the output (108) of the eighth bit of the shift register fl) is delayed by delay circuits (501) to (310). Here, the delay time T30j'T! of the delay circuits (301) to (310) is T30j'T! 510 is Tsol<Tso2<Tsas<Tso4<T5os<
Tso6<Tsoy<Tsoa<Tsaq<Ts 1° is set. AND circuit (311) ~ (521)
and OR circuit (322) From K, shift register l
) in the output (108) of the 8th bit of the shift register (11) and the output of the delay circuits (301) to (510) One is selected and the corrected data output (7) is obtained. In this recording timing correction method, the forward '! bit of bit "1" in the code bit string is shifted to the rear one (d +
1) The first bit is “1” and the other (d+n) bit is 0
”, if the (d+n+1)th bit is “IN”, nVC
Change the correction amount accordingly. FIG. 8 shows an example of the relationship between the code bit string pattern and the correction amount.

Corrections 8E1 to E5 in FIG. N, D1-D5.

The output of the delay circuit (305) is the reference timing N.
For K, 5 = 0-75Q5 ``4=T501-TE01 ?'3'''T502-T305 ``2''TE01-Ti2O3 ''''T504 TE01 D1''''T506-TE105 D2:T 507-T 505 D! I:TM01-Tsos D4″T509-TE01 D5=T510-Ts05 indicates that the recording timing is shifted.

As described above, in the recording timing correction method for the recording method using the conventional RLL code, the "1" following the bit "1" to be recorded in the code bit string is
The amount of correction is changed according to the number of 0'' bits to be recorded! ” was recorded by correcting the recording timing.

[Problem to be solved by the invention]

However, as recording density increases, a problem arises in that the conventional recording timing correction method cannot perform appropriate correction. R1.d=j. An example of a recording method using an I code will be explained. FIG. 9(1) is an example of a code bit string, (j) is a recording current corresponding to (D), and (k) is a reproduction signal corresponding to (1). Nine (J) is (1)
An example of a code bit string different from (m+ is a mental recording current corresponding to (ri), and (m) is a reproduction signal corresponding to (j).

The underlined bit "1" in the original code bit string shown in (1) and the underlined bit "1" in the original code bit string shown in 1/) are both bits "'0#
There is one in front and one in the back.

In this case, in the conventional recording timing correction method, the above fig.
, [ll are corrected by the same correction amount.

However, the underlined bit "1" in the code bit string shown in (1) has 0000000 behind it.
The bit string “10” continues, whereas the underlined bit “1’” in the code bit string shown in (j)
is followed by a bit string 000001010''.This ninth reproduced signal is generally influenced by several bits before or after the reproduced signal of the corresponding specific bit.For example, (k) and (n ), the pattern peak shifts ps3 and PS4 occurring in the peak corresponding to the underlined bit "1" in the code bit string are not equal.Therefore, with the conventional recording timing correction method, that is, correction with the same correction amount, appropriate correction is not achieved. A friend who has a problem of not being able to do this.

The present invention is intended to solve the above-mentioned problems, and aims to provide a recording timing correction method suitable for all code bit strings.

[Means to solve the problem]

The recording timing correction method according to this invention is (d.

k) In a recording method using an RLL code, the bit “1” that is to be recorded in the code bit string (d+
1) Bit to (cl+1+mf) bit (mf
is the interval up to (1+1 or more integer) or backward (d+1)
From the bit (a + 1 + mr) bit (mr ket d +
A function to identify how bit “0” and bit “1” appear in the interval up to (an integer greater than or equal to 1) and a function to identify how bit “a” and bit “1” appear in the above two intervals. It has a function to select one from a plurality of correction amounts.

be.

[Effect]

The recording timing correction method in this invention is as follows.

Specific bit “1” characterized by recording in code bit string
The interval from the forward (d+1)th bit to the (d+1+ mr)th bit or from the backward (d+1)th bit to (a-
4-1+mr) Identify how bits “0” and bits “1” appear in the interval up to the bit-th bit, and then identify how bits “0” and bits “1” appear in the interval by R. By selecting the correction amount accordingly, it is possible to select an appropriate recording timing correction amount for any code bit string.

[Embodiments of the invention]

Next, an example (mr = mf = 4) will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a recording timing correction system according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram of its operation. In Figure 1, (1) is a D type flip-flop (hereinafter D-F
A 13-bit shift register consisting of (101) to (115), (2) is an AND circuit (201) to
(220), set/reset flip-flop (
(hereinafter referred to as BR-IIF) (221) to (250) and read-on memory (hereinafter referred to as ROM) (2!51)
), (3) is an inverter circuit (531) Kaede 534), D-IPF (335)
, delay circuits (hereinafter referred to as DL) (356) to (339)
), AND circuits (340) to (544), and an OR circuit (545). (4
) is the clock signal, (5) is the (1,7) RLL code bit string input, and (7) is the corrected data w. Also,
(231a) - (231c) are ROM (231)
This is the output of

The friend code bit string input to (5) is changed from D-PIP(1[) to D-F'? at the timing of clock (4). (
101). D-F P (101)
The positive outputs of ~(105) and (109) ~(115) are connected to an AND circuit (201).

(205) , (205) , (207) , (
209), (211), (213).

(215), (217), and (219) Ic are logically ANDed with the positive output of D-IP F (107), and the set a of 1 day R-FF' (221) to (250) is obtained.
input to the child. Also D-F F (101) ~ (10
5) and the negative outputs of (109) to (113) are AND circuits (202), (204), (206),
(208).

(210), (212), (244), (
216), (21B), (220) makes D
-IP? (107) is ANDed with the positive output of E
It is input to the reset terminals of I R-F F (221) to (230). Therefore, when bit "t" is set in D-P IF (107) corresponding to the bit to be corrected, then D-F IP (101) ~
(105) and (109) ~ (113) tD fall is B R-F F (221) ~ (230) K-i! 7
): h, D-PIF (107) K next bit “1”
RR-F IF (221)~(
250) and the first shift is maintained. S.R.F.
The positive outputs of F (221) to (2!10) are ROM (
:>51) is input as the address or pattern to be accessed.

As shown in FIG. 3, ROM (231) K stores information "0""1" corresponding to the recording correction form in each address in advance.
Write either 2", 14" or 8". Third
In the figure, 81 to N5 are 0. 1. It is any value among 2°4.8. Here, "0" is the reference timing, "m" means very early timing, "02" means early timing, "4" means late timing, and "8" means recording at very late timing. shall be taken as a thing. Therefore, when D-PF (107) K bit "1" is set, D-F IF (101) to (1
A signal indicating the recording timing to be selected according to the values of 05) and (109) to (113) is sent to the ROM (254
) outputs (231a) to (231(1)). ROM (231) outputs (231a) to (231
d) is held until the next bit "1" is set in the D-IPF (107).

-) The positive output of 5D-IP F (107) is D -p
F (555) can delay the 1/2 cycle timing of clock (4). The positive output of D -F F (335) is D L (336) to (359) with different delay amounts.
input to further delay the timing. Dr.
The delay amount of C, 556) to (359) is T5s6, respectively.
．． If T5sy, 〒538, T559, then TE101 < TM01 < TM01 < Tss
Suppose that p. The output timing of the late KD-PF (335) is very early, the timing that the output of DI (556) is early, and the reference timing of DL (537).
D L (538) is slow timing, D L
(539) is a very slow timing. Inverter circuits (551) to (554).

AND circuits (540) to C, 544) and OR circuits (
345) Output (231a) of ROM (231) from K
~(231d) One of the one type of timing is selected according to K and output as corrected data (7).

The operation will be explained in more detail with reference to FIG.

Figure 2 shows a state where one unit of 13-bit information is shifted over a period of 25 clocks, and 00
0000010101000000010100000
The operation of the circuit shown in FIG. 1 is explained when a code bit string of ``001'' is input.In the conventional recording timing correction method, the two bits ``1'' (in the following description, 3rd bit 01″ and 5th bit
bit “1”) is corrected by the same correction amount. Mafp,
The ROM (231) has, for example, “
00000100000″ address 8” ”00000
10100″ address VC1141″’000010000
0' address ``1''0000110000'' address ``O''
1', "2" is written at address "0010100000". The above input nine-code bit string is passed through the shift register (1) at the timing of clock (4) from D -F F (115) to I) -F F'
(101). D-FF (107)
K bit “1” is set at 9 o’clock, D −F F
(101) to (105) and (to?) to (113)
The values of 8R-PIP (221) to (230) I/c are set. 8R-F TP (221) ~ (250)
K is set and the ratio value D-IF F (107) is held until the K next bit "1" is set. In other words, the first bit “1” of the input code bit string is D −
F 1F (107) When K is set, SR-
! PF(221) to (230)K are 0″ and “, respectively
o""o"o"'O'"1""Ol'
"1"10"0" are set.

D - F IF (107) K is held until the second bit "1" is set. Similarly, D −'F?
When the second bit “1” is set in (107), E
IFt-Fl(221) to (230)Ic are each “
0""0""On OII l"1""1"
0"0""0""0" is set, D-11
When the third bit of FIP (107)K is set to “1”, 5R-FIP (221) to (230) K are respectively '0' “0” “1” 0” “1” “0” “0” When 0"O", "On" is sent and the fourth bit "1" is set in D-FF (107), 5R-F"F'(
ON 0” for S-(250)
O'0"0"1'0"0"10"0" is set, and D -F F (j0
When the fifth bit “1” is set in 7), 5R-F
F' (221) ~ (230) K is each "0"
0″“0” ON “l” “0″ “0″θ″“
0", 0" are set. S R-F p (221
) to (250) are input to the ROM (231) as addresses to be accessed. ROM (230 outputs the contents of the input address as (231a) to (231d). That is, the first
When bit “1” is set, address “0000010100” of ROM (231) is accessed, and its content “4” becomes (251a) = “0” + (251b
) = “0”, (231c) = “1”, (25
1d) = "0', and this (direct) is D - F
It is held until the second bit "1" is sent to F (107). Similarly, when the second bit “1” is sent to D-FF (j07), 000 of ROM (251)
0110000” address is accessed and its content is “0”
is (231a) 2 “0”, (231b) = “O”
, (2+1c) = “O” (231d) = “o”
is output as To D-FF (107)? 1C30
When bit “1’ is set, ROM (23+)O’
The address “0010100000” is accessed and its contents 12’ are (231a) = “0” (231b) = “1
”, (231c) = “Q ”, (2+1d)
="0" is output. D-'IP F (107)
When the K fourth bit “1” is sent, the ROM (23
4) address “oooootootoooo” is accessed, and its content “8” is (251a)=”0”, (2
34 +) = ``0'' (251c) = ``O'', (
251(1) ==“1” is output.

When the fifth bit “1” is set to M9D-FF (107), ROM (231) On”QOOQl
ooooD” address is accessed and its content “1’ is (231a) = “1” (231b) = “0””,
(251C) = “0”, (231a); “0”
′ is output.

On the other hand, the output of D -F F (107) is D -F F
(?135) delays the clock (4) by half a period. The output of the D-FF (335) is further delayed by four delay circuits (556) to (339) having different delay amounts. Inverter circuits (331) to (334), AND circuits (340) to (34) and OR circuits (345)
Outputs (231a) to (231) of ROM (231) from K
1d) Depending on K, one of the outputs of the D-FF (535) and the delay circuits (!156) to (359) is selected, and corrected data (7) is obtained, and recording is performed.

In other words, the output of the delay circuit (337) is the reference timing,
D-FF C555) output at very early timing, delay circuit (556) at early timing, delay circuit (538) at late timing, *Nobeokaji (339) timing at very late timing. Then, the first bit "1" in the input bit string is the output (231a) of the ROM (231) = "
0” (251t+) = “0”, (231c)
= "1 ', (231 (1) = timing later than "O", second bit "1" is ROM (231)
Output (231a) = “0”, (25+b) = “0”
”, (231c) =MO', (231(1)
= “0” indicates the reference timing, the third bit “1” indicates each output (231a) of the ROM (241) = “0”,
(231b) - "1" (251a) = "'0", (
251d) = “0” causes 2″, that is, the timing is earlier, the fourth bit “1” is the output of ROM (2!11) (231a) = “O”, (251b) = “0”
, (231C) = “O”, (251(1)
= “1” The fifth bit “1” is much later than each output (231a) of the ROM (251) = “
1”, (251b) = “0”, (2510) ==
MO", (231d) = "0", the recording correction amount equivalent information "1", that is, very early timing is selected and recording is performed.

In this way, when the recording timing correction method of the present invention is used, the two underlined bits "1" of the input bit string are corrected differently, whereas the conventional recording timing correction method is corrected with the same amount of correction. Correction can be made by quantity.

In the embodiment, the output of D-P IF (107) is D-I
PF (5!15) is delayed from K but 2 e.g. if there is no such delay then ROM (231)
The W force generation timing is ANDed with the output of D-FF (107) from the rising timing of clock (4).
IC necessarily lags slightly behind, on the other hand D −F F (10
The output generation timing of clock (7) is slightly delayed from the rising timing of clock (4), and the amount of delay is larger in the former. Therefore, as in the embodiment, the output of D-PF (107) is D
- If delayed by FF (335), ROM (23
During the period in which the output of 1) is at the HIGH level, the correction amount of the recording timing correction can be reliably selected within the selectable period. In the present invention, mf and mr are determined by the properties of the magnetic head and recording medium. In the above embodiment, the case where mf=mr=4 was shown. This is because bits "1" existing within 6 bits before and within 6 bits after a certain bit "1" in the code bit string are the main causes of pattern peak shift, and other bits ("EK") are the main cause of pattern peak shift. This is effective when the pattern peak shift is not applied to a certain bin "1" in the code bit string that exists.

In other words, the code bit string is (OOHIIOIOGOloo)
and the code bit string is (10101010001
00) and the sign bit string is (001010
1000101), the underlined bit "1" has a different pattern peak shift by '4E, and the sign bit string is (aoatotataaota
ao) and the code bit string is (10010101
000100G) and the sign bit string is (o
This is effective when the pattern peak shifts occurring in the underlined bit "1" in the case of "ootototootootoot" are approximately equal.

In the above embodiment, rnf=rI3r, but depending on the characteristics of the head and the medium,9For example, if the reproduced signal in FIG. 4 has an asymmetrical waveform, mf>
What is necessary is to set mr or mf<mr.

In the above embodiment, the pattern identification section includes a ROM (25
1) may be used and a logic circuit network may be used instead of the ROM.Furthermore, it is also possible to provide five types of correction timing and increase or decrease as necessary.

In the embodiment, the specific bit "1" to be recorded is
"113M%1 of both the forward and backward few bits of"
We will show an example of selecting the appropriate correction amount by identifying the way in which the The gain is obvious.

〔Effect of the invention〕

As described above, according to the present invention, the bit pattern extending over several bits before or after the bit "1" to be recorded in the code bit string is identified, and the amount of correction is selected accordingly. Appropriate recording timing correction can be performed when the bit string has any bit pattern.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a recording timing correction circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing the operation of the circuit shown in FIG. 1, and FIG. 3 is a pattern identification circuit of the same as shown in FIG. 1. Figure 4 shows the concept of the pattern peak shift, and Figure 5 shows the contents of the ROM when it is conceptualized.
6 is a diagram showing the operation of the circuit in FIG. 5, FIG. 7 is a block diagram of the second conventional example, and FIG. 8 is a diagram showing the operation of the circuit in FIG.
FIG. 9 is a diagram showing the selection conditions of the correction amount in the conventional example, and FIG. 9 is a diagram showing the problems to be solved by the present invention. In the figure, 13) is a shift register, f2 is a pattern-specific circuit, and 13 is a timing correction circuit. The same symbols in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) Data bit string is set to bit “1” and next bit “1”
The number of bits “0” included between
This is a recording timing correction method in a recording circuit that uses an encoding method to convert a code bit string into a code bit string.
The interval from the d+1)th bit to the (d+1+m_f)th bit (where m_f is an integer greater than or equal to d+1) or the backward (d
+1) Identify how bits “0” and bits “1” appear in the interval from the th bit to the (d+1+m_r)th bit (where m_r is an integer greater than or equal to d+1), and identify the appearance of the bit “0” and the bit “1” in the identified two intervals. Select a timing correction amount from a plurality of correction amounts depending on how the bit “0” and bit “1” appear, and apply the selected correction amount to the bit “1” to be recorded in the code bit string. A recording timing correction method characterized by performing recording timing correction based on. (2) Data bit string is set to bit “1” and next bit “1”
The number of bits “0” included between ” is a minimum of d, a maximum of K
This is a recording timing correction method in a recording circuit that uses an encoding method that converts into a code bit string that is a code bit string.
The interval from the d+1)th bit to the (d+1+m_f)th bit (where m_f is an integer greater than or equal to d+1) and the rear (
Identify how bits “0” and bits “1” appear in the interval from bit d+1) to bit (d+1+m_r) (where m_r is an integer greater than or equal to d+1), and identify the appearance of bit “0” and bit “1” in the two identified intervals. Select a timing correction amount from a plurality of correction amounts depending on how the bit “0” and bit “1” appear, and apply the selected correction amount to the bit “1” to be recorded in the code bit string. A recording timing correction method characterized by performing recording timing correction based on.