JPH0236556A - Pin grid array and mounting of semiconductor element - Google Patents

Pin grid array and mounting of semiconductor element

Info

Publication number
JPH0236556A
JPH0236556A JP63187503A JP18750388A JPH0236556A JP H0236556 A JPH0236556 A JP H0236556A JP 63187503 A JP63187503 A JP 63187503A JP 18750388 A JP18750388 A JP 18750388A JP H0236556 A JPH0236556 A JP H0236556A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor element
mounting
flexible substrate
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63187503A
Other languages
Japanese (ja)
Other versions
JPH0777255B2 (en
Inventor
Shigenari Takami
茂成 高見
Tatsuhiko Irie
達彦 入江
Jiro Hashizume
二郎 橋爪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP63187503A priority Critical patent/JPH0777255B2/en
Publication of JPH0236556A publication Critical patent/JPH0236556A/en
Publication of JPH0777255B2 publication Critical patent/JPH0777255B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To make possible an adjustment of a parallelism even if there are warpage, undulation and so on in a substrate by a method wherein the rigid substrate part has lead pins being connected electrically with electrode parts and the flexible substrate part is joined with the rigid substrate part in a state that the flexibility of the flexible substrate part is not damaged. CONSTITUTION:A PGA 1 consists of a flexible substrate part 4 and a rigid substrate part 2, the part 4 is provided with an electric circuit 5 having a multiple of bumps 52... which are electrode parts and the part 2 is provided with lead pins 7. The circuit 5 and an electric circuit 3 provided on the part 2 are joined to each other by a connection part 51 and the bumps 52 are electrically connected with the pins 7. When the bumps 52 are joined with pads of a semiconductor element, the joining can be easily executed by adjusting the parallelism of a head to handle the element to a stage, on which a substrate is placed, regardless of the presence or absence of the warpage, undulation and so on of the substrate.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、ｒｃなどの半導体素子をパッケージ化する
ために搭載するピングリッドアレイ　（以下「ピングリ
ッドアレイ」をｒＰＧＡｊと言う）、および、ＰＧＡに
半導体素子を搭載する方法に関する。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a pin grid array (hereinafter referred to as "pin grid array" rPGAj) mounted for packaging semiconductor elements such as RC, and a PGA. The present invention relates to a method for mounting semiconductor elements on a semiconductor device.

〔従来の技術〕[Conventional technology]

ＩＣのパッド数の増加に伴い、ＴＡＢ　（テープオート
メーテツドボンディング）やフリップチップによるボン
ディングが行われている。ＩＣのパッドと搭載基板の電
極との電気的な接合は、パッド数の増加に比例してボン
ディング時間の長くなるワイヤボンディングよりも、パ
ッド数に関係なく短時間で多数のパ・ノドを一括してボ
ンディングできる（ギヤングボンディングできる）バン
ブボンディングが多くなっている。With the increase in the number of IC pads, bonding using TAB (tape automated bonding) and flip chip bonding is being performed. Electrical bonding between IC pads and electrodes on a mounting board can be achieved by connecting a large number of pads and nodes in a short time regardless of the number of pads, compared to wire bonding, which increases the bonding time in proportion to the increase in the number of pads. There is an increasing number of bump bonding types that can be bonded together (guyang bonding).

ボーンディングに使うバンプは、ＩＣ側または基板側の
いずれかに設けられるが、特に最近では、基板側に設け
られるようになっている。これは、ＩＣ側にバンブを設
けるためには、ＩＣに複雑な加工を施す必要があるから
である。したがって、ＩＣを搭載する基板として、バン
ブ付きＴＡＢ、バンブ付きＰＧＡなどが開発されている
。Bumps used for bonding are provided either on the IC side or on the substrate side, but recently, in particular, bumps have been provided on the substrate side. This is because it is necessary to perform complicated processing on the IC in order to provide the bump on the IC side. Therefore, bumped TABs, bumped PGAs, and the like have been developed as substrates on which ICs are mounted.

第４図ｆａｔおよび（ｂｌにみるように、ＰＧＡ６１は
、多数のり−ドピン７・・・を比較的小さな面積内に配
置できるという利点を有する。また、たとえば、規格化
された間隔でリードビン７・・・を設置するようにする
と、ＩＣ搭載後には、他の基板と接合しやすく、特別な
接合用装置を用いずとも接合を行うことができる。As shown in FIGS. . . . After the IC is mounted, it can be easily bonded to other substrates, and bonding can be performed without using a special bonding device.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、上記ＰＧＡ６１は、セラミック基板などリジッ
ドな基板２０上にＩＣ（図示省略）を搭載するため、基
板２０が反っていたり、うねっていたり、厚みにバラツ
キがあったりすると、基板２０表面の電路３上に設けた
バンブ５２・・・の高さ位置もばらつく。これにより、
ＩＣ接合時のキーバラメーターである平行度に、ばらつ
きが生じ、接合信頼性に大きく悪影響を及ぼす。However, since the PGA 61 has an IC (not shown) mounted on a rigid substrate 20 such as a ceramic substrate, if the substrate 20 is warped, wavy, or uneven in thickness, the electric circuits on the surface of the substrate 20 may The height positions of the bumps 52 provided above also vary. This results in
Variations occur in parallelism, which is a key parameter during IC bonding, and have a large negative impact on bonding reliability.

発明者らは、先に、半導体素子搭載用基板に反り、うね
りなどがある場合に、それに応じて、搭載しようとする
半導体素子の平行度を制御しながら接合を行うという方
法を提案している（特願昭６３−１０１８７８号）。The inventors have previously proposed a method of performing bonding while controlling the parallelism of the semiconductor elements to be mounted when the substrate for mounting semiconductor elements has warpage or waviness. (Patent Application No. 101878/1983).

他方、第３図（ａｌおよび（ｂ）にみるように、バンブ
付きＴＡＢ４０は、バンブ５２・・・がフレキシブルな
フィルム１４のボンディング部の孔４１に突出したフレ
キシブルなり−ド５・・・上に設けられているため、Ｉ
Ｃ（図示省略）との接合時にＩＣとの平行度調整は、Ｉ
Ｃとリード５・・・を加圧・加熱する、半導体素子吸着
ヘッドおよび基板載置ステージの平行度に依存するので
、比較的容易である。On the other hand, as shown in FIGS. 3(al) and (b), in the bumped TAB 40, the bumps 52 are placed on the flexible board 5 which protrudes into the hole 41 of the bonding portion of the flexible film 14. Since it is provided, I
Parallelism adjustment with IC when joining with C (not shown) is done with I
This is relatively easy because it depends on the parallelism of the semiconductor element suction head and the substrate mounting stage that pressurize and heat C and the leads 5 .

その反面、ＩＣ接合後には、フレキシブルフィルム１４
から１個１個切り離して他の基板と接合を行うのである
が、その取り扱いには特別な装置が必要となり、汎用性
に欠けるという問題点を有する。On the other hand, after IC bonding, the flexible film 14
Although the substrate is cut out one by one and bonded to other substrates, special equipment is required to handle it, which poses the problem of lack of versatility.

以上のことに鑑みて、この発明は、半導体素子と、搭載
用基板側の電極部との平行度調整が、同基板の反り、う
ねり等に影響されず、あらかじめ、半導体素子加熱ヒー
ターと基板加熱ヒーターとの間など、半導体素子を扱う
ヘッドと基板を載置するステージとの間の平行度を調整
しておけば基板に反り、うねり等があっても平行度の調
整が行えるＰＧＡを提供することを第１の課題とし、同
ＰＧＡを用いて、半導体素子と基板のバンブとを平行度
良く接合することのできる半導体素子搭載方法を提供す
ることを第２の課題とする。In view of the above, the present invention has been developed so that the parallelism adjustment between the semiconductor element and the electrode portion on the side of the mounting substrate is not affected by the warpage, waviness, etc. of the substrate, and that the parallelism between the semiconductor element heating heater and the substrate heating element is adjusted in advance. To provide a PGA in which parallelism can be adjusted even if the substrate is warped or undulated by adjusting the parallelism between a head that handles semiconductor elements and a stage on which a substrate is placed, such as between a heater and the like. This is the first problem, and the second problem is to provide a method for mounting a semiconductor element that can bond a semiconductor element and bumps on a substrate with good parallelism using the same PGA.

〔課題を解決するための手段〕[Means to solve the problem]

上記第１の課題を解決するために、請求項１の発明にか
かるＰＧＡは、半導体素子の搭載される基板がフレキシ
ブルな基板部分とリジッドな基板部分からなり、前記フ
レキシブルな基板部分が、前記半導体素子のバンドと接
合されて同パッドと電気的に繋がるようになっている電
極部を有する電路を有し、前記リジッドな基板部分が、
前記電極部と電気的に繋がっているリードビンを有し、
前記フレキシブルな基板部分が、そのフレキシブル性を
損なわない状態で前記リジッドな基板部分とが接合され
たものとされている。In order to solve the first problem, in the PGA according to the invention of claim 1, the substrate on which the semiconductor element is mounted is composed of a flexible substrate part and a rigid substrate part, and the flexible substrate part is connected to the semiconductor element. The rigid substrate portion has an electric path having an electrode portion that is bonded to the band of the element and electrically connected to the pad, and the rigid substrate portion
having a lead bin electrically connected to the electrode part,
The flexible substrate portion is bonded to the rigid substrate portion without impairing its flexibility.

上記第２の課題を解決するために、請求項２の発明にか
かる半導体素子搭載方法は、請求項１記載のＰＧＡのフ
レキシブルな基板部分の電極部と、半導体素子のパッド
とを対面させた状態で、前記フレキシブルな基板部分の
電路の上下から加圧および加熱を行って前記電極部と前
記パッドとの接合を行うようにしている。In order to solve the above second problem, a semiconductor element mounting method according to the invention of claim 2 is provided in which the electrode portion of the flexible substrate portion of the PGA according to claim 1 faces the pad of the semiconductor element. Pressure and heat are applied from above and below the electrical path of the flexible substrate portion to bond the electrode portion and the pad.

〔作　　　用〕[For production]

請求項１の発明にかかるＰＧＡは、電極部がフレキシブ
ルな基板部分に支持されているため、半導体素子のパッ
ドと接合するときに、基板の反り、うねりなどの有無に
関わらず、半導体素子加熱ヒーターと基板加熱ヒーター
との平行度など、半導体素子を扱うヘッドと基板を載置
するステージとの平行度に依存して前記電極部とパッド
との平行度が調整される。これにより、接合が容易に行
うことができる。しかも、リードビンの設けられたリジ
ッドな基板部分と前記フレキシブルな基板部分とが接合
されているので、ＩＣなど半導体素子（半導体チップ）
を搭載したあとも取り扱いやすく、汎用性がある。In the PGA according to the invention of claim 1, since the electrode part is supported by the flexible substrate part, the semiconductor element heating heater can be used when bonding to the pad of the semiconductor element, regardless of the presence or absence of warpage or waviness of the substrate. The parallelism between the electrode section and the pad is adjusted depending on the parallelism between the head that handles the semiconductor element and the stage on which the substrate is placed, such as the parallelism between the head that handles the semiconductor element and the stage on which the substrate is placed. Thereby, joining can be easily performed. Moreover, since the rigid substrate portion provided with the lead bin and the flexible substrate portion are bonded, semiconductor elements such as ICs (semiconductor chips)
Even after it is installed, it is easy to handle and has versatility.

請求項２の発明にかかる半導体素子搭載方法は、ＰＧＡ
のフレキシブルな基板部分の電極部と半導体素子のパッ
ドとを対面させた状態で、前記フレキシブルな基板部分
の上下から加圧および加熱を行うことにより、半導体素
子を扱うヘッドと基板を載置するステージとの平行度に
依存して前記電極と前記パッドとの平行度が調整され、
接合信頼性の高い搭載を行うことができる。しかも、汎
用性のある半導体素子搭載基板が得られる。The method for mounting a semiconductor element according to the invention of claim 2 is a method for mounting a semiconductor element on a PGA.
A stage on which a head for handling a semiconductor element and a substrate are mounted by applying pressure and heating from above and below to the flexible substrate part with the electrode part of the flexible substrate part and the pad of the semiconductor element facing each other. The parallelism between the electrode and the pad is adjusted depending on the parallelism between the electrode and the pad,
Mounting with high bonding reliability can be achieved. Moreover, a versatile semiconductor element mounting board can be obtained.

〔実　施　例〕〔Example〕

以下に、この発明を、その実施例を表す図面を参照しな
がら詳しく説明する。Hereinafter, the present invention will be explained in detail with reference to the drawings showing embodiments thereof.

第１図（ａ）および（ｂ）は、請求項１の発明にかかる
ＰＧＡの１実施例を表す。これらの図にみるように、こ
のＰＣＡＩは、フレキシブルな基板部分４およびリジッ
ドな基板部分２からなる。フレキシブルな基板部分４に
は、電極部である多数のバンプ５２・・・を有する電路
（リード）５・・・が設けられている。リジッドな基板
部分２には、リードピン７・・・が設けられている。リ
ードピン７は、スルーホール６に差し込んで設置された
り、スルーホール６縁のランド３１にろう付けされて設
置されたりする。なお、リードピン７・・・は、半導体
素子搭載面側であってもよく、この面の裏面側であって
もよい。フレキシブルな基板部分４とリジッドな基板部
分２とは、フレキシブルな基板部分４のフレキシブル性
を損なわない状態で接合されて一体になっている。FIGS. 1(a) and 1(b) represent one embodiment of a PGA according to the invention of claim 1. FIG. As seen in these figures, this PCAI consists of a flexible substrate section 4 and a rigid substrate section 2. The flexible substrate portion 4 is provided with electrical circuits (leads) 5 having a large number of bumps 52 serving as electrode portions. The rigid substrate portion 2 is provided with lead pins 7 . The lead pin 7 is installed by being inserted into the through hole 6, or is installed by being brazed to the land 31 on the edge of the through hole 6. Note that the lead pins 7 may be on the semiconductor element mounting surface side, or may be on the back side of this surface. The flexible substrate portion 4 and the rigid substrate portion 2 are joined and integrated without impairing the flexibility of the flexible substrate portion 4.

バンプ５２は、フレキシブルな基板部分４に設けられた
電路５とリジッドな基板部分２上に設けられた電路３と
が接続部５１により接合されていて電気的に繋がってい
ることにより、リードピン７と電気的に繋がっている。The bump 52 is connected to the lead pin 7 by connecting the electric path 5 provided on the flexible substrate portion 4 and the electric path 3 provided on the rigid substrate portion 2 by the connecting portion 51 and electrically connecting them. electrically connected.

前記接続部５１としては、たとえば、フレキシブルな基
板部分４に設けたアウターリードが利用される。前記電
路３と電路５との接合方法は、特に■定はなく、たとえ
ば、半田付けでもよく、導電性の接着剤による接合でも
よく、電気的に繋がれるか、または、電気的および機械
的に接合されればよい。As the connection portion 51, for example, an outer lead provided on the flexible substrate portion 4 is used. The method of joining the electrical circuit 3 and the electrical circuit 5 is not particularly limited, and for example, soldering or electrically conductive adhesive may be used to connect the electrical circuit 3 and the electrical circuit 5. It only needs to be joined.

フレキシブルな基板部分４としては、ＴＡＢなどのフィ
ルムキャリアに用いられるフレキシブルフィルム、たと
えば、ポリイミドフィルムなどが使用される。バンプ付
きＴＡＢなどＴ　Ａ　Ｂをそのフレキシブル性を損なわ
ない状態でリジッドな基板骨と接合するようにしてもよ
い。As the flexible substrate portion 4, a flexible film used for a film carrier such as TAB, such as a polyimide film, is used. A TAB such as a bumped TAB may be joined to a rigid substrate bone without impairing its flexibility.

フレキシブルな基板部分４に設けられる電路５は、フレ
キシブルであることが好ましく、たとえば、金属箔など
金属の薄膜などが使われる。金属としては、銅などが使
用されるが、これに限るものではない。前記電路５は、
第１図にみるように、これを支持するフレキシブルな基
板部分４の孔に突出している、いわゆる、インナーリー
ド、のようになっていてもよ（、同基板部分４上に沿っ
て設けられていてもよい。電路５の電極部にはバンプを
設けて、フレキシブルな基板部分をバンプ付きＴＡＢな
どとしてもよい。なお、バンプは、半導体素子のパッド
に設け、基板側には設けないようにしてもよいが、基板
側に設けるようにすると、上述した利点がある。バンプ
は、金、半田、アルミニウムなど適宜のものが使用され
る。The electric circuit 5 provided on the flexible substrate portion 4 is preferably flexible, and for example, a thin metal film such as metal foil is used. Copper or the like is used as the metal, but it is not limited to this. The electric circuit 5 is
As shown in FIG. 1, it may be a so-called inner lead that protrudes into the hole of the flexible substrate portion 4 that supports it. Bumps may be provided on the electrode portions of the electrical circuits 5, and the flexible substrate portion may be used as a TAB with bumps.The bumps may be provided on the pads of the semiconductor element and not on the substrate side. However, if the bumps are provided on the substrate side, there is the above-mentioned advantage.The bumps may be made of gold, solder, aluminum, or the like as appropriate.

リジッドな基板部分２としては、セラミック基板、樹脂
含浸基材から作った基板などが使用される。リジッドな
基板部分２は、たとえば、中央部の半導体素子搭載部に
あたる部分のない形、たとえばリング状の形とされ、こ
のリングの内側の孔２１の縁にフレキシブルな基板部分
４の外側の縁が重ね合わさせて接合されることにより、
上記のように、フレキシブルな基板部分４のフレキシブ
ル性をＦＢなわない状態で接合される。しかし、この状
態でのフレキシブルな基板部分４とリジッドな基板部分
２との接合の仕方はこれに限らない。As the rigid substrate portion 2, a ceramic substrate, a substrate made from a resin-impregnated base material, etc. are used. The rigid substrate portion 2 has, for example, a ring shape without a central portion corresponding to the semiconductor element mounting portion, and the outer edge of the flexible substrate portion 4 is attached to the edge of the hole 21 inside the ring. By overlapping and joining,
As described above, the flexible substrate portion 4 is bonded without bending the FB. However, the method of joining the flexible substrate portion 4 and the rigid substrate portion 2 in this state is not limited to this.

リジッドな基板部分２の上に設けられる電路３としては
、たとえば、前記電路５と同様、金属箔など金属の薄膜
などが使われ、金属としては銅などが使われる。As the electric path 3 provided on the rigid substrate portion 2, for example, like the electric path 5, a metal thin film such as metal foil is used, and the metal is copper or the like.

フレキシブルな基板部分４とリジッドな基板部分２との
接合は、前記電路３．５の接合により間接的になされて
もよく、接着剤などで直接的になされてもよ（、特に限
定はない。The flexible substrate portion 4 and the rigid substrate portion 2 may be bonded indirectly by bonding the electrical circuits 3.5, or may be directly bonded using an adhesive or the like (although there is no particular limitation).

第２図（ａｌおよび（ｂ）は、請求項２の発明にかかる
半導体素子搭載方法の１実施例を表す。これらの図にみ
るように、半導体素子搭載用基板として、第１図に示す
ＰＧＡＩを基板載置ステージ（図示されず）の上に準備
する。他方、基板載置ステージの基板を加熱するヒータ
ー（または同ステージ）１０、および、半導体素子を加
熱するヒーターを備え半導体素子を扱うヘッド９の間の
平行度を調整しておく。半導体素子８をヘッド９で取り
扱い、同ヘンド９とヒーター１０との間に半導体素子８
のバンド（図示されず）と基板側のバンブ５２・・・と
を対面するよう位置合わせし、この対面させた状態で決
み込む。そして、基板側のバンブ５２・・・と半導体素
子のパッドとを加圧しながら加熱し、熱圧着する。これ
により、信頼性の高い接合で半導体素子が基板に搭載さ
れるのである。Figures 2 (al and b) represent one embodiment of the semiconductor element mounting method according to the invention of claim 2.As seen in these figures, the PGAI shown in Figure 1 can be used as a semiconductor element mounting substrate. is prepared on a substrate mounting stage (not shown).On the other hand, a head that handles semiconductor elements is equipped with a heater (or the same stage) 10 that heats the substrate on the substrate mounting stage and a heater that heats the semiconductor elements. 9. The semiconductor element 8 is handled by the head 9, and the semiconductor element 8 is placed between the head 9 and the heater 10.
The band (not shown) and the bumps 52 on the board side are aligned so that they face each other, and are fitted in this facing state. Then, the bumps 52 on the substrate side and the pads of the semiconductor element are heated while being pressed to bond them by thermocompression. This allows the semiconductor element to be mounted on the substrate with highly reliable bonding.

前記ヘッド９に、超音波を印加する機構を設けておき、
半導体素子の接合時に超音波を印加するようにすると、
より低温で、さらには加熱を行わずに、接合を行うこと
ができる。The head 9 is provided with a mechanism for applying ultrasonic waves,
If ultrasonic waves are applied when bonding semiconductor elements,
Bonding can be performed at lower temperatures and even without heating.

なお、この発明は、上記実施例に躍らない。たとえば、
半導体素子を扱うヘッド、および、基板を載置するステ
ージで加熱を行わず、加圧のみを行って、超音波などを
利用して圧着を行うようにしてもよい。このようにする
と、加熱を行わないので、加熱による弊害をなくすこと
ができる。搭載された半導体素子は、必要に応じて、気
密封止、樹脂封止などにより封止される。It should be noted that the present invention is not limited to the above embodiments. for example,
The head that handles the semiconductor element and the stage on which the substrate is placed may not be heated, but only pressurized, and crimping may be performed using ultrasonic waves or the like. In this way, since heating is not performed, the adverse effects caused by heating can be eliminated. The mounted semiconductor element is sealed by hermetic sealing, resin sealing, etc. as necessary.

〔発明の効果］ 請求項１の発明にがかるＰＧＡは、以上のようなもので
あるので、半導体素子搭載部の電極部と半導体素子との
平行度が、基板の反り、うねり等にｉＳｌされず、半導
体素子を扱うヘッドと基板載置ステージまたは基板加熱
ヒーターとの平行度により調整されるようになる。また
、このＰＧＡは、半導体素子を搭載した後に他の基板と
接合する際に、特別な接合用装置を必要とせず、リード
ピンの挿入孔があれば、汎用的に使用することができる
ものである。[Effect of the Invention] Since the PGA according to the invention of claim 1 is as described above, the parallelism between the electrode part of the semiconductor element mounting part and the semiconductor element is not affected by warping, waviness, etc. of the substrate. It is adjusted by the parallelism between the head that handles the semiconductor element and the substrate mounting stage or substrate heating heater. Furthermore, this PGA does not require any special bonding equipment when bonding to other substrates after mounting semiconductor elements, and can be used for general purposes as long as it has lead pin insertion holes. .

請求項２の発明にかかる半導体素子搭載方法は、以上の
ようなものであるので、半導体素子搭載用基板に反り、
うねり等があっても、半導体素子を扱うヘッドと基板載
置ステージまたは基板加熱ヒーターとの平行度を調整し
ておくことにより、半導体素子搭載用基板の電極部と半
導体素子との平行度を調整することができ、接合信頼性
の高い接合を行うことができる。Since the semiconductor element mounting method according to the invention of claim 2 is as described above, the semiconductor element mounting substrate is not warped.
Even if there is waviness, the parallelism between the electrode part of the semiconductor element mounting board and the semiconductor element can be adjusted by adjusting the parallelism between the head that handles the semiconductor element and the substrate mounting stage or substrate heating heater. Therefore, it is possible to perform a bond with high bonding reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は請求項１の発明にがかるＰＧＡの１実施例を表
し、図（ａｌは斜視図、図（ｂ）は側面断面図、第２図
は請求項２の発明にかかる半導体素子搭載方法の１実施
例を表し、図（ａ）は搭載前の側面断面図、図（ｂｌは
搭載後の側面断面図、第３図（８）はバンブ付きＴＡＢ
の１例の平面図、同図（ｂ）はそのＡ−Ａ断面図、第４
図（ａｌは従来のバンブ付きＰＧＡの１例の斜視図、同
図（ｂ）はそのＢ−Ｂ断面図である路　４・・・フレキ
シブルな基板部分　５・・・電路　７・・・リードビン
　８・・・半導体素子　９・・・半導体素子を扱うヘッ
ド　１０・・・基板を加熱するヒーター５１・・・接続
部　５２・・・バンブFIG. 1 shows an embodiment of the PGA according to the invention of claim 1, and the figures (al is a perspective view, FIG. 2 (b) is a side sectional view, and FIG. Figure (a) is a side sectional view before installation, Figure (bl is a side sectional view after installation, and Figure 3 (8) is a TAB with bumps.
A plan view of an example of
Figure (al is a perspective view of an example of a conventional bumped PGA, and Figure (b) is a sectional view taken along line B-B.) Path 4...Flexible board portion 5...Electric path 7...Lead bin 8 ...Semiconductor element 9...Head that handles the semiconductor element 10...Heater 51 that heats the substrate 51...Connection part 52...Bump

Claims (1)

【特許請求の範囲】 １、半導体素子の搭載される基板がフレキシブルな基板
部分とリジッドな基板部分からなり、前記フレキシブル
な基板部分が、前記半導体素子のパッドと接合されて同
パッドと電気的に繋がるようになっている電極部を有す
る電路を有し、前記リジッドな基板部分が、前記電極部
と電気的に繋がっているリードピンを有し、前記フレキ
シブルな基板部分が、そのフレキシブル性を損なわない
状態で前記リジッドな基板部分とが接合されているピン
グリッドアレイ。 ２、請求項１記載のピングリッドアレイのフレキシブル
な基板部分の電極部と、半導体素子のパッドとを対面さ
せた状態で、前記フレキシブルな基板部分の電路の上下
から加圧および加熱を行って前記電極部と前記パッドと
の接合を行う半導体素子搭載方法。[Claims] 1. A substrate on which a semiconductor element is mounted is composed of a flexible substrate part and a rigid substrate part, and the flexible substrate part is connected to a pad of the semiconductor element and is electrically connected to the pad. The circuit board has an electrical path having an electrode part connected to the board, the rigid board part has a lead pin electrically connected to the electrode part, and the flexible board part does not impair its flexibility. The pin grid array is connected to the rigid substrate portion in a state. 2. With the electrode portion of the flexible substrate portion of the pin grid array according to claim 1 facing the pad of the semiconductor element, pressure and heating are applied from above and below the electrical path of the flexible substrate portion to A method for mounting a semiconductor device, in which an electrode portion and the pad are bonded.
JP63187503A 1988-07-26 1988-07-26 Pin grid array and semiconductor device mounting method Expired - Fee Related JPH0777255B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63187503A JPH0777255B2 (en) 1988-07-26 1988-07-26 Pin grid array and semiconductor device mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63187503A JPH0777255B2 (en) 1988-07-26 1988-07-26 Pin grid array and semiconductor device mounting method

Publications (2)

Publication Number Publication Date
JPH0236556A true JPH0236556A (en) 1990-02-06
JPH0777255B2 JPH0777255B2 (en) 1995-08-16

Family

ID=16207205

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63187503A Expired - Fee Related JPH0777255B2 (en) 1988-07-26 1988-07-26 Pin grid array and semiconductor device mounting method

Country Status (1)

Country Link
JP (1) JPH0777255B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4237267A1 (en) * 1991-11-14 1993-05-19 Gold Star Electronics Plug-type casing for semiconductor IC - has semiconductor chip with bondable coupling faces and plug for casing mounting on circuit board.
US5493150A (en) * 1993-02-15 1996-02-20 Yamaichi Electronics Co., Ltd. IC carrier
US5494169A (en) * 1993-06-29 1996-02-27 Yamaichi Electronics Co., Ltd. IC carrier
US5536969A (en) * 1992-12-18 1996-07-16 Yamaichi Electronics Co., Ltd. IC carrier
US5717162A (en) * 1995-04-07 1998-02-10 Yamaichi Electronics Co., Ltd. IC carrier having a movable and stationary corner rulers

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6252946U (en) * 1985-09-20 1987-04-02

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6252946U (en) * 1985-09-20 1987-04-02

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4237267A1 (en) * 1991-11-14 1993-05-19 Gold Star Electronics Plug-type casing for semiconductor IC - has semiconductor chip with bondable coupling faces and plug for casing mounting on circuit board.
DE4237267C2 (en) * 1991-11-14 2000-03-09 Gold Star Electronics Plug-like housing for an integrated semiconductor circuit
US5536969A (en) * 1992-12-18 1996-07-16 Yamaichi Electronics Co., Ltd. IC carrier
US5493150A (en) * 1993-02-15 1996-02-20 Yamaichi Electronics Co., Ltd. IC carrier
US5494169A (en) * 1993-06-29 1996-02-27 Yamaichi Electronics Co., Ltd. IC carrier
US5717162A (en) * 1995-04-07 1998-02-10 Yamaichi Electronics Co., Ltd. IC carrier having a movable and stationary corner rulers

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