JPH0237708A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make it possible to accurately detect the reference position of a device at any time by a method wherein the shape of an alignment mark is reflected on the device surface at any time by forming an alignment mark by a plurality of layers. CONSTITUTION:Etching processing is perform with a resist pattern 8 as a mask, obtaining alignment marks 4a, 4b of a two-layer structure. Next, an inter-layer insulation film 3b is formed, and an area corresponding to an alignment forming area 6 is removed. At this time, a portion of the upper layer of a field oxide film 2 in the periphery of the alignment marks 4a, 4b is removed, forming a recess 20. Then, an aluminum layer 5 is formed on the entire surface and a device is obtained by patterning. Since an alignment mark is of a two-layer structure in this way, the thickness of an alignment mark is two times that of a conventional one. The shape of an alignment mark is reflected on the device surface, and the reference position of a device can be detected at any time.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an alignment mark used during laser positioning in a semiconductor integrated circuit device such as a DRAM having a redundancy system using laser trimming, for example.

[Conventional technology]

Figure 3 shows D1 with a built-in conventional alignment mark.
FIG. 1 is a cross-sectional view of a semiconductor integrated circuit device such as 1AM. In the figure, 1 is a semiconductor substrate, and a field oxide lI2 is formed on the semiconductor substrate 1. Field oxide film 2 is a region provided to isolate elements formed on semiconductor substrate 1. , 3 is an interlayer insulating film such as a PSG film that covers the semiconductor substrate 1 and the field oxide film 2;
Reference numeral 4 indicates 7 alignment marks provided in the interlayer insulating film F1 portion.

This alignment mark 4 is formed of a polysilicon layer which is the same layer as the layer to be laser trimmed.

Furthermore, an aluminum layer 5 is formed on the interlayer insulating film 3, and the aluminum layer 5 has a shape wider than the alignment mark 4 and is an interlayer insulator! It covers Ij43.

When the upper part of the aluminum layer 5 of the semiconductor integrated circuit device incorporating the alignment mark 4 configured as described above is scanned with a laser beam, strong reflected light due to a large reflectance can be monitored. At the same time, since the surface of this aluminum layer 5 has uneven step portions 5a reflecting the presence of the alignment marks 4 in the lower layer, the reflected light is scattered at each of the step portions 5a, and the light of the reflected light is The amount of monitoring will be reduced. By detecting this, it is possible to finally confirm the position of the alignment mark 4, that is, the reference position of the layer to be laser trimmed, with high accuracy.

[Problem to be solved by the invention]

A conventional semiconductor integrated circuit device with a built-in alignment mark is configured as described above, and by detecting the stepped portion 5a of the aluminum layer 5 that reflects the alignment mark 4, the reference position of the layer to be laser trimmed is confirmed. was.

The polysilicon layer, which is the layer to be detrimmed, is generally used to form a high resistance layer in high resistance load type SRAMs. , the film thickness tends to be thinner.

On the other hand, as the integration density of devices improves and surface flattening technology advances, interlayer insulation g! 3 tends to be flattened.

For the above two reasons, the shape of the alignment mark 4 is difficult to be reflected on the surface of the aluminum layer 5 formed on the interlayer insulating film 3, and the detection accuracy when using the reflected light of the laser beam is reduced. There was a problem that position detection was difficult.

This invention was made to solve the above-mentioned problems, and provides a semiconductor integrated circuit device in which the shape of an alignment mark is always reflected on the device surface, and the reference position of the device can always be accurately detected. The purpose is to

(Means for Solving the Problems) A semiconductor integrated circuit device according to the present invention has an alignment mark that does not indicate a reference position of a predetermined layer by being detected by laser beam irradiation, and has a surface alignment mark. , is formed of a plurality of layers with the uppermost layer being formed simultaneously with the predetermined layer.

[Effect]

Since the alignment mark in this invention is formed of a plurality of layers, the film thickness of the alignment mark is the sum of the film thicknesses of each layer.

〔Example〕

FIG. 1 is a sectional view showing a semiconductor integrated circuit device which is an embodiment of the present invention. As shown in the figure, alignment marks 4a and 4b are formed in two layers. Further, the interlayer insulating film 3 of the alignment mark formation [6] has been removed, and the field oxide film 2 on the outer periphery of the alignment marks 4a, 4b is roughly on the right side of the four parts 20. and,
The aluminum layer 5 is formed directly on the alignment mark 4b and the field oxide film 2 in the alignment mark forming region td6.

FIGS. 2(a) to 2([) are cross-sectional views showing a method of manufacturing the semiconductor integrated circuit device shown in FIG. 1, respectively. below,
The manufacturing method will be explained with reference to the same figure.

First, a field oxide film 2 is formed on a semiconductor substrate 1,
As shown in FIG. 2(a), the polysilicon layer 4 is wider than the alignment mark formation 114 on the field oxide film 2.
Form 0a. This polysilicon layer t140a is the same layer as a polysilicon layer (not shown) used as a gate electrode and wiring of a transistor in an internal circuit.

Next, the entire surface is covered with an interlayer insulating film 3a, and a photoresist is further formed and patterned on this living room insulating film 3a to form a resist pattern 7 having an opening in a region corresponding to the alignment mark forming region 1ift6. It is formed as shown in Figure (b).

Then, using resist pattern 7 as a mask, etching is performed on interlayer insulation g13a to expose the surface of polysilicon layer 408 in alignment mark forming region 6. Thereafter, a polysilicon layer 40b is formed over the entire surface by CVD.

This polysilicon layer 40b is the same layer as a polysilicon layer (not shown) used as a high resistance layer and wiring (having a laser trimmed region) in the internal circuit. Next, 7 photoresist is applied on the polysilicon layer 40b, and this photoresist is patterned into a predetermined pattern (the above-mentioned high-resistance layer, wiring pattern, and alignment mark pattern) as shown in FIG. A resist pattern 8 is obtained.

Then, by performing an etching process using this resist pattern 8 as a mask, alignment marks 4a and 4b having a two-layer structure can be obtained as shown in FIG. 2(d).

Next, PSGI all over! ! An interlayer insulating film 3b consisting of 1 is formed as shown in FIG.
A photoresist is applied on the photoresist 13b and patterned to form a resist pattern 9 having an opening in the alignment mark forming region 6.

This resist pattern 9 can also be used as a resist pattern for forming contact holes in the internal circuit. By performing an etching process using this resist pattern 9 as a mask, the interlayer insulating film 3b in the alignment forming region 6 is removed as shown in FIG. At this time, a portion of the first layer of the field oxide film 2 around the alignment marks 48 and 4b is removed, and a recess 20 is formed.

Thereafter, aluminum FfA5 is formed on the entire surface and patterned to obtain the semiconductor integrated circuit device shown in FIG. 1.

In this way, since the alignment mark has a two-layer structure, the thickness of the alignment mark is twice that of the conventional one.
Even if the individual polysilicon layer 40a and job are USized,
The stepped portion 5a of the aluminum layer 5 can be sufficiently detected by laser beam irradiation.

Furthermore, since the polysilicon layers 40a and 40b forming the alignment marks 4a and 4b are formed simultaneously in the wiring, transistor gate, or high resistance layer formation process, a separate process is provided for forming the alignment marks 4a and 4b. There is no heart.

In addition, the interlayer insulating film 3 in the alignment forming region 6 is removed by etching, and during this etching, a part of the upper layer of the field oxide film 2 around the alignment marks 4a and 4b is removed, and the field oxide film around the alignment marks 4a and 4b is etched. A recess 120 is formed in the membrane 2. Therefore, the stepped portion 5a of the aluminum layer 5 serves as an alignment mark 4a.

4b film thickness, and in addition, field oxide film 2.
Since the depth of the four portions 20 of the aluminum layer 5 is reflected, the stepped portion 5a of the aluminum layer 5 can be more easily detected by laser beam irradiation.

This alignment]・The etching of the living room insulating film 3 in the formation area is due to progress in planarization technology for the interlayer insulating film 3.
7 Even if the thickness of the alignment mark is increased, the interlayer insulation rlA
This is particularly effective when 3 is flattened.

In this embodiment, the alignment mark is formed of two polysilicon layers, but the present invention is not limited to this, and the alignment mark may be formed of a multilayer structure of three or more layers. In this case, the layer formed at the same time as the layer to be trimmed needs to be the top layer of the alignment mark.

〔Effect of the invention〕

As explained above, according to the present invention, since the alignment mark is formed of multiple layers, the thickness of the alignment mark is the sum of the thicknesses of each layer, so the shape of the alignment mark is always reflected on the surface of the device. This has the effect that the reference position of the device can always be detected accurately.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIGS. 2(a) to 2(m) are sectional views showing a method for manufacturing the semiconductor integrated circuit device shown in FIG. 3
The figure is a sectional view showing a conventional semiconductor integrated circuit device. In the figure, 4a and 4b are alignment marks. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa

Claims (1)

[Claims] (1) In a semiconductor integrated circuit device having an alignment mark that is detected by laser beam irradiation and indicates a reference position of a predetermined layer, the alignment mark is formed at the same time as the predetermined layer and a layer formed at the same time as the uppermost layer. A semiconductor integrated circuit device characterized in that it is formed of a plurality of layers.