JPH023940A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve yield by utilizing a low resistive layer as a substratam to be coated by electrolytic plating. CONSTITUTION:A gate electrode constituting layer 47 is used as a protecting film for the contamination of a substrate, and a low resistive layer 45 is used as a substratum to be coated by electrolytic plating. In the state where the gate electrode constituting layer 33 of a gate electrode forming region is covered with an insulating mask 35, a plating pattern metal layer 35 and a resist pattern 41 are formed, and a resistor layer is formed in the manner of self alignment. After that, by using this low resistive layer 45 as an etching mask, a gate electrode 47 composed of two layers of the gate electrode constituting layer 33 and the low resistive layer 45 is formed by self-alignment.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to, for example, a field effect transistor (hereinafter simply FET).
stor). ), and particularly relates to a method that avoids substrate contamination and easily forms low-resistance electrodes.

(Prior Art) Conventionally, FET elements have been widely used as semiconductor elements constituting electronic devices.

When configuring electronic equipment with various functions using these FET elements, ultra-high-performance integrated circuits (VLS
Research and development to achieve I) is underway. In this FET element, a technique is widely known in which a heat-resistant metal is used as the material constituting the gate electrode, and a source active region and a train active region are formed with a self-line on this electrode.

As such a technique, for example, the literature: “Inter-
national 5olid-3tate C1
rcuits Conference Diquest
Of technical papers (International Solid State Certification Conference Digest of Technical Papers)
(Yokoyama et al., pp. 218-219, February 20, 1981
GaAs-MES (Meta
2. Description of the Related Art A method of manufacturing an FET device (1 Semiconductor) is known.

Hereinafter, as an example of a conventionally known semiconductor device manufacturing technology, the GaAs-MESFE disclosed in the above-mentioned document will be described.
The manufacturing technology of the T element will be explained with reference to the drawings.

FIGS. 2(A) to 2(D) are explanatory diagrams showing each manufacturing process using a schematic cross section of a substrate for explaining the method for manufacturing the above-described element. Note that in these figures, hatching and the like indicating cross sections are partially omitted.

Furthermore, in order to facilitate understanding of the following explanation, in this specification, the component before being activated by heat treatment will be referred to as an impurity region, and the component after the treatment will be referred to as an active i region.

First, on the surface of a substrate 11 made of semi-insulating GaAs, a region (
Hereinafter, this will be referred to as an element region. ) 13 is exposed and a resist pattern 15 is formed to cover other areas. Thereafter, using this resist pattern 15 as an ion implantation mask, for example, silicon ions (Si'') or other n-type impurities (indicated by a series of arrows a in the figure) are implanted at an acceleration energy of about 30 to 60 (KeV) and plane 2 degree is 10′2-10”
A channel impurity region 17 is formed by ion implantation under conditions of approximately (cm-2) (Fig. 2(A)).
.

Next, after removing the resist pattern 15 described above, a material having heat resistance, such as titanium-tungsten (Ti-W) alloy, for example, is applied to the gate electrode forming region 19 of the substrate 11.
A gate electrode 21 made of metal and forming a main shot barrier with the substrate 11 is deposited to a thickness of about 5000 (λ) (FIG. 2(B)).

This gate electrode 21 is made of the above-mentioned heat-resistant metal on the substrate 11.
After depositing on the entire surface, patterning is performed by plasma etching using carbon tetrafluoride (CF4) and oxygen (0□) as an etching gas, or by lift-off technology without performing an etching process. There is also

Subsequently, the above-described element region 13 is exposed and other regions iF are formed.
! After forming a resist pattern 23 covering the region i, using the resist pattern 23 and the aforementioned gate electrode 21 as an ion implantation mask, the source/drain impurity regions 25 are formed by implanting n-type impurities at in the same manner as described above. (Figure 2 (C)).

This source/drain impurity region 25 is deeply implanted with a higher concentration of impurity than the channel impurity region 17 described above, and has an acceleration energy of about 45-100 (eV) and an areal density of to+3 (cm-2). ) is formed under the conditions of degree.

Next, after removing the resist pattern 23 described above, silicon dioxide (SiO□) is deposited to a sufficient thickness on the entire upper surface of the substrate 11 to form an annealing protective film 277&.

Thereafter, heat treatment is performed for a predetermined period of time at any suitable temperature within the range of, for example, 750 to 900 ("C) to activate the aforementioned channel impurity region 17 and source/drain impurity region 25, As shown in FIG. 2(D), the channel active region 29 and the source/drain active layer tii3
1 is formed. In this figure, the interface of the channel impurity region 17 shown in FIGS. 2(A) to 2(C) is shown with some changes in order to clarify the heat treatment process.

After going through these steps, a step not shown in the diagram
By arranging source electrodes and train electrodes, or other components according to the design,
Complete.

According to the conventional semiconductor device manufacturing method described above, the impurity region is activated while the substrate is covered with the annealing protective film 27. For this reason, during heat treatment for the purpose of activation, the S component constituting the GaAs substrate is prevented from being gasified and desorbed from the surface, and the active region is roughly formed in the self-line with respect to the gate electrode. can do.

(Problems to be Solved by the Invention) However, the above-described conventional method for manufacturing a semiconductor device has various problems as described below.

■No channel! To! In order to implant ions into the impurity regions and source/drain impurity regions and to form the gate electrode, it is necessary to apply a resist material to the surface of the substrate and clean the substrate for the purpose of removing it.

For this reason, if the substrate surface is contaminated by residual resist material or chemicals used for cleaning, and an annealing protective film is applied and heat treatment is performed with these contaminants remaining,
This causes diffusion of the substance into the substrate. Therefore, the gate (
deterioration of Schottky characteristics (e.g., decrease in built-in potential φ8, increase in ideality factor n) and deterioration of FET characteristics (e.g., decrease in mutual conductance, decrease in drain saturation current Idds, decrease in parasitic resistance, etc.). (increase).

Such contamination occurs not only on the substrate surface but also on the surface of the gate electrode, leading to the same problem as the above-mentioned diffusion of contaminants.

Furthermore, when semiconductor devices are manufactured using GaAs as a substrate, it is known that arsenic is removed (gasified) due to the heat treatment described above, which can lead to variations in device characteristics and deterioration. Yes.

■For the purpose of forming a stable Schottky barrier between the gate electrode and the substrate, titanium-tungsten (T1
-W) alloy, tungsten-aluminum (W-Au)
Alloys, tungsten silicide (W-Si), tungsten nitride (WN) or other refractory metals are used. However, these metals have high resistivity and -
For example, in the case of W-Si, it is 180 to 200 (UΩ・cm
), WN has a high resistivity of about 60 to 140 (uΩ-cm).

Therefore, when the gate electrode is composed only of these heat-resistant metals, it is necessary to reduce the resistance of the gate electrode. One way to meet these demands is to increase the thickness of the gate electrode, but depending on the combination of semiconductor materials and heat-resistant metals, stress may occur due to differences in thermal expansion coefficients, which may cause peeling of the gate electrode. There was a problem with bringing it.

In general, increasing the thickness of the heat-resistant metal that constitutes the gate electrode mentioned above has limitations during etching processing such as the reproducibility of dimensions and shapes in forming the electrode, and it is necessary to reduce the resistance by increasing the thickness. There is also the problem of having limitations.

In view of the above-mentioned conventional problems, an object of the present invention is to widely apply it to semiconductor elements made of various semiconductor materials, avoid contamination in the manufacturing process, and realize a low-resistance electrode. An object of the present invention is to provide a method that allows semiconductor devices having excellent characteristics to be manufactured with high yield.

(Means for Solving the Problems) In order to achieve this object, according to the method of manufacturing a semiconductor device of the present invention, a gate electrode forming region of a substrate is formed, on which a gate electrode constituent layer is deposited and a channel impurity region is formed. depositing an insulating mask layer thereon; and at least as described above! The edge mask layer is used as an ion implantation mask, and the source and
After forming the drain impurity region, heat treatment is performed to form a channel active region and source/drain active region, and after electrolytic plating is applied to the gate electrode constituent layer to deposit a plating pattern layer, the above-mentioned insulating mask is applied. forming a first opening in the gate electrode formation region by removing the layer; and forming a second opening in communication with the first opening on the plated patterned metal layer. a step of forming a back-filling layer, a step of forming a low resistance layer by electrolytic plating to backfill at least the first opening described above, and a step of removing the resist batten forming the second opening described above and the plating pattern layer described above. After that, using the aforementioned low resistance layer as an etching mask, the aforementioned gate electrode constituting layer is patterned into a metal layer, and the gate electrode is formed in a self-aligned manner.

(Function) According to the configuration of the method for manufacturing a semiconductor device according to the present invention,
The gate electrode constituent layer functions as a protective film against contamination of the substrate. Further, this gate electrode constituent layer is made of a heat-resistant metal that forms a Schottky barrier with the substrate.

Roughly speaking, in the method of the present invention, the gate electrode constituting layer that functions as a protective film as described above also acts as a base for depositing the aforementioned low resistance layer by electrolytic plating. Specifically, the gate electrode constituent layer in the gate electrode formation region is covered in advance with an insulating mask layer, and in this state, electrolytic plating is selectively performed only on the exposed gate electrode constituent layer,
A plated patterned metal layer is formed. This plating pattern metal layer and resist pattern create a self-aligned (
A low resistance layer is formed. Thereafter, using this low-resistance layer as an etching mask, a gate electrode consisting of two layers, a gate electrode constituent layer and a low-resistance layer, is formed as a self-line.

(Embodiments) Hereinafter, embodiments of the method for manufacturing a semiconductor device of the present invention will be described with reference to the drawings. Note that the drawings referred to in the following description are merely schematic illustrations to facilitate understanding of the present invention, and the present invention is not limited only to these illustrated examples. In addition, in this embodiment, the method of the present invention will be explained by exemplifying the case where it is applied to manufacturing a GaAs-MESFET device.

FIGS. 1A to 1J are explanatory diagrams showing each manufacturing process'@schematic cross-section of a substrate, similar to FIGS. 2A to 2D. Furthermore, in these figures, components having the same functions as those already described are designated by the same reference numerals.

First, about 500 to 200
For example, with a predetermined film thickness within the range of 0 (λ),
A'l is deposited to form a gate electrode constituent layer 33 (FIG. 1(A)).

Next, as in the conventional case, after forming a resist pattern 15 that exposes the element region 13 and covers other regions, Si, which is an n-type impurity, is ion-implanted to form a channel impurity region 17 (see FIG. 1(B)). )).

Here, the conditions for forming the above-mentioned channel impurity region 17 will be explained.

As can be understood from the above description, the gate electrode constituent layer 33 is deposited on the surface of the substrate 11, and ions are implanted through the constituent layer 33. For this reason, Figure 2 (c)
The channel impurity region 17 is formed with an areal density of about 1013 (1013) using a predetermined acceleration energy in the range of about 100 to 400 eV. Form.

Next, after removing the resist pattern 15 described above, the gate electrode forming layer 33 corresponding to the gate electrode forming region 19 is removed.
An insulating mask layer 35 made of, for example, silicon dioxide (SiO□) or any other suitable insulating material is deposited on the surface of the substrate to a thickness of about 10,000 cm (FIG. 1C).

The insulating mask layer 35 can be formed by depositing SiO□ on the entire surface of the gate electrode forming layer 33, and then by photolithography and etching techniques, or by lift-off technique.

Subsequently, after forming a resist pattern 23 having an opening only in a region corresponding to the element region 13, the pattern 23 is
3 and the insulating mask layer 35 as a mask for ion implantation, Si is ion-implanted as indicated by a series of arrows a8 to form the source/drain region 25 (FIG. 1 CD))
.

As already explained with reference to FIG. 1(B), in the method of the present invention, it is necessary to perform ion implantation through at least the gate electrode forming layer 33.

Therefore, when forming the source/drain impurity regions 25, the acceleration energy is 150 to 450 (eV).
A predetermined value within the range of approximately 5 x 1013 areal density
(Si was implanted under the conditions of (1013).

Next, after removing the above-mentioned resist pattern 23, about 8
A heat treatment is performed for about 20 minutes at a temperature of 0.00°C to form a channel active region 29 and source/drain active regions 31 (FIG. 1(E)).

As can be understood from the above explanation and FIGS. 1(B) to (D), the method of this embodiment allows at least the formation of the channel impurity region 17 (see FIG. 1(B)) and the formation of the source/drain regions. Regarding the formation of the impurity region 25 (see FIG. 1(D)), the resist patterns 15 and 25 used for the ion implantation mask are formed on the surface of the gate electrode constituting layer 33. Therefore, FIG. In the heat treatment described with reference to this, it is possible to avoid diffusion of impurities such as a resist material and chemicals related to cleaning into the substrate 11.Furthermore, it is possible to prevent the substrate 11 from being covered with the gate electrode constituent layer 33. By performing the heat treatment in a state where the substrate is in a state where the substrate is heated, detachment of the material constituting the substrate can also be avoided.

Next (Use the above-mentioned gate electrode constituent layer 33 as an electrode for electrolytic plating, and apply a metal such as nickel (Ni) to about 5,000 to +0,000 C on the surface of the constituent layer 33 excluding the gate electrode forming region 19) The metal layer 37 is plated to a predetermined thickness within the range shown in FIG. 1(F) to form a plating pattern metal layer 37.

As can be understood from this figure, the gate electrode constituent layer 33
Of these, a portion corresponding to the gate electrode formation region 19 is covered with an insulating mask layer 35 and cannot be contacted by the plating solution used in electrolytic plating. Furthermore, this insulating mask layer 35 is made of an insulating material, No current flows through the layer 35, and the plating layer does not grow.Therefore, the plating pattern metal layer 37 is selectively deposited only on the surface of the gate electrode forming layer 33, excluding the gate electrode formation region 19. It will be done.

Next, the insulating mask layer 35 is removed using, for example, hydrofluoric acid, and a first opening 39 is formed. As can be understood from this explanation, by providing the plating pattern metal layer 37 with a thickness smaller than that of the insulating mask layer 35, the insulating mask layer 35 can be easily removed. Thereafter, by forming a resist pattern 41 on the above-mentioned plating pattern gold R layer 37, a second opening having a wider opening width than the first opening 39 and communicating with the first opening 39 is formed. 43 is formed (FIG. 1(G)).

As can be understood from this figure, by making the opening width of the second opening 43 larger than that of the first opening 391,
It is preferable to reliably maintain exposure of the gate electrode constituent layer 33 through the first opening 39.

Next, the gate electrode constituent layer 33 in the above-mentioned state is used as an electrode, for example, made of gold (Au!). A low-resistance material is electrolytically plated to form a low-resistance layer 45 as shown in FIG. 1(H).

As can be understood from the above description, according to the method of the present invention, the first opening 39 defined by the plating pattern metal layer 37 and the second opening 43 defined by the resist pattern 41 are formed. Accordingly, the above-described low resistance layer 45 can be formed by electrolytic plating in a self-aligned manner. Masu,
By applying an electric current to the gate electrode forming layer 33 and performing electrolytic plating, the plating pattern metal layer 37 that comes into contact with the plating solution through the first opening 39 and the gate electrode forming layer 33 that is exposed to the gate electrode forming region 19 are formed. Toni low resistance layer 45
is grown to backfill the first opening 39. After this,
The electrolytic plating process is stopped before the second opening 43 is backfilled by the growth of the low resistance layer. Thereafter, the resist pattern 41 and the plating pattern metal layer 37 are removed using conventionally known techniques, thereby obtaining the state shown in FIG. 1(I).

As can be understood from this explanation, the structure facilitates the removal of the resist pattern 41 and the plating pattern metal layer 37 by stopping the plating growth of the low resistance layer 45 before the second opening 43 is backfilled. It has become.

Next, plasma etching technology using, for example, sulfur hexafluoride (SFe) etching gas (as an example of conditions, the applied power is 100 (W) and the pressure inside the reaction chamber is 3 (Pa)).
By using the above-mentioned low resistance layer 45 as an etching mask, only the upper electrode constituting layer 33 in the state shown in FIG. 1(I) is selectively etched away. In this way, the gate electrode 47 consisting of two layers, the low resistance layer 45 and the gate electrode constituent layer 33, is formed in a self-aligned manner (
Figure 1 (J)).

After passing through these steps, a small number of constituent components (not shown) are formed as in the conventional method, and the GaAs-MESFET is completed.

As can be understood from the above description, according to the method of the embodiment of the present invention, each step shown in FIGS. It can be implemented as a remote state. Furthermore, since the gate electrode forming layer 33 that has been exposed during this period is removed by forming the gate electrode 47 described above, it can be understood that the influence of the aforementioned contamination on the semiconductor element can be reduced.

Although the embodiments of the present invention have been described in detail above, it is clear that the present invention is not limited only to these embodiments.

For example, in the embodiment described above, a GaAs substrate is used and ME
The case of manufacturing an SFET has been explained. However, the present invention is not limited only to the above-mentioned embodiments, and silicon (Sl), indium-1 non-(InP)
Alternatively, the same effect as described above can be obtained by a manufacturing process using a substrate made of other semiconductor materials. In particular, MIS (M
etal Insulator Semiconductor
or) Even in the case of a FET, a semiconductor element can be obtained in a similar process by sandwiching an insulating film between the substrate 11 and the gate electrode forming layer 33 in the state shown in FIG. 1(A), for example. can.

In addition, various materials can be used depending on the design of the semiconductor element, for example, when using SiN instead of 7:SiO□ as an insulating mask layer, or using silver (A9) or platinum (Pt)W instead of Au as a plating pattern metal layer. can be used.

It is clear that these materials, dimensions, shapes, distribution relationships, numerical conditions, and other specific conditions may be modified and modified within the scope of the invention.

(Effects of the Invention) As is clear from the above description, according to the method of manufacturing a semiconductor device of the present invention, the gate electrode constituent layer is used as a protective film against contamination of the substrate, and the low resistance layer is formed by electrolytic plating. It also acts as a base for coating. Further, a plating pattern metal layer and a resist pattern are formed with the gate electrode constituent layer in the gate electrode formation region covered with an insulating mask layer, and a low resistance layer is formed in a self-aligned manner. Thereafter, using this low resistance layer as an etching mask, a gate electrode consisting of two layers, a gate electrode constituent layer and a low resistance layer, is formed by self-line.

Therefore, by widely applying the method of the present invention to semiconductor devices made of various semiconductor materials, it is possible to avoid contamination during the manufacturing process and to provide semiconductor devices with excellent characteristics by providing low-resistance electrodes. P8f' can be easily manufactured.

[Brief explanation of the drawing]

1 (A) to (J) are explanatory diagrams showing schematic cross sections of the substrate for each manufacturing process in order to explain the present invention in detail, and FIG. 2 (A) to (D) are explanatory diagrams showing the conventional To explain the technology,
FIG. 1 is an explanatory diagram similar to FIGS. 1(A) to (J) shown in FIGS. 11°...Substrate, 13...Element area +5.23
．． 41...Resist pattern 17...Channel impurity region 19...Gate electrode formation region 21.47...Gate electrode 25...Source/drain impurity region M region 27...
Annealing protective film, 29...channel active region 31...
...Source/drain active region 33...Gate electrode constituent layer, 35...Insulating mask layer 37...Plating pattern metal layer, 39...First opening 43...
-Second opening, 45...Low resistance layer a...Impurity used for ion implantation. (A) 1. Substrate 33: Gate electrode constituent layer Patent applicant Oki Electric Industry Co., Ltd. 19: Gate electrode formation 9 IA area 35, Insulating mask layer Explanatory diagram of an embodiment Fig. 1 An explanatory diagram of a gate electrode embodiment Fig. 1 Figure 2

Claims (1)

[Claims] (1) A step of depositing an insulating mask layer on the gate electrode formation region of the substrate on which the gate electrode constituent layer is deposited and the channel impurity region is formed, and at least the insulating mask layer is used as an ion implantation mask, and forming a source/drain impurity region through the gate electrode constituent layer, and then performing heat treatment to form a channel active region and a source/drain active region; and forming a plating pattern layer on the gate electrode constituent layer by electrolytic plating. After depositing, removing the insulating mask layer to form a first opening in the gate electrode formation region; and forming a second opening on the plating pattern metal layer in communication with the first opening. a step of forming a resist pattern for forming an opening; a step of forming a low resistance layer by electrolytic plating to backfill at least the first opening; and after removing the resist pattern and the plating pattern layer, A method of manufacturing a semiconductor device, comprising the step of patterning the gate electrode constituent layer using the layer as an etching mask and forming a gate electrode with a self-alignment line.