JPH024000B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speech unit editing type speech synthesis device.

More specifically, the present invention provides a circuit that can accurately and easily control the time base conversion ratio of a speech synthesizer.

In general, the time axis conversion ratio (m) of a phoneme editing type speech synthesizer is determined by the clock frequency ( ₁ ) (first clock) for writing the input audio signal into the storage circuit and the clock frequency for reading the input audio signal stored in the storage circuit. The ratio to frequency ( ₂ ) (second clock) is given by m= ₁ / ₂ (1), and an audio signal with a frequency 1/m times that of the input audio signal is reproduced. If the first clock (or the second clock) is fixed to a constant frequency and configured as a variable clock circuit that can vary the frequency of the second clock (or the first clock), the desired time base conversion ratio can be obtained. I can do things.

This type of variable clock circuit used an RC oscillation circuit using a variable resistor and a charging time constant of a capacitor, a variable resistor and a voltage-controlled oscillation circuit, etc.; The variable range changes depending on variations in the initial characteristics, temperature characteristics, aging characteristics, etc.

(b) The relationship between the sliding amount of the variable resistor and the aforementioned time axis conversion ratio (m) is restricted by the sliding amount of the variable resistor and the resistance value change characteristics.

It has the following problems.

The present invention relates to improvements in this problem. Furthermore, if you transpose the accompaniment of a song played on a tape recorder etc. according to your preference and sing along with it, the pitch will be transposed in units of semitones or one tone (12√2 or 6√2 times the frequency). In some cases, it may be more satisfying to musical tastes than transposing in arbitrary units.
The present invention is also applicable to this case, and the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a speech synthesis circuit, in which 101 is an analog audio signal input terminal, 102 is an audio signal output terminal, 1
03 is a first analog-digital conversion circuit (hereinafter referred to as A/D) that converts an analog audio signal into digital data. 104 is a random access memory (hereinafter referred to as RAM) having a storage element of 2 ^A bytes (1 byte is D bits), and depending on the logic level of the control input terminal (LT ₃ ), (a) data input terminals I ₁ - Either store the digital value given to I _D at the address given by address input terminals _A1 to _A , or (b) Store the contents of the address to data output terminals ₁ to _D.
The output is controlled. 106 and 10
8 is a clock generation circuit, and its output ( _R )
and ( _W ) are divided by counters 107 and 109, respectively, and the divided outputs are applied to input terminals of switching circuit 110, respectively.

Now, the clock generation circuit 108 is the RAM 104.
Give the write timing. The output ( _W ) of the clock generation circuit 108 is output from the A-bit frequency dividing circuit 10.
9, and sequentially advances the outputs (W ₁ to W _A ) of the frequency divider circuit 109 .
Reference numeral 110 denotes a switching circuit, which switches the outputs of the frequency divider circuit 109 (W ₁ to W _A ) and the outputs of the frequency divider circuit 107 (R ₁ to R _A ) to the RAM 104 according to the logic level of the control input LT ₁ .
Select output to address input terminal. Reference numeral 111 denotes a latch circuit, which latches input information at this point in time when a clock is applied to the control input terminal _LT2 . 112 is a digital-to-analog conversion circuit (hereinafter referred to as D/A), which converts digital values into analog values. A low-pass filter 113 removes sampling noise from the D/A converted audio signal. 114 is a timing control circuit which inputs the write clock ( _W ) which is the output of the clock generation circuit 108 and generates timing control signals LT ₁ , LT ₂ and LT ₃ . This situation is shown in the time chart of FIG.

Assuming that the frequency dividing circuit 109 advances at the rising edge of f _W , LT ₂ becomes logic level "1" at the rising edge of f _W , and the input information at this time is latched. When LT ₂ becomes a logic bell "0", latch 111 transfers the input to the output.

LT ₁ rises after a certain time delay from the rise of ( _W ), and falls after a certain time delay from the rise of LT ₃ . When LT ₁ is at the logic level "1", the switching circuit 110 outputs the output of the frequency dividing circuit 109 (W ₁ ~
W _A ) is selectively output to the input terminal of the RAM 104.

As shown in the figure, LT ₃ rises with a certain time delay from the rise of LT ₁ . When the logic level of LT ₃ is "1", the RAM 104 stores the output of the A/D 103 at the address given by the output (W ₁ to W _A ) of the frequency dividing circuit 109.

With this configuration, the audio signal applied to the input terminal 101 is converted into a digital value by the A/D 103 and stored in the RAM 104 at the cycle of the read clock ( _W ). Since the frequency dividing circuit 109 is stepped at a cycle of ( _W ), the addresses of the RAM 104 where the audio signal is sampled and stored are continuous. However, the address of ^2A is 0.

The audio signal sampled according to the write clock ( _W ) and stored as a digital value in the RAM 104 is read out according to the read clock ( _R ), is D/A converted 112, and the audio signal is reproduced as an analog signal. The ratio of the write clock ( _W ) to the read clock ( _R ) is the ratio at which the time axis is converted.

Above, we have described a circuit that performs time axis conversion of an audio signal using a digital storage element RAM.However, even if an analog storage element such as a BBD is used as a storage means for an audio signal, the write clock ( _W ) and the readout clock ( _R ), the time axis is similarly converted.

FIG. 3 shows an embodiment of a clock circuit for controlling the time conversion ratio (m) of the present invention. As mentioned above, the time axis conversion ratio (m) is determined by the ratio of the write clock ( _W ) and the read clock ( _R ), so in order to change the time axis conversion ratio (m), one of these two clocks must be used. The clock may be fixed at a constant frequency, and the other clock may be adjusted by a setting value of a variable resistor or the like.

In FIG. 3, 201 is a variable resistor;
Connect one end to constant voltage power supply Vcc, and ground the other end to circuit ground. This sliding terminal 201a is connected to the input terminal VT of the set value detection circuit 202 of the variable resistor. The set value detection circuit 202 is conveniently configured with an analog-digital conversion circuit A/D, and converts the input voltage into a K-bit digital value C ₁ ~
It is converted into C _k and output to the numerical conversion circuit 203.
The numerical conversion circuit 203 is a conversion means that converts the digital values C ₁ to C _k given to the input terminals into a predetermined numerical value series F ₁ to F _N , and is a digital storage circuit such as a read-only memory circuit (hereinafter referred to as ROM). It is convenient to configure the following. Numeric value conversion means 203
Digital values input when configured with ROM
Connect C ₁ to C _k to the address input terminal of the ROM,
The contents of the address are output (F ₁ to _{F N} ). 20
6 is a clock generation circuit, which outputs a clock ( _A ) to a variable frequency divider circuit 204 and a frequency divider circuit 205; 204 is a variable frequency divider circuit, and the clock ( _A ) ROM 203 is input to the clock input terminal T.
The frequency is divided by the value of the output (F ₁ to F _N ) of the clock ( _R ).
Output. That is, the clock ( _A ) is (F ₁ ~ _{F N} )
1 every time you count the number indicated by the digital value of
Outputs two clock pulses ( _R ). A frequency dividing circuit 205 divides the frequency of the clock ( _A ) inputted to the clock input terminal T by a predetermined number to generate a clock ( _W ).

In this way, the predetermined value of the variable resistor is detected, the corresponding numerical series is selected, and the clock ( _A ) can be frequency-divided to create the readout clock ( _R ). The write clock ( _W ) is the clock ( _A ) divided by a predetermined number, and therefore,
The time axis conversion ratio (m) is determined by the clock generation circuit 206.
The variable resistor 201
and only changes in the characteristics of the A/D 202. In general, variable resistors and A/D circuits can have extremely small variations in characteristics, temperature characteristics, changes over time, etc. compared to those of circuit components such as capacitors.
In addition, when the set value of the variable resistor 201 is smaller or larger than a certain value, the memory contents of the ROM 203 can be set so that a numerical series having a certain value is selected, and the variable resistor 201 and the A/
The time axis conversion ratio (m) can be set between predetermined values regardless of the change in the characteristics of D202.

Next, although the relationship between the sliding amount of the variable resistor 201 and the resistance value change characteristic is almost uniquely determined at the manufacturing stage of the variable resistor, the relationship between the sliding amount of the variable resistor 201 and the time axis conversion ratio (m) is It is clear that the ROM 203 can be configured so that the numerical series is selected so as to have a predetermined relationship. Additionally, the numerical series in the ROM 203 can be set so that the frequency to which the read clock ( _R ) is set is selected in units that maintain musical relationships, such as semitones (12√2 times) or one tone (6√2 times). can.

Next, the time axis conversion ratio (m) set by the variable resistor 201 can be (a) set as a fine adjustment amount around 1, (b) set as a variable amount in fine units,
(c) It is possible to have a configuration that can be selected according to preference, such as setting it as a variable amount of musical units. For this purpose, it is necessary to make it possible to select the numerical sequence to be converted by the ROM 203, and a separate numerical sequence specification circuit 21 is required.
0 may be provided to control the ROM 203. In the simplest configuration, the sequence specifying circuit 210 may be configured as a switch, and the address line of the ROM 203 may be controlled by this switch. That is, the signal line from this switch 210 is connected to the upper address of the ROM address line (to which K address lines C ₁ to Ck are input connected from the lower one), and the stored contents of this address are converted into a desired numerical value series. You can fix it as . Note that if the switch 210 is configured to be able to select a plurality of states, it is possible to control the setting states of the variable resistor 201 of the time axis conversion ratio (m) as many as the number of states.

In the above description, the numerical conversion circuit 203 is
Although it has been described as a ROM, part of the functions of an arithmetic control means such as a microcomputer may also be used. In addition, a frequency divider circuit 20 is used to create a write clock ( _W ).
5 is used, but a separate clock circuit may be used. Furthermore, in the above explanation, the time axis conversion ratio was set by varying the readout clock ( _R ), but
It is clear that the same effect will occur even if the clock ( _W ) is varied.

As described above, according to the present invention, it is possible to accurately and easily control the time axis conversion ratio of the speech synthesizer.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a specific embodiment for time axis conversion of a speech synthesizer, FIG. 2 is a timing diagram for explaining FIG. 1, and FIG. 3 is a schematic diagram showing the speech synthesizer of the present invention. FIG. 101...Audio signal input terminal, 102...Audio signal output terminal, 103...A/D converter, 1
04... RAM, 106, 108... Clock circuit, 107, 109... Frequency dividing circuit, 201... Variable resistor, 202... Variable resistor set value detection circuit, 203... Numeric value conversion circuit, 206... Clock circuit, 204... variable frequency divider circuit, 210... number sequence designation circuit.

Claims (1)

[Scope of Claims] 1. An analog input signal is sampled by a first clock and stored in a first storage means, the stored contents of the first storage means are read out based on a second clock, and the analog input signal is sampled by a first clock and stored in a first storage means. In a speech segment editing type speech synthesizer that reproduces an analog input signal whose time axis is converted by a frequency ratio, (a) a variable resistor and (b) a value corresponding to the setting value of the variable resistor is detected. (c) a numerical conversion circuit that converts the variable resistor detection value detected by the variable resistor setting value detection circuit into a predetermined numerical value series, and and the frequency of the second clock is controlled by a numerical value converted by the numerical value conversion circuit. 2. The audio according to claim 1, wherein the numerical conversion circuit is a circuit that performs numerical conversion so that the ratio of the frequencies of the first clock and the second clock is quantized into discrete values in musical scale units. Synthesizer. 3. The speech synthesis device according to claim 1, wherein the numerical conversion circuit is a circuit that performs numerical conversion so that the frequency ratio of the first clock and the second clock does not become less than or more than a predetermined value. 4. The speech synthesis device according to claim 1, wherein the numerical value conversion means is a circuit that uses a value corresponding to the variable resistor detection value as an address, reads out the stored content of the second storage means, and converts it into a numerical value. 5. The speech synthesis device according to claim 1, wherein the first clock (or second clock) is provided by an output of a frequency dividing circuit that divides a predetermined clock by a value converted by the numerical value conversion circuit. . 6. The first clock (or second clock) is provided by the output of a frequency dividing circuit that divides a predetermined clock by the value converted by the numerical value conversion circuit, and
2. The speech synthesis apparatus according to claim 1, wherein the clock (or the first clock) is provided by an output of a frequency dividing circuit that divides the frequency of the predetermined clock by a predetermined value. 7. Sample the analog input signal using the first clock and store it in the first storage means, read out the stored contents of the first storage means based on the second clock, and set the time axis based on the ratio of the first clock and the second clock. A speech segment editing type speech synthesis device that reproduces an analog input signal that is converted into a speech segment includes (a) a variable resistor, and (b) a setting of the variable resistor that detects a value corresponding to the setting value of the variable resistor. a value detection circuit; (c) a number sequence specification circuit for specifying a conversion sequence; and (d) converting the set value detected by the set value detection circuit of the variable resistor into a numerical sequence specified by the number sequence specification circuit. (e) a variable frequency dividing circuit that divides a predetermined clock by the numerical value converted by the numerical value converting circuit; Alternatively, the speech synthesizer is used as a second clock, and the sequence of ratios of the first clock and the second clock is controlled by the sequence designation circuit. 8. Claims characterized in that the sequence designation circuit controls whether or not the sequence of numbers that can take the ratio of the frequencies of the first clock and the second clock is a quantum sequence of discrete values in units of musical scales. 7. The speech synthesis device according to 7. 9. The speech synthesis device according to claim 7, wherein the sequence designation circuit controls whether or not the possible sequence of the frequency ratio of the first clock and the second clock is a very small amount in the vicinity of 1. .