JPH024013B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program sequence control method, and more particularly, to a method for controlling the execution order of a plurality of independent programs when the same processing device operates them in a time-sharing manner (time slice). It is related to.

Attempts to run multiple independent programs in a time-sharing manner under the control of the same processing unit are difficult to implement when controlling a group of relatively small and slow peripherals or when there are many parallel tasks to be processed at the same time. In some cases, it is increasingly being adopted as an effective means. This is because (i) independent programming is possible, so the number of steps required to create a program can be relatively small; (ii) Many programs can be shared, saving memory.
(iii) It has the advantage that the amount of hardware is smaller than creating a processor for independent programs, and as long as the processing capacity is satisfied, the system can be created economically in a short period of time.

However, since all programs are executed on the same processing device, uniform time-sharing control of each program may not be enough to satisfy the time allocation for programs that require a large amount of processing at one time. cannot be done, and the limits of processing are reached. Therefore,
A method of dynamically changing the time slice ratio for each program has been considered, and has been implemented in some cases, but the conventional method requires (i) complicated wiring logic and an increase in the amount of hardware;

(ii) There is little flexibility for systems with different operating modes.

(iii) It is difficult to take into account sequence constraints caused by hardware limitations, such as prefetching and delays.

It has the following disadvantages.

An object of the present invention is to alleviate the above-mentioned conventional drawbacks, and to provide a program sequence control method that uses less hardware, provides flexibility in control, and easily incorporates hardware limitations. It is in.

Now, in recent years, there has been a remarkable improvement in the density of memory, and memory devices with 10 bits or more in the address direction are becoming inexpensive and easily available. The present invention uses such a memory, writes various combination program identification codes corresponding to each time slice in the memory in advance, and uses a binary counter and a binary counter updated every instruction cycle as the address of this memory. , reads a desired program identification code from the memory using a time slice execution allocation change request signal, for example, a busy signal of a program at each level, and uses this program identification code to determine the program to be executed in the next instruction cycle. It is characterized by this.

Next, one embodiment of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram of an instruction reading section within a processing device. In FIG. 1, reference numeral 1 denotes a program identification code generation circuit, which generates an identification code for the next program to be executed for each instruction cycle and provides it to the instruction address register group 2. The instruction address register group 2 consists of a plurality of instruction address registers in one-to-one correspondence with a plurality of programs, and each instruction address register has the following information:
The address of the next instruction to be executed in the program (instruction address) is stored. Instruction address register group 2 is specified by the program identification code above.
The instruction address register corresponding to the program indicated by the program identification code is selected, and the instruction address is read out and latched into the address register 3 of the control storage device 4. Based on the contents of the address register 3, an instruction is read out from the control storage device 4, latched into the instruction register 5, and executed. At the same time, the contents of the next instruction address field of the instruction register 5 are registered in the selected instruction address register in the instruction address register group 2. Next, the program identification code generating circuit 1 outputs the identification code of the next program to be executed, and the above-described operation is repeated.

The present invention is applied to the program identification code generation circuit 1 shown in FIG.

FIG. 2 shows an embodiment of a program identification code generation circuit to which the present invention is applied, and is an example in which four independent programs A, B, C, and D are operated in a divided manner. In Figure 2, 10 ₁ to 1
₀₄ is a busy flip-flop for each program A, B, C, and D, and its output (busy signal) 11 is used as a time slice execution allocation change request signal. These busy flip-flops 10 ₁ ~
₁₀₄ is designed to be coupled to the system busbar or to be set and reset by wiring logic. 13 is a 4-bit binary counter,
Count signal 12 that occurs once during an instruction cycle
It is updated sequentially. Reference numeral 15 denotes a memory element, which uses the outputs 11 of the busy flip-flops 10 ₁ to 10 ₄ and the output of the binary counter 13 as addresses to read out the identification code of the program to be executed in the next instruction cycle, and stores the program identification code. Latch to register 16. The output of the register 16 is applied to the instruction address register group 2 in FIG. 1, and is used to select the instruction address register of the program indicated by the program identification code.

FIG. 3 shows an example of the contents stored in the memory element 15. For example, when all the busy flip-flops 10 ₁ to 10 ₄ are “0”, the count values of the counter 13 are 0, 1, 2, . . . D, E, F.
For, the program is A→B→C→D→A→B
The identification code of each program is written in the memory element 15 so that it can be executed equally as follows. Also, for example, if program D is busy,
When flip-flop ₁₀₄ is “1”,
The identification code of the program is written so that program D can be executed with sufficient frequency, such as A→D→B→D→C→D→.... That is, the program identification code is written in the memory element 15 in correspondence with the busy state of each program so as to satisfy the capability required by the system.

In actual execution, the memory element 15 is 2
The program identification signal to be executed next is output in sequence according to the value of the value counter 13, but at this time, when the busy flip-flops 10 ₁ to 10 ₄ are in the state, those sequences function as if they had been modified. However, processing is executed frequently enough for programs with heavy loads.

With the configuration as described above, the following effects can be obtained with the present invention.

1 The degree of integration of memory devices has become extremely high in recent years, and the number of programs for other peripheral ICs has increased to 8.
~16 can be realized with a few ICs, and the amount of hardware increase is small.

2. By rewriting the contents of the memory, it is possible to adapt it to various types of systems.

3. Hardware limitations can be factored into the programming of memory contents. (for example,
(Restrictions such as not allowing the same program to continue for more than two cycles) 4 Program busy flip-flops, etc.
Since the execution frequency changes only by turning ON/OFF, program control is easy.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the instruction reading unit in the processing device, FIG. 2 is a block diagram of the program identification code creation circuit of FIG. 1, which shows an embodiment of the present invention, and FIG. FIG. 2 is a diagram showing an example of contents stored in a memory element of FIG. ₁₀₁ to ₁₀₄ ...Program busy flip-flop, 13...Binary counter, 15...Memory element,
16...Program identification code register.

Claims (1)

[Claims] 1. An information processing device that operates multiple independent programs in a time-sharing manner includes a memory element that stores in advance multiple sets of program identification code strings with different program execution assignments, and a circuit that issues a program execution assignment change request signal. , a counter that is incremented every instruction cycle, one of the plurality of program identification code strings in the memory element is selected by the change request signal, and each time the counter is incremented, the counter is incremented every instruction cycle. A program sequence control method characterized by sequentially reading out each program identification code of a selected program identification code string, and specifying a program to be executed in the next instruction cycle using the program identification code.