JPH0240640Y2 - - Google Patents

Description

[Detailed explanation of the idea] (Technical field) The present invention relates to random access memory.

(Prior Art) Conventionally, as a random access memory, the number of words and the number of bits were fixed, so the memory capacity was fixed for the same product.
Therefore, in products controlled by the same manufacturing process,
A wide variety of memory types have been developed in response to modern uses, which often require various numbers of words and bits, and users have prepared and used each of them. For this reason, it is difficult for users to purchase, handle, and handle a wide variety of products in small quantities.
There are drawbacks such as high costs for managing inventory, device manufacturing, etc., and high costs because it is difficult for memory manufacturers to mass produce.

(Objective of the invention) An object of the invention is to provide a random access memory having multiple types of memory functions by eliminating the above drawbacks.

(Structure of the invention) The random access memory of the invention includes a plurality of memory cells, a plurality of word lines for selecting memory cells in word units from the plurality of memory cells, and a memory cell selected from the plurality of memory cells. A plurality of memory cell groups each comprising a plurality of bit lines for inputting and outputting cell data, and corresponding word lines are commonly connected to each other, the plurality of memory cell groups, and the plurality of word lines. an X address decoder that selects one of the memory cell groups, and a plurality of Y address decoders that are provided corresponding to each of the memory cell groups and selectively control the bit lines of the corresponding memory cell group in accordance with a first switching signal; A bit number switching circuit comprising a plurality of gates provided between corresponding bit lines of each memory cell group and connecting and disconnecting the respective bit lines according to a second switching signal; The control circuit includes a bit number switching signal for determining the number of bits to be processed and a control circuit that receives a specific address signal and generates the first and second switching signals.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of the present invention. This embodiment includes a plurality of memory cells, a plurality of word lines for selecting memory cells in word units among the plurality of memory cells, and a plurality of word lines for inputting and outputting data of a selected memory cell among the plurality of memory cells. Bit line (DI ₁ to DI _n or DI _1a to DI _na )
a plurality of memory cell groups, each of which has a plurality of memory cells, and corresponding word lines are commonly connected to each other.
RAM ₁ , RAM ₂ , an X address decoder XD for selecting one of _the plurality of word lines _, and a first
bit lines ( _{DI 1 to DI n} or
A plurality of Y address decoders Y ₁ and Y ₂ selectively control DI _1a to DI _na ) and memory cell groups RAM ₁ and RAM _2.
Each corresponding bit line DI ₁ −DI _1a , ~, DI _n −
A plurality of gates G ₁ to _{G n} are provided between DI _na and connect or disconnect each bit line DI ₁ to _{DI 1a} , DI _n to DI _na according to a second switching signal.
A bit number switching circuit 1 equipped with a bit number switching circuit 1, a bit number switching signal for determining the number of bits to be processed in parallel, and a specific address signal A _o are inputted to generate the first and second switching signals. control circuit 2;
Bit number switching signal and address signal A ₀ to A _o
and an address buffer circuit AB that holds and outputs.

Here, the bit number switching circuit 1 is a p-channel insulated gate field effect transistor and an n-channel insulated gate field effect transistor inserted between the bit lines DI ₁ and DI _1a to be combined between the bit lines DI _n and DI _na , respectively. It consists of gates G ₁ to G _n which are connected in parallel. The control circuit 2 also controls the bit number switching signal input to the address buffer circuit AB.
An inverter G _c whose input is AS and whose output is connected to one of the control gates of gates G ₁ to _{G n} , the output of this inverter G _c and an address signal A _{o are} input, and its output is input to a Y decoder Y ₁ . NAND gate
G _a , the output of this NAND gate G _a and the inverter
A NAND gate G _b whose input is the output of G _c and whose output is input to Y decoder Y ₂ , and an inverter G whose input is the output of inverter G _c and its output is connected to the control gate of one of the gates G ₁ to G _n . It consists of _d .

In the figure, R/WSEL ₁ and R/WSEL ₂ are read/write selectors, WB is write buffer,
R/WC is read/write controller, CG is chip select gate, SA is sense amplifier, RB
is the read buffer, is the chip select signal,
WE is a write enable signal.

Next, the operation of this embodiment will be explained.

In this embodiment, a plurality of data inputs DI ₁ ′ to DI _n ′,
DI _1a ′ to DI _na ′ allows multiple outputs DO ₁ to DO _n ,
Multiple bit lines to obtain DO _1a ~ DO _na
The present invention is applied to a random access memory having DI ₁ to _{DI n} and DI _1a to DI _na , and a case will be explained in which the number of bits is halved and the number of words is doubled instead.

Gates G ₁ to G _n are connected between bit lines DI ₁ and DI _1a to bit lines DI _n and DI _na , respectively.
These gates G ₁ to _{G n} are controlled by the bit number switching signal via inverters G _c and G _d so that they are turned on when the bit number switching signal is at a low level, and turned off when it is at a high level. and the gate
When G ₁ to _{G n} are on, the bit line DI ₁ and the bit line DI _1a to the bit lines DI _n and DI _na are brought into conduction by the gates G ₁ to _{G n} , respectively. Therefore data output
DO ₁ , DO _1a to DO _n , and DR _na also appear to have the same data output, and the number of bits is halved.

Further, in order to make the word numbers corresponding to these bit lines consecutive so that the word numbers are doubled by pairing the bit lines, Y decoders Y ₁ and Y ₂ are separated corresponding to the bit numbers. Here, the decoder side that is after the word number is Y decoder _Y2 ,
Address signals A ₀ to _{A o-1} control the same address number to Y decoders Y ₁ and Y ₂ , and the last address signal A _o identifies Y decoders A ₁ and A ₂ . That is, when the bit number switching signal is low level, the address signal A _o is low level, the output of NAND gate G _a is high level, the output of NAND gate G _b is low level, Y decoder Y ₁ is selected, and the opposite is selected. When address signal _Ao is high level, Y
Decoder _Y2 is selected. Thus, the number of words is doubled.

Normally, when used as an m+ma bit memory where data inputs DI ₁ ' to DI _n ' and DI _1a ' to DI _na ' are used independently, when the bit number switching signal is set to high level, the address signal A _o Regardless, Y decoders Y ₁ and Y ₂ are selected at the same time, so
By selecting addresses using address signals A ₀ to _{A o-1} , Y decoders Y ₁ and Y ₂ are controlled at the same level, and memory cell groups RAM ₁ and RAM ₂ are read/written as one unit.

Next, when dividing the memory cell group into halves and using the number of bits in half, set the bit number switching signal to low level and set the address selection signal to
Address control is performed using A ₀ to A _o . By setting the bit number switching signal to low level, Y decoders _Y1 and _Y2 are switched to Y decoder Y1 and _Y2 by address signal _Ao .
The word number can be a serial number that is the sum of _{the memory cell groups RAM 1 and} RAM ₂ . Also gates G ₁ to _{G n}
The bit line connected with is the bit number switching signal.
Since AS is at a low level, the gates G ₁ to _{G n} are turned on, and the bit lines DI ₁ and DI _1a to _{DI n} and DI _na are brought into conduction with each other.

Here, memory cell groups RAM ₁ and RAM ₂ connected to bit lines DI ₁ and DI _1a are connected to Y decoder Y ₁ ,
Since they can be separated from each other by _Y2 , this embodiment can be used as a memory with half the number of bits but twice the number of words.

In addition, in the above embodiment, the number of bits is halved,
Although the case where the number of words is doubled has been described, the present invention is not limited to this, and can also divide bit lines and multiply word lines.

(Effects of the invention) As explained above, since the random access memory of the invention has the above configuration, it has the effect that one type of memory can be used for multiple memories. There is. Therefore, the user does not have to prepare different types of memory depending on the application, which improves efficiency in order planning and inventory management, and the memory manufacturer can reduce costs by mass producing a small number of products.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention. 1... Bit number switching circuit, 2... Control circuit,
A ₀ , A ₁ , ..., A _o-1 , A _o ...address selection signal,
AB...address buffer circuit,...bit number switching signal, CG...chip select gate,
...Chip select signal, DI ₁ ~ DI _n , DI _1a ~
DI _na ...Bit line, DI ₁ ′ to DI _n ′, DI _1a ′ to DI _na ′...
…Data input, DO ₁ ~ _{DO n} , DO _1a ~ DO _na … Data output, G ₁ ~ G _n … Gate, G _a , G _b …
NAND gate, G _c , G _d ...inverter,
RAM ₁ , RAM ₂ ...Memory cell group, RB...Read buffer, R/WSEL ₁ , R/WSEL ₂ ...Read/Write selector, R/WC...Read/Write controller, SA...Sense amplifier, WB...
...Write buffer, ...Write enable signal, XD...X address decoder, Y ₁ , Y ₂ ...Y
address decoder.

Claims (1)

[Scope of utility model registration request] A plurality of memory cells, a plurality of word lines for selecting memory cells in word units among the plurality of memory cells, and a plurality of bit lines for inputting and outputting data of the selected memory cell among the plurality of memory cells, respectively. a plurality of memory cell groups in which corresponding ones of the word lines are commonly connected to each other; an X address decoder that selects one of the plurality of memory cell groups and the plurality of word lines; A first memory cell is provided corresponding to each memory cell group.
a plurality of Y address decoders for selectively controlling the bit lines of the corresponding memory cell groups according to a second switching signal; A bit number switching circuit equipped with a plurality of gates that connect and disconnect the bit lines, a bit number switching signal for determining the number of bits to be processed in parallel, and a specific address signal are inputted to the circuit. 1st and 2nd
and a control circuit that generates a switching signal.