JPH0240734A - Program development support device - Google Patents

Abstract

PURPOSE:To execute a target repair program without correcting a processing program itself direction by adding an address decision part, a correction address generation part, a correction code memory, and an end address detection part to a conventional program developing device. CONSTITUTION:A main computer 100 controls gates A111 and B112 and a code memory 106, a data memory 107, and other blocks are connected to a microprocessor 101. The address decision part 102 reads the start address of a program to be corrected out of the memory 106, compares addresses of instructions that the processor 101 executes to detect address, and reads correction codes out of the correction memory 104. The end address detection part 105 detects the end of the correction program and restores it to the original program through gates 113 and 114. Consequently, the target correction program is executed without correcting the processing program itself to perform program development supporting operation.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a processing program development support device for a microprocessor, and more particularly to a device that can easily modify and execute a processing program.

Conventional technology During the development process of microprocessors, it is necessary to have the CPU run a program that performs a specific process, check the operating status of the CPU, and debug if any problems occur with the program. come. A block diagram of a conventional device that performs such processing is shown in FIG.

This device consists of a host computer 1 that controls the entire device.
00, a microprocessor 101 that is a target for executing a predetermined processing program, and a microprocessor 1
a code memory 106 that stores instructions to be executed by 01;
Data memory 107 for storing processing target data and results
are connected via an address bus 1000 and a data bus 110.

The host computer 100 controls the gate A11l and the gate B112 using the memory access right control signal 124, and switches whether the code memory 106 and the data memory 107 are connected to the host computer 100 or the microprocessor 101. Further, the host computer 100 uses the reset signal 125 to specify whether the microprocessor 101 is in a reset state or a reset release state.

In addition, the host computer 100 opens the gate A11l and closes the gate B112 using the memory access right control signal 124, and loads the program to be executed by the microprocessor 101 into the code memory 106 and the data to be processed into the data memory 107. . The host computer 100 also includes a microprocessor 10.
After 1 executes the program, the result is stored in the data memory 10.
Read from 7.

To cause the microprocessor 101 to execute a processing program, the host computer 100 first loads the program to be executed by the microprocessor 101 and the data to be processed into the code memory 106 and data memory 107, respectively, and then switches the memory access right control signal 124. (game) Close ALII and open gate B112 to allow the microprocessor 101 to access the memory. Thereafter, when the reset signal 125 is released, the microprocessor 1'01 starts executing the processing program in the code memory 106. After executing the program, the host computer 100 activated the reset signal 125 and obtained the results of the program executed by the microprocessor 101.

Problems to be solved by the invention are not limited to the development of processing programs for microprocessors;
During the development stage of a program, it is very often necessary to actually run it and debug it.

In the conventional apparatus described above, when it becomes necessary to modify the processing program, for example, when it is desired to modify the program in the part of FIG. 11(a) to the program in FIG. 11(5), the program to be modified ( If the size (number of bytes) of the modified program is larger than the modified program (hereinafter referred to as the modified program), then the program after the modified program, that is, ro073H in the case of Figure 11 (C) (H is hexadecimal representation) Since it was necessary to rearrange subsequent programs or go back and modify the source program before it was assembled or compiled, this work was time consuming and inefficient.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a program development support device that can execute a desired modification program by simply inputting the program to be modified from a host computer into a modification code memory without changing the processing program itself. It is.

Means for Solving the Problems The program development support device of the present invention includes an address determining section that determines an address to be modified in a program executed by a microprocessor, and an address of the program to be modified based on a control signal from the address determining section. a modification address generation unit that stores a modification program that is executed when the modification address generation unit outputs address information; and a modification address generation unit that detects an end address of the target modification program and generates a modification address from the modification address generation unit. and an end address detection section that prohibits address output.

Effects As described above, according to the present invention, an address determination section, a modified address generation section, a modified code selection section, and an end address detection section are added to the conventional program support development apparatus.

With this configuration, the modified program is stored in the modified code memory without directly modifying the processing program itself, while the address of the modified portion of the original program is detected by the address determination section. Thus, when the address discrimination section detects the address of the modified portion of the program, the modified program is read from the modified code memory and executed, and the end address detection section detects the end of the modified program and returns to the original program. This allows the target modified program to be executed without directly modifying the processing program itself.

Embodiment Next, an embodiment of the program support development apparatus according to the present invention will be described with reference to the accompanying drawings.

Embodiment 1 A block diagram of one embodiment of a program support development apparatus according to the present invention is shown in FIG. In the figure, a host computer 100 that controls the entire device, a microprocessor 101, and an address determination unit that compares the start address of a program to be modified with the address of an instruction executed by the microprocessor 101 and outputs an address determination signal 120. 102, a modified address generation section 103 that outputs the address information of the modified program to the address bus B109, a modified code memory 104 that stores the code of the modified program, and an end address detection section 105 that detects the end of the modified program. The code memo January 06 that stores the processing program including the modified program and the data memory 107 that stores the processing target data and results are connected to the address bus AlO3, the address bus B109, and the Oyohi data path 1.
They are connected to each other via 10.

Here, the modified code memory 104 and the code memory 10
6 uses a memory with chip select.

That is, the code memory 106 has an address “0XXX
Selected by HJ and modified code memo! It is assumed that J 104 is selected at an address other than that.

Note that a first gate 113 is set between the address AlO3 and the address B109, and a first gate 113 is set between the address AlO3 and the address B109.
A second gate 114 is set between the address bus B109 and the address bus B109, and controls the derivation of the corrected address data and the address data during normal program execution to the address bus B109.

The flip-flop A117 outputs 1 depending on the state of the address determination signal 120 and the end address detection signal 126 which is the output signal of the end address detection section 105.
27, and the flip-flop 8118 outputs the first gate control signal 121 as a signal obtained by delaying the flip-flop output 127.

In addition, the host computer 100 uses the memory access right control signal 124 to control the gate A111 and the gate B).
112, code memory 106 and data memory 1
07 and other blocks are connected to the host computer 100.
In addition to having the function of switching whether to connect to the microprocessor 101 or the microprocessor 101, the reset signal 12
5 is used to specify whether the microprocessor 101 is in a reset state or a set release state.

FIG. 2 is a block diagram showing in detail the configurations of address discriminator 102, corrected address generator 103, and end address detector 105 in FIG. 1.

The address determination unit 102 is a latch A that is initialized with a value obtained by subtracting "IH" from the address value at which the correction program is inserted.
201, and a comparator A200 that compares the address values of the latch A201 and the address bus AlO3 and outputs an address determination signal 120.

Further, the modified address generation unit 103 is composed of a modified address pointer 202 that stores a modified address value, and an incrementer 203 of the modified address pointer 202.

The end address detection unit 105 includes a latch B2O5 that is initialized with the end address value of the modified program, and a latch B2O.
Comparator B2 compares the value of 5 with the address data of address bus B and outputs the end address detection signal 126.
04.

Using the program development support device shown in FIGS. 1 and 2, the program in the code memory 106 including the modified program shown in FIG. 3(a) is replaced with the modified program shown in FIG. 3(b). The operation when executed will be explained below.

However, in this embodiment, the latch A201 stores r006PHJ, which is the value obtained by subtracting "IH" from the correction start address value at which the correction program is inserted, and the correction address pointer 202 stores the start address value at which the correction program is stored. The address value rlooo HJ is stored, and the end address value r100 of the correction program is stored in the latch B2O5.
It is assumed that 6HJ is stored.

First, from the host combinator 100, the code memory 10
6 and the data memory 107 respectively, load the processing program and the data to be processed, respectively, as shown in FIG. 3 (5).
Write the modified program to the modified code memo IJ104. Thereafter, the host combinator 100 switches the memory access right control signal 124, closes the game) A11l, opens the game) B112, and releases the reset signal 125, thereby causing the microprocessor 101 to read the memory access right control signal 124 stored in the code memory 106. roooo in Figure 3 (a)
Start execution of the program starting from HJ.

The following description will be made with reference to FIGS. 4 and 5. Figure 4 shows the address bus AlO3 and address bus B10 used when the address output of the correction program starts.
9, address determination signal 120, first gate control signal 12
1, second gate control signal 122, address change signal 12
3. End address detection signal 126, flip-flop A
5 is a timing chart of the output 127 of the correction program, and FIG. 5 shows the address bus B 109, address judgment signal 120, first gate control signal 121, second gate control signal 122, address change signal 123, and end at the end of address output of the modification program. 3 is a timing chart of the address detection signal 126 and the output 127 of flip-flop A.

At the start of the program, the microprocessor 101 transfers address information r0000 HJ to the address bus AlO3.
This address information is output by comparator A20.
0 and is compared with the old initial value ro06FHJ of latch A2. In this case, since the two values do not match, the address judgment signal 120 becomes "0", and the first gate control signal 121
is "0" and the second gate control signal 122 is "1", so the first gate 113 is open and the second gate 114 is closed, so the microprocessor 101 reads the code memory 106.
Execute the program within.

From then on, execution continues in the same way up to ro06FHJ, but when the next address r006FHJ is output to the address bus AlO3, the comparator A200 outputs the address judgment signal 1 because it matches the value stored in the latch A201.
20 is set to "1" and output, flip-flop A117
is set. Subsequently, the first gate control signal 121 becomes "1" at the timing when the microprocessor 101 outputs the next address, so the second gate control signal 122 becomes "1".
becomes "0", the first gate 113 is closed, and the second gate 11
4 opens. Therefore, the address data r1000HJ stored in the modified address pointer 202 is output to the address bus B109, and the operation code of the program in the modified code memory 104 is fetched.

Furthermore, upon the next rise of the address change signal 123, the incrementer 203 updates the value of the modified address pointer 202, and the address data "1001H" is output to the address bus B109. microprocessor 1
01 similarly executes the program in the modified code memory 104 up to r1004HJ.

Here, select the desired hotfix program "BB", "00", "
A branch instruction is added to return to the original processing program address immediately after completion of "CO", "53", and "9D". In other words, the address r1005 HJ and r1006 HJ of the modification program have content "6B",
rFO” (JMP 0073 H).

As a result, the address r1006 is input from the second gate 114.
When HJ is output to the address bus B109, the comparator B204 in the end address detection unit 105 selects the address value '1006 stored in the latch B2O5.
By comparing HJ with the end address of the branch instruction and setting the modified program end detection signal 126 to "1", the flip-flop A117 is reset, and the first gate control is subsequently performed at the timing when the microprocessor 101 outputs the next address. The signal 121 becomes "0". As a result, the first gate 113 opens and the second gate 114 closes, thus prohibiting the modified address data from being output to the address bus B109, and r0073 HJ of the code memory 106 according to the address output by the microprocessor 101 by executing the branch instruction. Returns control to execution of the processing program from.

The hardware configuration described above makes it possible to easily execute a modification program without changing the processing program itself.

Example 2 A second example of the present invention will be described. Note that in this implementation, a case will be explained in which corrections are made at multiple locations (three locations).

The overall configuration is the same as that in Figure 1, except for the address discrimination section 1.
02 and the modified address generation section 103 and end address detection section 105 are different. First, let me explain this point.

FIG. 6 is a block diagram of the address discrimination section 102 and modified address generation section 103' in this embodiment, and FIG. 7 is a block diagram of the end address detection section in this embodiment.

In FIG. 6, the address determination unit 102 stores latches 1-A 604, 1-B 605, and latches 1-A 604 and 1-B 605 in which values obtained by subtracting "IH" from each address value into which a modification program is to be inserted are written.
Latch 1-C606, gate 1-A600 that controls the derivation of the address value of each latch, gate 1-B601, gate 1-C602, the values derived from each latch, and the address output to address bus 1-AlO3. A comparator A200 that compares the information, and a gate control signal A620 and a gate control signal B621 that control the opening and closing of each gate.
, and a gate control counter 603 that outputs a gate control signal C622. The modified address generation unit 103 also includes a latch 2-A607, a latch 2-8608, and a latch 2-C609 that store each start address value of the modified program, and a gate 2-A610 that controls derivation of the address value of each latch. It is composed of a gate 2-8611, a gate 2-C612, a modified address pointer 202, and an incrementer 203 for the modified address pointer 202.

Further, in FIG. 7, the end address detection unit 105 stores the end address values of each modification program in latch 3-A704, latch 3-B705, and latch 3-C7.
06 and gate 3 that controls the derivation of the address value of each latch.
-A701, Gate 3- B702, Gate) 3-C70
3, values derived from each latch, and address bus 1-81
09 and a comparator B204 that outputs an end address detection signal 126 by comparing the address information outputted at 09.

Using the program development support apparatus shown in FIGS. 6 and 7, the modified program shown in FIG.
The following describes the operation when the modified program shown in ) is changed and executed.

However, in this implementation, latch 1-A604, latch 1-B605, and latch 1-C606 have roolF HJ, roOFF HJ, and r03FF H, respectively.
J is stored, and latch 2-A607, latch 2-
8608 and latch 2-C609 have [1000HJ and "20
00 HJ, r3000 HJ are stored, and latch 3-A704, latch 3-B705, latch 3-C
706, r1004 HJ, r2005 HJ, r3003 as the end address values of the modified program, respectively.
It is assumed that HJ is stored.

As in the previous embodiment, first, the host computer 100
Load the processing program and data to be processed into the code memory 106 and data memory 107, respectively,
Figure 8 0)) Corrected code memory 10
Write in 4. Thereafter, the host computer 100 switches the memory access right control signal 124 to
(close game) open B112 and reset signal 12
5, the microprocessor 101 executes the code stored in the code memory 106, as shown in FIG. 9(a).
Start executing the program starting from roooo HJ. At the same time, the value of the gate control counter 603 is initialized to "0" by the reset signal 125, and only the gate control signal A620 becomes "1", so that the value of the gate control counter 603 is initialized to "1".
, Gate 2-A610, Gate 3-A701 are opened, and the initial value of each latch is derived.

At the start of the program, the microprocessor 101 sends address information r0000 to the address bus-A108.
HJ, this address information is compared by comparator A200 with the value ro01F HJ derived from latch 1-A604. In this case, since they do not match, the address judgment signal 120 is "0", the first gate control signal 121 is "mouth", and the second gate control signal 122 is "1".
Therefore, the first gate 113 is opened and the second gate 114 is opened.
closes. Thus, microprocessor 101 executes the program in code memory 106.

Thereafter, the process is sequentially executed in the same manner up to ro01F HJ.

Next address '0OIF HJ is address bus-A10
Since the address values match, the comparator A200 sets the address determination signal 120 to "1" and outputs it, so the flip-flop A117 is set. Subsequently, the first gate control signal 121 becomes "l" at the timing when the microprocessor 101 outputs the next address.
", the second gate control signal 122 becomes "0", so the first gate 113 is closed and the second gate 114 is opened, so the address data r100 is transferred from the corrected address pointer 202.
0HJ is routed to address bus-B 109 and the opcode of the program in modified code memory 104 is fetched. Furthermore, at the next rising edge of the address change signal 123, the incrementer 203 changes the address pointer 20 to the corrected address pointer 20.
Change the value of 2 and update the address value rlooIH
J is output to address bus -8109. From now on, the microprocessor 101 similarly executes the program in the modified code memo 'J 104 up to rlo04HJ.

When the final address r1004HJ of the branch instruction is output to the address bus-8109, the address bus-810
Since the address data of 9 and the value of latch 3-A704 in the end address detection section 105 match, the end address detection signal 126 becomes "1", so the flip-flop 117 is reset and the address information of the correction program is Control is returned to the execution of the processing program from r0022 HJ of the code memory 106 by inhibiting it from being routed to the address bus A108 until the next modification program insertion address is reached, i.e. until address roOFF HJ. The programs in 106 are executed sequentially.

The value of the gate control counter 603 is updated at the fall of the first gate control signal 121, and the start address of the program to be modified next, the start address of the modification program, and the end address of the modification program are stored. The gate control signal B621 that controls derivation of the address value from the latch becomes "1".

From now on, address rQQFF of code memory 106
HJ, r03FF Also in HJ, the microprocessor 101 executes the modification program and processing program in the same way as in the above case.

By using the present invention, even if a program needs to be modified at multiple locations, the program can be easily modified and executed.

As described in detail, the present invention adds an address determination unit, a modified address generation unit, a modified code memory, and an end address detection unit to a conventional program development apparatus, thereby allowing processing programs to be developed without directly modifying the processing program itself. , the effect is that you can run the desired fix.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the program development support device according to the present invention, and FIG. 2 is a block diagram of a first embodiment of the program development support device according to the present invention.
FIG. 3 is a detailed block diagram of the address discrimination unit, modified address generation unit, and end address detection unit according to the embodiment.
FIG. 4 is a diagram showing an example of the arrangement of a modified program and a modified program in program development using the embodiment.
5 is a timing chart of each part at the start of address output of the modified program in the example of program development using the embodiment; FIG. 5 is a timing chart of each part at the end of address output of the modified program in the example shown in FIG. 4; FIG. 6 shows the second part of the program development support device according to the present invention.
FIG. 7 is a detailed block diagram of the address discrimination section and the corrected address generation section in the embodiment of the present invention.
FIG. 8 is a block diagram of the end address detection unit in the embodiment of the present invention.
FIG. 9 is a diagram showing an example of the arrangement of a modified program and a modified program in program development using the embodiment.
10 is a block diagram of a conventional program development support device. FIG. 11 is a diagram of a program using a conventional program development support device. It is a figure which shows an example of a correction. [Main reference numbers] 100...Host combination Niichiyo, 101...
-Microprocessor, 102...Address determination section, 103...Modified address generation section, 104...
・Correction code memory, 105...End address detection unit, 106...
-Code memory, 107...Data memory, 108...Address bus A1 109...Address bus B1 110...Data bus, 111...Gate A1 112...Gate B1 113...First Gate, 114...Second gate, 117, IIA...Flip 70 tube, 200
... Comparator A1 201 ... Latch Al 2O2 ... Modified address pointer, 203 ... Incrementer, 204 ... Comparator B1 2O3 ... Latch B1 600.601.602 ... Gate 603
...Gate control counter, 604.605.606.6
07.608.609...Latch 610, 611.6
12.701.702.703...Gate 704.
705.706...Latch 1000...Address bus.

Claims (1)

[Claims] an address determining section that determines a start address of a program to be modified in a program executed by a microprocessor; a modified address generating section that outputs address information of the modified program in response to a control signal from the address determining section; and the modified address generating section. a modification code memory that stores a modification program code executed by address information output from the modification program; and an end address detection unit that detects the end address of the modification program and prohibits output of address information from the modification address generation section. A program development support device having a section.