JPH0240741A - Cache speeding-up device - Google Patents

Abstract

PURPOSE:To shorten a cache operation time by prefetching an address while making the output of a cache access timing generating circuit which responds to a phase different clock lead an address determination signal, and then starting cache operation. CONSTITUTION:A microprocessor 2 which is applied with a synchronizing clock 100 generates a memory access signal 210, an address signal 230, and the address determination signal 220. On the other hand, a cache access timing generating circuit 3 which is applied with the delay clock from a phase clock generating circuit 1 outputs a cache access timing signal 310 leading the signal 230 by a specific time to a cache controller 5 which is applied with the output of an invalid control circuit 7 for invalidating wrong data written in a cache according to an address error together with the signal 230. Then the address signal is prefetched to start the cache operation and the cache operation time is shortened by the specific leading time to perform the cache operation substantially at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an information processing device, and more particularly to a cache speedup device.

Conventional technology Conventionally, it has been common practice in computer systems to use a cache to shorten the average memory access time, but an address confirmation signal sent from the microprocessor side is used to start the cache operation. It had been.

Problems to be Solved by the Invention However, since the address confirmation signal used for the conventional cache access timing described above is output with a delay from the actual address confirmation time, there is a drawback that the cache operation start time is delayed. Ta.

SUMMARY OF THE INVENTION Therefore, the present invention aims to provide a cache speed-up device that can start cache operation earlier than in the past.

Means for Solving the Problems According to the present invention, a microprocessor generates a memory bus access start signal, an address signal, and an address confirmation signal when accessing a memory bus in a system having a cache; means for generating a cache access timing signal delayed from the memory bus access signal; and inputting the address signal;
a cache directory circuit that starts a cache hit determination operation in response to the cache access timing signal and generates a bus request signal and a main memory write signal; and the bus request signal and the address confirmation signal generated from the directory circuit. a bus request control circuit that controls a bus request to a memory bus according to the conditions of the main memory write signal generated from the IJ circuit and the address confirmation signal; a main memory write control circuit; a circuit that receives at least the address confirmation signal and the cache access timing signal and generates an address error determination signal; and a circuit that receives the flash occurrence address signal, the address signal, and the address error determination signal. and an invalid control circuit that receives the address error determination signal and the flush generation signal and outputs an invalid generation signal to the directory circuit. A cache acceleration device is provided.

In one preferred embodiment of the present invention, the cache access timing signal generation means includes a phase difference clock generation circuit that generates a phase difference clock having a constant phase difference from the operating clock of the microprocessor, and a phase difference clock generation circuit that generates a phase difference clock having a constant phase difference from the operation clock of the microprocessor; and a circuit that receives the phase difference clock and generates the cache access timing signal, and the address error determination signal generation circuit receives the phase difference clock in addition to the address confirmation signal and the cache access timing signal. It is done like this.

In another preferred embodiment of the present invention, the cache access timing signal generation means is a delay circuit that receives and delays the memory bus access signal and outputs the delayed signal as a cache access timing signal; In addition to the address confirmation signal and the cache access timing signal, the memory bus access signal is received.

Operation As described above, in a preferred embodiment of the cache acceleration device of the present invention, in order to make the cache operation start time earlier than the address confirmation signal, a phase difference clock generation circuit is used to adjust the synchronization clock of the microprocessor. A phase difference clock whose phase is shifted by a certain amount of time is generated. Here, the certain period of time is defined as the maximum time from the rising edge of the microprocessor's synchronous clock until the address signal is determined when accessing the memory bus.

The cache access timing signal generation circuit generates a cache access timing signal by sampling the memory bus access signal using such a phase difference clock. At this timing, the cache controller circuit starts the cash hit determination operation.

A bus request control circuit and a main memory write control circuit inhibit or enable a bus request and a write signal to the main memory generated by the cache controller circuit due to its cache operation using an address confirmation signal on the microprocessor side.

Furthermore, the address error determination circuit determines an address error by sampling the address confirmation signal using a phase difference clock, on the condition that the cache access timing signal is generated. Then, the invalid control circuit invalidates the data in the cache based on the address error determination signal and the flush generation signal from the main memory, and the invalid address control circuit causes a flush generation signal from the main memory to be generated based on the address error determination signal. Input an address or an incorrect address from the microprocessor to the cache controller and make it invalid.

On the other hand, the address confirmation signal is generated only when a memory bus cycle on the processor side is executed.

In this way, the cache speed-up device according to the present invention preempts the address without waiting for the address confirmation signal to be output, and starts the cache operation earlier than the conventional cache access timing.

Embodiment Next, an embodiment of the cache acceleration device according to the present invention will be described with reference to the accompanying drawings.

FIG. 1 shows one embodiment of a cache acceleration device according to the present invention, and shows only the parts related to the present invention. FIG. 2 is a timing chart illustrating the operation of the device of FIG.

The phase difference clock generation circuit 1 inputs the synchronous clock 100 of the microprocessor 2, and as shown in FIG.
The phase difference clock 11 is shifted by a certain period of time t1.
Generates 0. The microprocessor 2 outputs a memory bus access signal 210, an address signal 230, and an address confirmation signal 220.

Time 1. As shown in FIG. 2, when accessing the memory bus, the maximum time t2 from the rising edge of the microprocessor's synchronous clock until the address signal is determined is set to be longer than t2.

The memory bus access signal 210 means that the memory bus access for that cycle has started, and is output together with the address signal 230. The address confirmation signal 220 is generated only when a memory bus cycle from the microprocessor is executed. Therefore, as shown in FIG. There is a delay of time t3.

The cache access timing generation circuit 3 samples the memory bus access signal 210 using the phase difference clock 110, and generates the cache access timing signal 310 as shown in FIG.

Memory bus access signal 2 is generated by phase difference clock 110.
10, the cache access timing signal 310 rises earlier than the rise time of the address confirmation signal 230 by time t4.

The cache controller 5 receives the address signal 230 from the microprocessor 2 and starts operating the cache controller in response to the cache access timing signal 310. The operation of the cache controller 5 is to check the address directory, but if there is a miss during a read operation, it will issue a bus request to the memory bus, and during a write operation, if it is a write-through type, the bus will be sent to the memory bus as soon as the operation starts. Generate a request.

The signal generated at that time is the memory bus request signal 5.
30, and as shown in FIG. 2, from the rise time of the cache access timing signal 310, the time 1.
Running late. Furthermore, during a write operation, writing to the main memory occurs. This generated signal is the main memory write signal 540, and as shown in FIG.
Time t6 is delayed.

Further, the memory bus request signal 530 and the address confirmation signal 220 are inputted to an AND circuit 8 which functions as a bus request control circuit, and the AND circuit 8 controls the memory bus request signal 530 and the address confirmation signal 220 according to the conditions of the memory bus request signal 530 and the address confirmation signal 220. Control bus requests to.

Main memory write signal 540 and address confirmation signal 220
is manually input to an AND circuit 9 which functions as a main memory write control circuit, and the AND circuit 9 controls main memory write according to the conditions of the main memory write signal 540 and the address confirmation signal 220.

Therefore, the bus request 530 generated by the cache operation of the cache controller 5 and the write signal 540 to the main memory are sent to the bus request control circuit (AN
D circuit 8) and main memory write control circuit (AND
The circuit 9) inhibits or enables the address determination signal from the microprocessor side.

Further, the address error determination circuit 4 starts operating in response to the cache access timing signal 310, samples the address determination signal 220 using the phase difference clock 110, determines whether or not the address of the cycle is determined, and confirms the address. If not, an address error determination signal 410 is generated.

When the address error determination signal 410 is generated, the flash generation signal 610 from the main memory is
Address error determination signal 410 and flash generation signal 6
10, the OR circuit 6 receives the invalid generation signal 51.
0 is generated and input to the cache controller 5 manually. This OR circuit 6 constitutes an invalid control circuit.

Further, the invalid address control circuit 7 that receives the address error determination signal 410, the flush generated address signal 620, and the address signal 230 sends the address signal 230 to the cache controller 5 as an invalid address signal 520, regardless of the flush generated address signal 620. Manually invalidate incorrect data written in the cache.

From the above, from the start of memory bus access to the cache access timing is t.

It can be seen that the access time is reduced by an amount of time.

FIG. 3 illustrates a modification of the cache acceleration device shown in FIG. 1, and the same reference numerals are given to the same components as those in FIG. 1, and the explanation thereof will be omitted.

As is clear from a comparison between FIG. 1 and FIG. 3, the memory bus access signal 210 from the microprocessor 2 is
The signal is directly input to the address error determination circuit 4, and is also input to the cache controller 5 via the delay circuit IO. The delayed memory bus access signal 21
0, the cache controller 5 starts operating.

In the cache acceleration device shown in FIG. 3 as well, by delaying the memory bus access signal 210 and inputting it to the cache controller 5 for operation, caching can be performed before the address confirmation signal.

The cache acceleration device shown in FIG. 3 is suitable for cases where board area is limited because the circuit that determines cache access timing is only a delay circuit.

Effects of the Invention As is clear from the above description, the cache speeding up device according to the present invention enables caching before the address confirmation signal, so that the cache operation time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a cache acceleration device according to the present invention. FIG. 2 is a timing chart illustrating the operation of the device of FIG. FIG. 3 is a block diagram illustrating a modification of the cache acceleration device shown in FIG. 1. [Main reference numbers] 1. Phase difference clock generation circuit 2. Microprocessor 3. Cache access timing generation circuit 4. Address error determination circuit 5. Cache controller

Claims (1)

[Scope of Claims] A microprocessor that generates a memory bus access start signal, an address signal, and an address confirmation signal when accessing a memory bus in a system having a cache; means for generating a delayed cache access timing signal; and a cache that receives the address signal, starts a cache hit determination operation based on the cache access timing signal, and generates a bus request signal and a main memory write signal. a directory circuit; a bus request control circuit that controls a bus request to a memory bus according to the conditions of the bus request signal and the address confirmation signal generated from the directory circuit; and the main memory write signal generated from the directory circuit. a main memory write control circuit that controls main memory writing according to the conditions of the address confirmation signal and the address confirmation signal; and a circuit that receives at least the address confirmation signal and the cache access timing signal and generates an address error determination signal. a circuit that receives a flush generation address signal, the address signal, and the address error determination signal and outputs an invalid address signal to the directory circuit; and a circuit that receives the address error determination signal and the flash generation signal and outputs an invalid address signal to the directory circuit. A cache acceleration device comprising: an invalid control circuit that outputs a signal.