JPH0240946A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce a region occupied by the capacitor of a voltage step-up circuit and miniaturize a device by applying a first conducting layer as a second layer to a first electrode of the capacitor, and forming a second electrode by connecting a second conducting layer and a diffusion Iayer. CONSTITUTION:In a semiconductor integrated circuit, a thermal oxide film 32 is formed on a P-type semiconductor substrate 31, and a thermal oxide film 33 is formed in a capacitor forming region 33 divided by the film 32. An N-type diffusion layer 37 is formed on the substrate 31 of the capacitor forming region. A first conducting layer 35 of polycrystalline Si is formed on the films 33, 32. On the film 35 and the substrate 31 surface of a forming region for a MIS type semiconductor device, an oxide film 34, a gate electrode 36a, and a second conducting layer 36b of the capacitor are formed, and an oxide film 41 is formed thereon. In a source.drain region and the capacitor part, an N<+> diffusion layer 38 is formed. By using a wiring 40 formed on an interlayer insulating layer 39 formed on the whole surface, an electrode is led out from the layer 35, and used as the first terminal of the capacitor. The layer 37 and the layer 36b are connected and used as the second terminal thereof.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit constituting a booster circuit that generates a voltage higher than a power supply voltage.

[Prior Art] FIG. 7 shows one unit of a conventional semiconductor integrated circuit composed of a capacitor and an MIS type semiconductor device, and FIG. 8 shows a circuit diagram of a booster circuit. In the booster circuit shown in Fig. 8,
Six semiconductor sound product circuits (FIG. 7 is a cross-sectional structure thereof) constituted by an N-channel MIS transistor 4 and a capacitor 3 are connected from a power supply terminal 1 via an N-channel MIS semiconductor device 2. The structure is connected in series.

Reference numerals 6 and 7 are both clock input terminals, and clock signals having mutually opposite phases are input to the clock input terminal 6 and the clock input terminal 7. Reference numeral 5 is an output terminal of the booster circuit, from which a voltage higher than the power supply voltage can be obtained.

Next, the principle of the booster circuit shown in FIG. 8 will be explained. FIG. 9 shows a circuit in which two semiconductor integrated circuits of the unit whose cross-sectional view is shown in FIG. 7 are connected in series. The potential of the −1nth connection point 9 is assumed to be V4. Capacitor 12 is the MIS type capacitor shown in FIG.
Letting the capacitance value be C, it is usually about 1 to 4 pF. Capacitance 13 is a parasitic capacitance attached to each connection point, and if its capacitance value is Cs, usually Cs = 0.1 to 0.
．． It is 3pF. Note that the threshold voltage of the N-channel MIS type semiconductor device is vTN. Clock signals having mutually opposite phases are inputted to the clock input terminal 6°7, and the amplitude voltage thereof is assumed to be φ. Note that the frequency of this tarok signal is usually between 2 MHz and 6 MHz. First, the tarock input terminal 6 is set to O volts, the clock input terminal 7 is set to φ volts, and the voltage at the (n-1)th connection point 8 is set to V, -1. Then, consider the moment when the clock is inverted and the input terminal 6 becomes ■φ volt and the input terminal 7 becomes 0 volt. The total charge accumulated at the connection point 8 is Cs V n-s +
C(Vn-1+Vφ). ■When the clock changes o, the input terminal 7 becomes 0 volts, and the capacitance 13 and the capacitance 1
If the potential is immediately after the charge of 2 is redistributed, then the connection point 8
The charge moves to the connection point 9 via the N-channel MrS type semiconductor device 10, and the movement occurs when the voltage at the connection point 8 is
(2) This is continued until the state becomes TN and the N-channel MIS type semiconductor device 10 becomes non-conductive. At this time, the charge accumulated at the connection point 8 is (C0Cs) (Vfi+VTN). Therefore, the charge Q transferred from connection point 8 to connection point 9 is C! 11
V,,+C(V,,+Vφ)(CTCs)(V
, +VTN) = Q - (1). When the units of semiconductor integrated circuits shown in FIG. 7 are connected in N stages in series, solving the recurrence formula expressed in (1) yields N...(2). In order to obtain a sufficient boost voltage, C>
It can be seen that it is necessary to be Cs. The current fXQ can be taken out from the output terminal 5 of the booster circuit shown in FIG. Here, f is the clock frequency of the booster circuit.

By making the capacitance value C sufficiently large, -Q/(CT
Cs) can be made sufficiently small, and the output current f
If XQ is constant, a higher boosted voltage Vti can be obtained, and if boosted voltage VN is constant, more current can be outputted.Normally, a value of about C≠1005 can be used. many.

FIG. 7 shows a cross-sectional view of a capacitor according to the prior art, in which a polycrystalline silicon film is used to form the upper electrode 26b of the capacitor for forming the gate electrode 26a of the MIS type semiconductor device.
In the lower diffusion layer, an N-type diffusion layer 25 formed by ion implantation, etc., and in the lower electrode extraction part, an N+ diffusion layer 2 in the source region and drain region of the MIS type semiconductor device is formed.
The N+ diffusion layer 24b formed in the same process as 4a is used, and the gate oxide film 23 formed in the same process as the gate oxidation M23a of the MIS type semiconductor device is used as the insulating film between the electrodes of the capacitor.
b is used.

In FIG. 7, the gate electrode 26a made of a polycrystalline silicon layer of the MIS type semiconductor device is connected to the aluminum wiring 28 on the channel region; In reality, the aluminum wiring 28 and the polycrystalline silicon layer 26 which is the gate electrode are formed on the element isolation oxide film 22.
A connection is established with a.

Note that reference numeral 27 is an insulating film between the eyebrows, and reference numeral 29 is a thermal oxide film.

[Problems to be Solved by the Invention] However, the conventional booster circuit described above uses a capacitor 12 that is sufficiently larger than the parasitic capacitance 13 (capacitance value Cs) attached to each connection point to configure the booster circuit. There is a need. Also, when trying to obtain more output power from the booster circuit,
Alternatively, when attempting to increase the output voltage of the booster circuit, a large number of capacitors with large capacitance values are required. in this way,
In order to form a large number of capacitors with large capacitance values, a vast area is required on the substrate 21, which has the drawback of increasing the size of the semiconductor integrated circuit.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a semiconductor integrated circuit that can reduce the area occupied by the capacitance of a booster circuit and can be miniaturized.

[Means for Solving the Problems] A semiconductor integrated circuit according to the present invention has a drain electrode and a gate electrode of a first MIS type semiconductor device connected to a first electrode of a capacitor to serve as a first terminal, and a source electrode connected to a first electrode of a capacitor. As the second terminal,
The second electrode of the capacitor is the third terminal, and this first MI
A plurality of unit integrated circuits, one unit of which is composed of an S-type semiconductor device and a capacitor, are connected in series by mutually connecting their first and second terminals. In a semiconductor integrated circuit in which a terminal is connected to a source electrode of a second MIS type semiconductor device, and a gate electrode and a drain electrode of the second MIS type semiconductor device are connected to a potential supply source, the capacitance is a second conductivity type diffusion layer formed on a conductivity type semiconductor substrate; a first insulating film formed on the diffusion layer; a first conductive layer formed on the first insulating film; a second insulating film formed on a first conductive layer; and a second conductive layer formed on the second insulating film, the first conductive layer being the first electrode of the capacitor, and the The second conductive layer is connected to the second conductivity type diffusion layer to serve as the second electrode of the capacitor.

[Function] In the present invention, the second conductivity type diffusion layer constituting the capacitor,
A first insulating film, a first conductive layer, a second insulating film, and a second conductive layer are laminated in this order, and three layers of electrodes are laminated with the insulating film in between. The first conductive layer of the second layer is used as the first electrode of the capacitor, and the second conductive layer and the diffusion layer are connected to form the second electrode. As a result, the area where the first electrode and the second electrode face each other with the first and second insulating films in between is twice the area where the first and second electrodes are formed on the semiconductor substrate, which is extremely small. A capacitor with a large capacitance value can be formed in the formation region.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a sectional view showing one unit of a capacitor and an MIS type semiconductor device in a semiconductor integrated circuit according to an embodiment of the present invention.

A thermal oxide film 32 for element isolation is formed on the surface of the P-type semiconductor substrate 31.
A thermal oxide film 33 is formed in a capacitor formation region partitioned by this oxide film 32. Furthermore, an N-type diffusion layer 37 is formed in the substrate 31 in this capacitor formation region by ion implantation of phosphorus. In addition, the thermal oxide film 33
A first conductive layer 35 is formed on the element isolation oxide film 32 by depositing a polycrystalline silicon layer by vapor phase epitaxy and then patterning the layer.

On the other hand, an oxide film 34 is formed by thermally oxidizing each surface of the polycrystalline silicon first conductive layer 35 and the substrate 31 in the MIS type semiconductor device formation region, and is further formed by a vapor phase growth method to form an MIS type semiconductor device. Polycrystalline silicon forming the gate electrode 36a and a polycrystalline silicon layer forming the second conductive layer 36b of the capacitor are formed simultaneously. Then, the surfaces of the polycrystalline silicon layer of the gate electrode 36a and the second conductive layer 36b are thermally oxidized to form an oxide film 41.

Further, an N+ diffusion layer 38 is formed in the source region and drain region of the MIS type semiconductor device by ion implantation, and an N+ diffusion layer 38 is also formed in the capacitor part in the same process.
is formed. The glabellar insulating film 39 formed on the entire surface includes an N+ diffusion layer 38, a first conductive layer 35 made of a polycrystalline silicon layer, a gate electrode 36a, a second conductive layer 3
6b are formed, and the electrodes are taken out from the polycrystalline silicon first conductive layer 35 using the aluminum wiring 40 patterned on the glabella insulating film 39 to increase the capacitance. A semiconductor integrated circuit is constructed by connecting the first terminal and the second terminal by connecting the lower diffusion layer 37 and the polycrystalline silicon second conductive layer 36b.

In the semiconductor integrated circuit configured in this way, the first
The conductive layer 35 is used as one terminal, and the second conductive layer 36b and N
A capacitor is configured with the type diffusion layer 37 as the other terminal. In other words, since a capacitor is formed by three layers of electrodes formed with an insulating film in between, by using the capacitor of this structure,
When the film thicknesses of the oxide films 33 and 34 are the same, a capacitance value twice that of the conventional one can be obtained if the area of the capacitor formation region is the same as that of the conventional one, or a capacitance value twice that of the conventional one can be obtained, or if the capacitance value is the same as that of the conventional one, it is possible to obtain a capacitance value twice that of the conventional one. The same capacity can be achieved with half the area.

FIG. 2 is a sectional view showing a semiconductor integrated circuit according to a second embodiment of the invention.

The main structure of this example is the case of FIG. 1 and the N-type diffusion layer 3.
The only difference is that 7 is omitted and an N well 42 is formed.

Therefore, in FIG. 2, the same parts as those in FIG. 1 are given the same reference numerals and their explanations will be omitted.

As shown in FIG. 2, in the case of a complementary semiconductor device, the lower diffusion layer of the capacitor is not formed by ion implantation.
The N-well 42 formed on the P-type semiconductor substrate 31 can be used as a lower diffusion layer for capacitance. Therefore, in this example, there is no need to add a new ion implantation process to form the N-type diffusion layer below the capacitor.
By using the N-well 42, a capacitance equivalent to that shown in FIG. 1 can be formed. Recently, in order to reduce power consumption, complementary MIS type semiconductor devices are often used, and in this case, it is possible to use the N well 42 for the lower diffusion layer as in the present structure.

FIG. 3 shows a third embodiment of the invention. In FIG. 3, parts corresponding to those in FIG. 1 are given the same reference numerals, and their explanations will be omitted.

In this embodiment, a second conductive layer 36 made of a polycrystalline silicon layer is used.
c is formed so as to cover the side surfaces of the first conductive layer 35 made of a polycrystalline silicon layer. Thereby, the capacitance between the side surface portion of the first conductive layer 35 and the second conductive layer 36c is also effectively utilized.

4 and 5 are schematic plan views showing the planar shape of the capacitor. 51 is an N+ diffusion layer; 52 is a lower polycrystalline silicon layer corresponding to a first conductive layer; 53 is an upper polycrystalline silicon layer corresponding to a second conductive layer; 54 is a contact;
5 is an aluminum wiring. In Figure 4, the first
The area of the upper polycrystalline silicon layer 1i53 corresponding to the second conductive layer is larger than the area of the lower polycrystalline silicon layer 52 corresponding to the conductive layer, and the polycrystalline silicon layer 53 sandwiches the insulating film and covers the side surfaces. The structure is such that it covers the polycrystalline silicon layer 52 as well. On the other hand, FIG. 5 shows a case where the area of the polycrystalline silicon layer 53 corresponding to the second conductive layer is smaller than the area of the lower polycrystalline silicon layer 52 corresponding to the first conductive layer. In either case, unlike the embodiments shown in FIGS. 1 to 3, contact between the second conductive layer and the aluminum wiring is made on the element isolation oxide film.

The booster circuit according to the embodiment of the present invention uses the same semiconductor to generate a write/erase voltage in an electrically programmable/erasable nonvolatile semiconductor memory device having two gate layers: a control gate and a floating gate. It is particularly useful when formed on a substrate.

FIG. 6 shows a cross-sectional view of an electrically writable and erasable nonvolatile semiconductor memory device having two gate layers, a control gate and a floating gate. The structure of the nonvolatile semiconductor memory device will be explained using FIG. 6.

An element isolation oxide film 62 and an oxide film 63 are formed on a P-type semiconductor substrate 61, and a portion of the oxide film 63 is a tunnel oxide film 72 having a thickness of approximately 100 mm. Mana, oxidized M6
A first conductive layer 65 made of a polycrystalline silicon layer is formed on the first conductive layer 65, and an oxide film 64 is formed by thermally oxidizing the surface of the first conductive layer 65. Furthermore, a second conductive layer 6 made of a polycrystalline silicon layer is formed to cover the polycrystalline silicon layer 65.
6 is formed, and the surface of this second conductive layer 66 is thermally oxidized to form an oxide film 71. And the glabellar insulating film 69
After forming contact holes, an aluminum wiring layer 70 is formed.

Further, on the surface of the substrate 61, N+ diffusion layers 68 are formed in the source region and the drain region. Furthermore, in the region from below the tunnel oxide film 72 to the drain region, and from the source region to below the polycrystalline silicon first conductive layer 65,
An N-type diffusion layer 67 is formed.

From the structure shown in FIG. 6, an N-type diffusion layer 67 formed under the gate necessary to form the capacitance of the booster circuit of the present invention,
It is clear that there are two conductive layers, a first conductive layer 65 and a second conductive layer 66 made of polycrystalline silicon.

Therefore, the booster circuit of the present invention can be applied to a booster circuit for generating a write/erase voltage in a nonvolatile semiconductor memory device having a structure as shown in FIG. 6 without providing any special additional steps.

In this way, in an electrically programmable and erasable semiconductor memory device having two gate layers, a control gate and a floating gate, electrons are transferred to the floating gate by a Fowler-Nordheim current through a tunnel oxide film approximately 100 nm thick, for example. In semiconductor memory devices that can be electrically programmed and erased by injection or discharge, recently, the high voltage of about 20V necessary for programming and erasing the semiconductor memory device is not supplied externally, and the normal 5V of a semiconductor integrated circuit is used. It is generated by boosting the voltage from the power supply.

For this purpose, a circuit as shown in FIG. 6 is used to realize the voltage boost described above. At this time, the polycrystalline silicon layer used as a floating gate in the first conductive layer is
By using a polycrystalline silicon layer used as a control gate as a conductive layer, it is possible to reduce the area occupied by a capacitor part used in a booster circuit without providing an additional process.

In Example 1.2.3, the second layer of polycrystalline silicon was formed in the same process to form the gate electrode of the MIS type semiconductor device formed on the same substrate. Recently, a compound of silicon and a high melting point metal, such as silicide, has been used as the gate electrode.

Therefore, in the capacitor of the present invention, it is also possible to use silicide or the like instead of the second polycrystalline silicon layer.

In addition, in the embodiment 1.2.3 above, a thermally oxidized film of silicon or polycrystalline silicon was used as the first insulating film or the second insulating film of the capacitor. For example, silicon nitride film,
It is also possible to use a tantalum oxide film or the like. At this time, a silicon thermal oxide film is used for the gate insulating film of the MIS type semiconductor device as in the past, a thermal oxide film is used for the corresponding capacitor insulating film, and the remaining capacitor insulating film is used as described above. By using a material with a higher dielectric constant than a silicon oxide film, the device of this embodiment can be manufactured in the same process as the conventional MIS type semiconductor device manufacturing method, and a large capacitance value can be obtained with a smaller area than the conventional method. Is possible.

[Effects of the Invention] As explained above, the present invention has three layers of a second conductivity type diffusion layer, a first conductive layer, and a second conductive layer sandwiching a first insulating film and a second insulating film. Forming the capacitor of the stacked structure, the first
By using the conductive layer as the first electrode and connecting the second conductive type diffusion layer and the second conductive layer to form the second electrode, the capacitance of the conventional MIS type structure is smaller than that of the conventional MIS type structure. Since the same capacitance value can be obtained, there is an effect that the area occupied by the capacitor section, which is essential for the configuration of the booster circuit, can be reduced without impairing the characteristics of the booster circuit.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a booster circuit according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view showing a booster circuit according to a second embodiment of the present invention, and FIG. FIG. 4 is a plan view of the capacitance of the boost circuit according to the embodiment of the present invention, FIG. 5 is a plan view of the capacitance of the boost circuit according to the embodiment of the present invention, FIG. 6 is a sectional view of an electrically writable and erasable semiconductor device, FIG. 7 is a sectional view of a conventional booster circuit, FIG. 8 is a circuit diagram of the booster circuit, and FIG. 9 is a partial circuit diagram of the booster circuit. It is. 1; Power supply terminal, 2, 4; N-channel MIS type semiconductor device, 3; Capacitor, 5; Output terminal, 6, 7; Clock input terminal, 35; First conductive layer, 36a; Gate electrode, 36b; Second conductive layer Layer, 38; N+ diffusion layer, 51; N+ diffusion layer, 52
; lower polycrystalline silicon layer, 53; upper polycrystalline silicon layer, 54; contact, 55; aluminum wiring, 63;
Oxide film, 65; First conductive layer, 66; Second conductive layer, 72;
tunnel oxide film

Claims (1)

[Claims] (1) Connecting the drain electrode and gate electrode of the first MIS type semiconductor device to the first electrode of the capacitor to form the first terminal,
The source electrode is a second terminal, the second electrode of the capacitor is a third terminal, and a plurality of unit integrated circuits, each unit of which is composed of the first MIS type semiconductor device and the capacitor, are connected to the first terminal and the second terminal. 2 terminals are connected to each other in series, and the unconnected first terminal of the unit integrated circuit is connected to the second MIS.
connected to the source electrode of the type semiconductor device, and connected to the source electrode of the second MIS
In a semiconductor integrated circuit in which a gate electrode and a drain electrode of a type semiconductor device are connected to a potential supply source, the capacitance includes a diffusion layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type, and a diffusion layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type; a first insulating film formed on the first insulating film, a first conductive layer formed on the first insulating film, a second insulating film formed on the first conductive layer, and a first insulating film formed on the second insulating film. and a second conductive layer formed on the capacitor, the first conductive layer being the first electrode of the capacitor, and the second conductive layer being the second conductive layer.
A semiconductor integrated circuit, characterized in that the second electrode of the capacitor is connected to a conductive type diffusion layer.