JPH0240948A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To control independently the rise time and the fall time of a CMOS logic circuit by inserting variable resistance elements controlled from mutually independent external terminals, in an power supply route and a grounding route of the CMOS logic circuit. CONSTITUTION:An internal inverter circuit is constituted of a CMOS inverter circuit, N-channel or P-channel MOS Tr 3 and Tr 4. In the CMOS inverter circuit, gates of a P-channel MOS Tr 1 and an N-channel MOS transistor Tr 2 are mutually connected, and drains of the transistors are mutually connected. The above node-points are made the logic input and the logic output, respectively. The MOS Tr 3 and Tr 4 are inserted, respectively, in the power supply side and the grounding side of the CMOS inverter circuit. The Tr 3 and the Tr 4 are used as variable resistance elements, and the gates of them are connected with the external input terminals 5 and 6, respectively. By voltages independently applied to the external input terminals 5, 6, characteristics of the rise time and the fall time of output voltage can be independently controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CMOS semiconductor integrated circuit, and in particular to a CMOS semiconductor integrated circuit.
The present invention relates to a semiconductor integrated circuit in which the propagation delay characteristics of an S logic circuit can be controlled from outside the integrated circuit.

[Prior art] Among the propagation delay times of CMOS semiconductor integrated circuits, the rise time depends on the product of the on-resistance of the P-channel MOS transistor and the output load capacitance, and the fall time depends on the product of the on-resistance of the N-channel MOS transistor and the output Depends on the product with load capacity.

Normally, the on-resistance of a MOS transistor is affected by process variations.
Depending on temperature, the output load capacitance depends on the circuit configuration and wiring routing on the chip.

[Problems to be Solved by the Invention] The conventional CMOS semiconductor integrated circuit described above cannot adjust the propagation delay time or shape the output waveform because it is difficult to control the elements that determine the propagation delay time. There was a problem.

The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a semiconductor integrated circuit whose propagation delay characteristics can be controlled from outside the integrated circuit.

[Means for Solving the Problems] A semiconductor integrated circuit according to the present invention includes first and second variable resistance elements whose resistance values can be controlled from an external terminal, and a power supply via the first variable resistance element. and a CMOS logic circuit connected to the ground via the second variable resistance element.

[Function] According to the present invention, the first variable resistance element inserted in the power supply connection path of the CMOS logic circuit determines the on-resistance of the P-channel MOS transistor, and the first variable resistance element inserted in the ground path of the CMOS logic circuit determines the on-resistance of the P-channel MOS transistor. The second variable resistance element is N channel M
It acts to determine the on-resistance of the OS transistor. Since the resistance values of these two variable resistance elements can be controlled from external terminals, the rise time and fall time of the CMOS logic circuit can be controlled independently, and as a result, the propagation delay characteristics of the circuit can be controlled.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a diagram showing an embodiment in which the present invention is applied to an internal inverter gate of an integrated circuit. This circuit consists of a CMOS inverter circuit that connects the gates and drains of a P-channel MOS transistor 1 and an N-channel MOS transistor 2, and uses each node as a logic input and output, and a power supply side and a ground side of this circuit. N-channel or P-channel MOS) transistors 3 and 4 inserted into the MOS transistors 3 and 4, respectively. The MOS transistors 3 and 4 are used as variable resistance elements, and their gates are connected to external input terminals 5 and 6, respectively.

An internal signal of the integrated circuit is applied to the input of the CMOS inverter circuit, and another internal gate is connected to the output. The isometric load capacitance is expressed by capacitor 7.

Here, the on-resistance value of the P-channel MOS transistor 1 is RION, the on-resistance value of the N-channel MOS transistor 2 is R2o, and the source of the MOS transistor 3 is determined depending on the voltage V applied to the external input terminal 5.・
The resistance value between the drain is R3 (V5), and the resistance value between the source and drain of the MOS transistor 4, which is determined depending on the voltage v6 applied to the external input terminal 6, is R4 (V, 6).
, when the capacitance of capacitor 7 is C1 and the power supply voltage is VDD, CMO consisting of MOS transistors 1 and 2
Logic output voltage V of the S inverter gate. When the output rises, ut is the P-channel MOS) - Vout-VDD, with the time when transistor 1 turns on from off to t=0, [1-1] When the output falls, the P-channel MOS )--t=0 is the time when the transistor 2 is turned on from off, and it is expressed as ■...t=voo... (2).

As is clear from these equations (1) and (2), the logical output voltage ■ is determined by the voltages v5 and ■6 applied to the external input terminals 5 and 6. It is possible to independently control the rise and fall characteristics of . Therefore, by using these relationships, it becomes possible to adjust the propagation delay time of the 0MO3 logic gate and shape the output waveform from the external terminal of the semiconductor integrated circuit, which was previously impossible.

FIG. 2 shows an example in which the present invention is applied to an external input inverter/buffer of an integrated circuit. This circuit is similar to the circuit shown in FIG.

FIG. 3 shows an example in which the present invention is applied to an external output inverter/buffer, and the configuration and operation are the same except that the logic output of the CMOS inverter circuit is connected to the equal load capacitor 7 via the external logic output terminal 9. Both circuits are similar to the circuit shown in FIG.

In the above embodiment, a CMOS inverter circuit was taken as an example, but the present invention is applicable to CMOS inverter circuits such as 0MO3 logic gates and arithmetic circuits.
Needless to say, it is applicable to all MO3 circuits.

[Effects of the Invention] As explained above, the present invention enables CMO3 logic, which was previously impossible, by inserting variable resistance elements controlled from independent external terminals into the power supply connection path and the ground path of a CMOS logic circuit. This has the advantage that the gate propagation delay time can be adjusted and the output waveform can be shaped from an external terminal of the semiconductor integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a CMOS semiconductor integrated circuit according to a first embodiment of the present invention, FIG. 2 is a circuit diagram of a CMOS semiconductor integrated circuit according to a second embodiment of the present invention, and FIG. 3 is a circuit diagram of a CMOS semiconductor integrated circuit according to a second embodiment of the present invention. FIG. 3 is a circuit diagram of a CMOS semiconductor integrated circuit according to a third embodiment of the present invention. 1; P channel MOS transistor, 2; N channel MO3) transistor, 3, 4; MOS transistor,
5, 6; External input terminal, 7; Equivalent load capacity, 8; External logic input terminal, 9; External logic output terminal

Claims (1)

[Claims] (1) first and second variable resistance elements whose resistance values can be controlled from external terminals; connected to a power supply via the first variable resistance element and grounded via the second variable resistance element; A semiconductor integrated circuit characterized by comprising a CMOS logic circuit.