JPH0241012A - Analog signal delay circuit - Google Patents

Abstract

PURPOSE:To apply the title circuit to MOS LSI processing properly by using a DELTASIGMA type AD converter so as to make the circuit immune from noise. CONSTITUTION:An input analog signal A is inputted to the DELTASIGMA type AD converter 10, where the signal is sampled at a fast speed by using a clock pulse fs and converted into a 1-bit digital output B and extracted. The address of the digital signal B is changed by the same frequency as the sampling frequency fs and the result is written in a memory 41. Then a digital output C read in the timing retarded by a prescribed time is binarized by a binarizing circuit 20 under the control of a control logic circuit 40, passed through a low pass filter 30, a high frequency component is eliminated and the original input analog signal A is recovered. Thus, the circuit is made immune from and proper to LSI processing.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an analog signal delay circuit.

[Prior Art] In a conventional analog signal delay circuit, an analog signal is written into a charge transfer element using a BBD (packet gate type device), etc., and the output is read out at a timing T time delayed from the writing, and the delay time is 1 hour. A method is used to extract delayed analog signals.

[Problems to be Solved by the Invention] In this case, there are problems in terms of frequency characteristics and S/N ratio, and in addition, it is difficult and expensive to convert the circuit into a MOS-LSI.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an inexpensive analog delay circuit that can widen the dynamic range of an analog human input signal, is less susceptible to noise, is suitable for MOS-LSI implementation, and is inexpensive.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides an analog signal with a frequency f that is several tens of times higher than the frequency of the analog signal.
A ΔΣ type AD converter means that samples at s to form a 1 bit digital signal, and a series of 1 bit digital No. 13 formed and output by the ΔΣ type AD converter means are written to the memory at the same frequency as the frequency fs. , a memory control means for temporarily holding and reading, a binarization means for binarizing the read series of 1-bit digital signals, and a high frequency component removed from the output from the binarization means; The present invention is characterized by comprising filter means for extracting an analog signal delayed by a time difference between writing and reading of a 1-bit digital signal in the memory control means.

[Function] According to the present invention, by using a ΔΣ type eight converter, it is less susceptible to noise, and the entire circuit is made up of MOS.
It is also suitable for LSI implementation.

[Examples] Examples of the present invention will be described in detail below with reference to the drawings.

An embodiment of the present invention is shown in FIG. 1, and examples of signal waveforms at various parts thereof are shown in FIGS. 2(A) to 2(D).

In FIG. 1, lO is a ΔΣ type AD converter,
For example, when an analog input signal (A) as shown in Fig. 2 (A) is received, a pulse signal (with a duty ratio proportional to the amplitude of the analog human input signal (A) as shown in Fig. 2 (B)) is generated. B) is obtained.

The ΔΣ type AD converter IO itself has a known configuration, where 11 and 12 are operational amplifiers, 13 and 14 are adders, and 15 and 16 are operational amplifiers 11 and 12.
17 is a comparator, 18 is a D-type flip-flop, and 19 is a 1-bit DA converter.

The adder 13 is supplied with the human input analog signal (A) and the output from the DA' converter 19, and the added output is supplied to the negative input terminal of the operational amplifier 11. The output of the operational amplifier 11 and the output from the DA converter 19 are supplied to the adder 14, and the added output is supplied to the negative input terminal of the operational amplifier 12. Each positive input terminal of operational amplifiers 11 and 12 is connected to analog ground potential. The comparator 17 compares the output from the operational amplifier 12 with the analog ground potential, and outputs "1" when the output is greater than the analog ground potential, and "0" otherwise. supplies the binary output "0" or "1" from the comparator 17, and also supplies a clock pulse fS having a frequency several tens of times higher than the frequency of the human input analog signal (A) to the clock input terminal,
At the rising edge of the clock pulse, data "0" or "1" from the comparator 17 is taken in.

The output of the flip-flop 18 is supplied to a 1-bit OA converter 19, where, for example, -IV
, for "0", a predetermined voltage such as +1v is generated, and the analog output is sent to adders 13 and 14.
are fed back as a difference to operational amplifiers 11 and 12, respectively. As a result, the newly incoming analog signal is differentiated by the analog amount corresponding to the immediately preceding digital data, and then integration is performed.

In this way, the first human-powered analog signal (A) is sampled at high speed with the clock pulse f5 and is
), it is converted into a 1-bit digital output (B) and taken out.

This digital signal (B) becomes a pulse train with a duty ratio proportional to the amplitude of the analog signal (A). However, since the flip-flop 1B operates with the clock pulse fS, the pulse width of the digital output is 1 ats.
It only takes a value that is an integral multiple of (seconds), and is a digitally discrete quantity. In other words, as shown in Figure 2 (A), the duty ratio changes depending on the amplitude and polarity of the analog signal (A), and the duty ratio changes when the input is in the negative direction than when the input is in the positive direction. However, the duty ratio is low. Further, when the amplitude is zero, that is, there is no signal, the duty ratio is 50 zero.

As described above, in the present invention, the digital output obtained by converting an input analog signal into a 1-bit digital signal by the ΔΣ type AD converter 10 is converted into a 1-bit digital signal by the ΔΣ type AD converter 10 under the control of the control logic circuit 40. After changing the address at the same frequency as the sampling frequency f8, writing it into the memory 41 and temporarily holding it,
Reading is performed at a timing T time later than writing (see FIG. 2(B) and FIG. 2(C)). memory 41
is normal RAM.

It can be configured with a FIFO (first in first out) register or a shift register.

When using RAM, the delay time T becomes T-N/fS when the memory addresses are sequentially read from O to N-1 and then written, and by changing N. Any delay time can be obtained.

When using FIFO registers or shift registers, depending on their depth and sampling frequency fs,
A delay time is determined.

The digital output read out at a timing delayed by T time under the control of the control logic circuit 40 is binarized through the binarization circuit 20 and then passed through the low-pass filter 3.
Figure 2 (
The first human-powered analog signal can be reproduced as shown in D).

The low-pass filter 30 can also be configured with a passive filter using a CR or an active filter using a CR and an operational amplifier.

In fact, as a feature of the present invention, this low-pass filter can be directly constructed from a switched capacitor filter without inserting an anti-aliasing filter.

Since the switched capacitor filter samples and processes input data using its sampling clock f+:LK, signals in the frequency band of Cfc+, an integer multiple of ) ± (filter passband) are returned to the passband as they are. It will be done. Therefore, in the conventional method using a charge transfer device, the width of the output pulse is arbitrary, so
Its frequency spectrum can span the entire range,
Since components of the entire band are folded back, a low-pass filter for preventing folding is inserted before the switched capacitor filter to cut off frequencies higher than the pass band. On the other hand, in the present invention, the frequency fS of the sampling clock of the AD converter lO and the sampling clock fC of the switched capacitor filter
LK are set equal, and the frequency is set sufficiently high with respect to the passband. 〇 Output of converter 10 (B)
Since the frequency spectrum of has no energy near the frequency fs, that is, an integer multiple of fcL, the present invention does not require a folding filter.

[Effects of the Invention] As is clear from the above, by using a ΔΣ type AD converter, the present invention is less susceptible to noise 929, unlike the conventional method using a charge transfer element, and the entire circuit can be implemented as a MOS LSI. It is also suitable for use and is inexpensive.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a signal waveform diagram of each part for explaining its operation. lO...ΔΣ type AD converter, 11.12... Operational amplifier, 13.14... Adder, 15.16... Capacitor, 17... Comparator, ]8... D type flip-flop , 19... DA converter, 20... Binarization circuit, 30... Low pass filter, 40... Control logic circuit, 41... Memory.

Claims (1)

[Scope of Claims] 1) ΔΣ type AD converter means for sampling an analog signal at a frequency f_s that is several tens of times higher than the frequency of the analog signal to form a 1-bit digital signal; and the ΔΣ type AD converter means. a memory control means for writing, temporarily holding, and reading a series of 1-bit digital signals formed and outputted in a memory at the same frequency as the frequency f_s; binarization means for binarizing a digital signal; and a high-frequency component of the output from the binarization means is removed, and the 1-bit digital signal is delayed by a time difference between writing and reading in the memory control means. An analog signal delay circuit comprising filter means for extracting the analog signal.