JPH0241029A - Analog/digital conversion circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for A/D conversion and to confirm the accuracy of a resistance ladder circuit in a short time by designating a test mode and reading a divided voltage designated by the resistance ladder circuit externally directly. CONSTITUTION:When a level 1 is set to a mode register 11, a selector 12 inputs an output of a counter 13 to a resistance ladder circuit 1. The resistance ladder circuit 1 outputs a prescribed division voltage alphaVr of a reference voltage depending on the content of the counter 13. When the resolution of the resistance ladder circuit 1 is 1/256, since the counter 13 handles 8-bit, the resistance ladder circuit 1 outputs a voltage corresponding to the count (m) of the counter 13, that is, a voltage being a multiple of m/256 of the reference voltage Vr. The voltage is outputted one after another by counting up the counter 13 and outputted to a terminal 2 via a switch 14. Thus, the test of the ladder resistance deciding the conversion accuracy is conducted by measuring the voltage alphaVr at the terminal 2 externally.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a successive conversion type analog-to-digital conversion circuit (hereinafter referred to as an A/D converter), and particularly relates to a test method for a resistance ladder circuit that divides a reference voltage. .

[Prior Art] Conventionally, a successive approximation type A/D converter is known as a relatively high-speed A/D converter.

FIG. 3 shows the configuration of this type of A/D converter.

The resistance ladder circuit 1 divides the reference voltage Vr and outputs a predetermined divided voltage. The analog voltage input from the terminal 2 is compared with the above-mentioned divided voltage in the voltage comparison circuit 3. The comparison results are stored in the successive approximation register 5 via AND gates 41 to 4n. Successive approximation register 5
Based on the comparison result of the voltage comparator circuit 3, divided voltages of the resistance ladder circuit 1 are sequentially selected by a binary search method. That is, V,/2 is first selected as the dividing voltage,
When the analog input voltage ■In is VIn>■r/2, then 3V, /4 is selected, and when it is V+, *r/2, vr/4 is selected. This kind of selection is gradually made at a finer level. This comparison is performed for the number of bits of the A/D converter. For example, in the case of an 8-bit A/D converter, eight comparisons are performed. Clock signal ψ1 is output once for each comparison. By counting this clock signal ψ1 with a counter 6, the number of comparisons is counted.

The decoder 7 sequentially operates AND gates 41 to 4 . Activate.

As a result, the comparison result of each bit is stored in the successive approximation register 5.
be taken into account.

Incidentally, in order to examine the A/D conversion accuracy of the above-mentioned A/D converter, the following test has been conventionally performed. That is, first, a known analog voltage is input from terminal 2. For example, in an A/D converter with a resolution of 1/256, a known analog voltage is input after changing it in 256 steps. Then, A/D conversion using a successive approximation method is performed for each of these analog voltages, and it is checked whether the converted digital value is an ideal digital value corresponding to the input known analog voltage. /D converter accuracy is being determined.

[Problems to be Solved by the Invention] In the conventional test method for the successive conversion A/D converter described above, for example, if the conversion accuracy is 8 bits, it is necessary to input the analog input voltage 256 times at 1/256 steps. . Furthermore, it is necessary to count up the counter 6 eight times to obtain a digital value for one analog input voltage.

Furthermore, it is also necessary to output the converted digital value to the outside, which has the disadvantage of increasing test time. Furthermore, as the conversion accuracy increases to 9 bits and 10 bits, the number of ladder resistors increases to 512.degree. 1024, which increases the test time and makes this drawback even more noticeable.

The present invention has been made in view of such problems, and includes:
The object of the present invention is to provide a successive approximation type analog-to-digital conversion circuit that can perform tests in an extremely short time.

[Means for Solving the Problems] The analog-to-digital conversion circuit according to the present invention has an additional means for directly reading out the specified divided voltage of the resistance ladder circuit to the outside by establishing a test mode. It is.

That is, the analog-to-digital conversion circuit according to the present invention is
a resistor ladder circuit that outputs a specified divided voltage among a plurality of divided voltages obtained by dividing a reference voltage; an input terminal that inputs an analog voltage; a voltage comparison circuit that compares a specified divided voltage; a successive approximation register that sequentially stores comparison results of the voltage comparison circuit; and mode switching means for switching between a test mode and a normal operation mode;
Means for specifying a divided voltage for the resistor ladder circuit based on the output of the successive approximation register in normal mode and a divided voltage that is not observed in test mode; and a switch for connecting the input terminal to the output of the resistor ladder circuit in the test mode.

[Operation] According to the present invention, by specifying the test mode,
The specified divided voltage from the resistor ladder circuit is output directly to the terminal via the switch. Therefore, in this case, A/
There is no need to perform D conversion, and the accuracy of the resistance ladder circuit can be checked in an extremely short time by outputting the divided voltage to the outside a number of times corresponding to the resolution of the A/D converter. Also,
The accuracy of the voltage comparator circuit can be checked by applying some representative analog input voltages.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an A/D converter according to an embodiment of the present invention. The same parts as in FIG. 3 are given the same reference numerals. This A/D converter differs from conventional ones in that it includes a mode register 11° selector 12. counter 13
．． and a switch 14 is added. The mode register 11 stores 1-bit mode designation information for specifying either a normal A/D converter operating mode (hereinafter referred to as "normal mode") or a test mode. When the mode designation information indicates the normal mode (for example, "0"), the selector 12 provides the output of the successive approximation register 5 as input information to the resistance ladder circuit 1;
When the mode designation information indicates the test mode (for example, 1"), the value of the counter 13 is given as input information to the resistance ladder circuit 1. The counter 13 is a counter with the same number of bits as the number of bits n of the A/D converter. The switch 14 connects the analog voltage input terminal 2 to the input terminal of the voltage comparison circuit 3 in the normal mode, and connects the terminal 2 to the output terminal of the resistance ladder circuit 1 in the test mode. Connect to.

Next, the operation of the A/D converter configured as described above will be explained.

In this circuit, two types can be selected: a normal mode in which the converter operates like a normal A/D converter, and a test mode in which a ladder resistance test is performed to determine conversion accuracy.

First, when the mode register 11 is set to 0'', the normal mode is designated.At this time, the switch 14 detects that the analog voltage ■lfl applied to the terminal 2 is set to the voltage comparator circuit 3.
connected to be input. Further, the selector 12 selects the output of the successive approximation register 5. When the counter 6 is reset and its count value reaches the initial value O, the decoder 7 decodes O and outputs a decoder output "1" to the AND gate 41. Subsequently, the conversion operation is started. Assuming that the resolution of the resistance ladder circuit 1 is 1/256 and the successive approximation register 5 is 8 bits, before the conversion starts, the successive approximation register 5 corresponds to a voltage value V, /2, which is 1/2 of the reference voltage ■, It is set to a digital value (7FH). As a result, the resistance ladder circuit 1 outputs V,/2 as a divided voltage. The analog voltage input to terminal 2 and the divided voltage V, /2 of resistance ladder circuit 1 are compared by voltage comparison circuit 3, and the comparison result is ANDed.
It is stored in the most significant bit of the successive approximation register 5 via the gate 41. If the analog input voltage Vl, is greater than V,/2, the most significant bit of the successive approximation register 5 is “1”.
”, and at the same time sets the next lower bit to “0”, and its value becomes (BFH). On the other hand, the analog input voltage VI
If fi is smaller than V, /2, successive approximation register 5
The most significant bit of is set to O'', and at the same time, the next lower bit is set to O'', and its value becomes (3FH). When one comparison is completed, clock signal ψ1 is output. A count-up operation is performed in synchronization with the signal ψ1. As a result, the count value becomes 1'', so the decoder 7 outputs II II II to the AND gate 42. At this time, the output of the successive approximation register 5 determined when the count value is "0" is input to the resistance ladder circuit 1 via the selector 12. As a result, the tap output of the reference voltage Vr in the resistance ladder circuit 1 is selected and compared with the analog input voltage vIfl. Thereafter, the counter 6 counts up each time one comparison is completed, and the analog input voltage Vla is compared with the output voltage of the resistor ladder circuit 1, and the comparison result is successively counted up until the comparison result reaches the least significant bit of the successive approximation register 5. Once stored, the count-up operation of the counter 6 ends and the digital conversion cycle ends. Therefore, at the end of the conversion, the contents of the successive approximation register 5 indicate a digital value that approximates the analog input voltage with a resolution of 1/256.

Next, a test operation of the resistance ladder circuit 1 in the test mode will be explained.

When mode register 11 is set to “1”, selector 1
2 inputs the output of the counter 13 to the resistance ladder circuit 1. Further, the switch 14 connects the terminal 2 to the output end of the resistance ladder circuit 1. The counter 13 is reset and its count value is set to the initial value "0".The count value is input to the resistor ladder circuit 1 via the selector 16. When the resolution of the resistance ladder circuit 1 is 1/256, the counter 13 is 8 bits, so the resistance ladder circuit 1 outputs a voltage corresponding to the count value m of the counter 13, That is, m/of the reference voltage V,
Outputs 256 times the voltage. This voltage is
By counting up 3, they are output one after another.

This divided voltage is output to terminal 2 via switch 14. Therefore, by measuring the voltage αvr at terminal 2 externally, it is possible to perform a ladder resistance test that determines conversion accuracy.

The voltage comparison circuit 3 operates by setting the mode register 11 to "0" and inputting three to four types of analog voltages to the terminal 2 to perform an A/D conversion operation test similar to the conventional example. do it.

FIG. 2 is a diagram showing another embodiment of the present invention.

In this embodiment, the selector 12 and counter 1 of FIG.
3, the output of the successive approximation register 15 can be specified externally as a digital value for testing when the mode register 11 is "1''. Therefore, in the test mode, the output of the successive approximation register 15 is The resistance ladder circuit 1 selects the reference voltage tap output based on the output of the comparison register 15, and outputs it to the terminal 2 via the switch 14.Other structural requirements are the same as in the previous embodiment.

According to this embodiment, the digital value to be tested can be input to the successive approximation register 15 via the mode register 11, so if high accuracy is not required, the test time can be reduced by testing only an arbitrary digital value. can be made shorter.

Note that when the mode register 11 is “0”, the normal A
/D converter.

In each of the above embodiments, a mode register is provided for setting the test mode, but the test mode may also be set from an external terminal or the like.

[Effect of the invention] As explained above, the present invention achieves A
Since each voltage level of the ladder resistor, which serves as the standard for A/D conversion accuracy, can be output directly to the outside and measured, the test can be completed in a fraction of the time without requiring A/D conversion operation time. effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an A/D converter according to an embodiment of the present invention, FIG. 2 is a block diagram of an A/D converter according to another embodiment of the present invention, and FIG. 3 is a conventional A/D converter. FIG. 1; Resistance ladder circuit, 2; Terminal, 3; Voltage comparison circuit, 4
1 to 4n; AND gate; 5, 15; successive approximation register; 6; counter; 7; decoder; 11; mode register; 12; selector; 13; counter; 14; switch

Claims (1)

[Claims] (1) A resistor ladder circuit that outputs a specified divided voltage among a plurality of divided voltages obtained by dividing a reference voltage, an input terminal that inputs an analog voltage, and the analog input through this input terminal. a voltage comparator circuit that compares a voltage with the designated divided voltage; a successive approximation register that sequentially stores comparison results of the voltage comparator circuit; mode switching means for switching between a test mode and a normal operation mode; means for specifying a divided voltage for the resistance ladder circuit based on the output of the successive approximation register in a normal mode and a divided voltage to be observed in a test mode;
An analog-to-digital conversion circuit comprising a switch that connects the input terminal to one input of the voltage comparison circuit in a normal mode and connects the terminal to an output of the resistance ladder circuit in a test mode.