JPH0241049B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a floating point number data processing device using a variable length exponent representation method.

[Prior Art] Floating point representation is a representation method used particularly in scientific and technical calculations because it can handle both large and small numbers with high precision.

However, conventional floating-point data arithmetic devices have the disadvantage that the exponent display part has a constant length, which limits the range of numbers that can be expressed. The drawback was that there was no flexibility in using that space to improve the precision of the mantissa.

A typical example of conventional floating point representation is shown in FIG.

In the figure, 1 is 1 bit of data code information, 2 is 1 bit of exponent code information, and 4 is absolute value information of the exponent, and 2 and 4 together are also called an exponent part. 5 is the mantissa part, and 6 is the boundary between the exponent part and the mantissa part.

[Problems to be Solved by the Invention] In the conventional floating point representation, the boundary 6 between the exponent part and the mantissa part is fixed.
That is, the number of bits for displaying the exponent part was constant. This caused the practical inconveniences mentioned above.

SUMMARY OF THE INVENTION An object of the present invention is to provide a floating-point data processing apparatus using a floating-point variable-length exponent representation method that eliminates the above-mentioned drawbacks of the conventional floating-point representation method.

[Means for Solving the Problems] In order to achieve the above object, the floating point data processing device of the present invention consists of a string of “0” or a string of “1” with a length determined depending on the value of an exponent. From floating point data having an exponent part consisting of the first half of the exponent part and the second half of the exponent part which has a length determined depending on the length of the first half of the exponent part and specifies the value of the exponent,
Means for dividing the second half of the exponent part and the mantissa part according to the length of the "0" row or "1" row in the first half of the exponent part, and predetermined processing for the divided second half of the exponent part and the mantissa part. and means.

[Operation] Data targeted by the present invention is expressed using the same expression method whether the index is large or small. The apparatus of the present invention can process the exponent part and mantissa part of such characteristic data separately.

[Embodiments of the Invention] Before going into a specific explanation of the floating point arithmetic device according to the present invention, let us explain the exponent variable-length floating point representation system (hereinafter referred to as “this expression” or “this expression system”) used in the arithmetic device of the present invention. ) will be explained in detail.

The key point of this representation method is the leading “0” in the exponent part.
The length of the exponent part is determined by the sequence of or the sequence of "1". As a result, numbers close to 1, which frequently appear in daily life, can be expressed with a shorter exponent and longer mantissa, making it possible to express them more accurately than before. Even extremely small numbers can be expressed because the exponent part can be long.

The method for determining the length of the exponent part will be specifically explained below. The floating point representation of a number is defined as follows.

(i) This expression can express the number 0 and infinity as follows.

0 “000……0” Infinity “100……0” Below, we will discuss other numbers.

(ii) Assume that a number x is expressed by an exponent e and a mantissa m as follows.

x=m·2 ^e Here, e is an integer, and m is defined as follows according to the sign of x.

is also stipulated as follows.

(a) When x>0 1m<2,=m-1 (b) When x<0 −2m−1, m=+2 Also, is defined as follows.

(a) When e0 =e+1 (b) When e<0 =-e Furthermore, n is defined as follows.

n=[log ₂ ]+1 However, the symbol [ ] is a Gauss symbol,
[x] represents the largest integer not exceeding x.

(iii) This representation and bit arrangement are basically the same as the arrangement shown in Figure 3. However, the length of the exponent part is variable and is 2n bits.

(iv) Bit 1 of code information is 0 when x>0, and bit 1 is 0 when x<0.
When it is 0, it is 1 (same as the conventional expression).

(v) The exponent part is defined as follows:

(a) The left n bits are a string of "1"s.

(b) The right n bits are a bit string of length n obtained by binary expansion, with the left end changed to "0".

(c) However, when x<-1 or 0<x<1, it is one's complement of what is determined by (a) and (b) above.

(vi) The mantissa is defined as follows:

When the binary expanded form of is 0・b ₁ b ₂ b ₃ ......, it is as long as necessary from the left of the bit string "b ₁ b ₂ b ₃ ......".

The above definition uniquely determines the number represented by any bit string.

As an example, a case of several 100 will be specifically explained. The number 100 is expressed as follows.

100=(25/15)×2 ³ Therefore, according to the above rules, e=6, m=25/16
and =7, =9/16, n=3.

FIG. 2 shows floating point representation according to this representation. Sign bit 1 is “0” because the number is positive, and since n=3, the left 3 of the exponent part
Bit 3a is the “1” column, right 3 bits 3b is 2
This is "011", which is obtained by changing the first "1" of the expanded value "111" to "0". Since the binary expanded form of the mantissa part 5a is 0.100100000..., it is "100100000...".

As described above, in this representation, the string of "0"s or strings of "1s" preceding the exponent part determines the length of the exponent part.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing the main parts of a floating point data arithmetic device showing one embodiment of the present invention.
In the figure, 11 is a floating point register, 12 is a mantissa register, 13 is an exponent register, 14 is a counter, 15 is a flip-flop, and 16 is a
is a two-input logic circuit.

Let the length of floating point register 11 be k+1 bits. The right k bits excluding sign bit 17 are a shift register and have the following functions.

(1-1) Each time the left shift trigger 31 is applied, the bit is shifted to the left by 1 bit.

(1-2) Each time the right shift trigger 32 is applied, the bit is shifted to the right by one bit.

(1-3) Transfer the value to the mantissa register 12.
The mantissa register 12 is a shift register having a length k bits and has the following functions.

(1-4) Each time the left shift trigger 33 is applied, the bit is shifted to the left by one bit.

(1-5) Each time the right shift trigger 34 is applied, the bit is shifted to the right by one bit.

(1-6) Transfer the value to floating point register 11. The exponent register 13 is a shift register having a length of k bits and has the following functions.

(1-7) Each time the left shift trigger 35 is applied, the bit is shifted to the left by one bit.

(1-8) Every time the right shift trigger 36 is given, it is shifted to the right by 1 bit. (1-9) The value is increased by 1 by the value increase trigger 37.

(1-10) Decrease the value by 1 using the low value range trigger 38.

(1-11) The complement trigger 39 inverts the values of each bit to "0" and "1" all at once.

(1-12) Detect that all bits are “0”. Two-input logic circuit 16 generates an output as shown in FIG. 4 according to the values of inputs 40 and 41. When shifting in each of the shift registers, unless otherwise specified, the information of overflowing bits is lost and the bits to be supplied are "0".

The operation of the apparatus of this embodiment having the above-mentioned configuration will be explained below.

Data calculations using this expression are performed in the following steps.

(1) Counting a column of “0” or “1” (2) Separating the exponent and mantissa parts (3) Adjusting the value of the exponent in addition and subtraction (4) Calculation (5) Normalization (6) Exponent Combining part and mantissa (7) Inserting a string of "0" or "1" Of these, steps (2) to (6) are performed for the conventional fixed-length floating-point representation of the exponent part. Steps (1) and (7) are the steps for processing data using this expression,
This will be explained in detail.

(1) Counting a column of “0” or “1” (a) Set the value of the counter 14 to 0. The value of the first bit 18 of the floating point register 11 excluding the sign bit 17 is set in the flip-flop 15.

(b) Put the first bit 18 of the floating point number register 11 into the input 40 of the logic circuit 16; The value of flip-flop 15 is applied to input 41 of logic circuit 16. Logic circuit 16 at this time
The counter 14 counts the output (“1”).

(c) The next step (d) is repeated until the output of the logic circuit 16 becomes "0", and the counter 14 counts the number of times.

(d) Shift the floating point number register 11 to the left using the function (1) above. Newly said first bit 1
8 is input into the input 40 of the logic circuit 16. The value of flip-flop 15 is applied to input 41 of logic circuit 16.

(e) The first value of the floating point register 11 at the time when the output of the logic circuit 16 becomes “0”
Invert the value of bit 18.

(2) Separation of exponent and mantissa parts (a) Enter the value of the first bit 18 of the floating point register 11 into the input 40 of the logic circuit 16. The value of flip-flop 15 is applied to input 41 of logic circuit 16. The value of the counter 14 is decremented by 1, and at this time the logic circuit 16
The above function (1-
7), the exponent part register 13 is shifted to the left.

(b) Repeat steps (e) and (d) while decreasing the value of the counter 14 by 1 until it becomes 0.

(c) Floating point register 11 is set to the above function (1
-1) to shift to the left. Newly said 1st
The value that comes to bit 18 is input to input 4 of logic circuit 16.
Put it in 0. The value of flip-flop 15 is applied to input 41 of logic circuit 16.

(d) Using the output of the logic circuit 16 as a supply bit,
Exponent register 1 is set by the function (1-7) above.
Shift 3 to the left.

(e) The function (1-
10) to reduce the value 1.

(f) Sign bit 17 and flip-flop 15
The value of is input to the logic circuit 16, and if the output value is "1", the complement is taken by the function (1-11).

(g) Transfer the value of the floating point register 11 to the mantissa register 12 using the function (1-3). The value of sign bit 17 is also transferred to sign bit 19 of mantissa register 12,
The value obtained by inverting the value of the sign bit 17 by the inverter 22 is transferred to the left bit of the decimal point position 20 of the mantissa register 12.

In this state, the value of e is stored in the exponent register 13 as an integer (a negative number is reinforced with 2), and the value of m is stored in the mantissa register 12 as a decimal number (a negative number is a 2's complement). (as).In the above-mentioned concrete example, the number 100
Exponent register 1 corresponding to Figure 2 in the case of
3. The contents of the mantissa register 12 are shown in FIG.

Steps (3), (4), and (5) will be omitted and the explanation will move on to step (6).

(6) Combination of exponent and mantissa parts (a) Transfer the contents from the mantissa register 12 to the floating point register 11 using the function (1-6) above.

(b) The sign bit 21 of the exponent register 13 is input to the input 40 of the logic circuit 16, the sign bit 19 of the mantissa register 12 is input to the input 41, and the output is input to the flip-flop 15.

(c) When the value of the sign bit 21 is "1", the complement of the exponent part register 13 is taken by the function (1-11).

(d) Increase the value of the exponent register 13 by 1 using the function (1-9). Set the value of the counter 14 to 0.

(e) Next (f) while increasing the value of counter 14,
The above function (1-12) is repeated until the value of the exponent register 13 becomes 0.

(f) Set the exponent register 13 to the above functions (1-8).
Shifts one bit to the right. The overflowing bits are input to the input 40 of the logic circuit 16, the value of the flip-flop 15 is input to the input 41 of the logic circuit 16, and the output is input to the floating point register 11 by the function (1-2) to the right. Used as bits supplied from the left end when shifting by one bit.

(7) Inserting a string of “0” or “1” (a) First bit 1 of floating point register 11
Invert the value of 8.

(b) The value of the counter 14 (step (6))
Execute the following (c) only by (e)).

(c) Using the value of the flip-flop 15 as a supply bit, shift the contents of the exponent register 13 to the right by one bit by the function (1-8).

Due to the above-described operation, the floating point arithmetic device of the present invention is capable of mutually converting a value expressed using a conventional fixed-length floating-point exponent part and a value expressed using a new expression method, a variable-length floating-point exponent part. This makes it possible to put into practical use the exponent variable-length floating point representation, which is an effective representation method, using conventional arithmetic devices.

It goes without saying that each component of the above embodiment can be replaced with other specific means having substantially the same function.

As described above, the processing device of the present invention uses a variable-length exponent representation method that can express numerical values close to 1 that frequently appear in daily life with higher accuracy than before, and can also express extremely large numbers and extremely small numbers. This has the remarkable effect of making it possible to use the information effectively.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an arithmetic unit showing an embodiment of the present invention, FIG. 2 is a diagram showing variable length floating point representation of the exponent part, FIG. 3 is a diagram showing fixed length floating point representation of the exponent part, and FIG. 5 is a diagram showing the input/output relationship of the logic circuit, and FIG. 5 is a diagram showing the contents of the registers in FIG. 4. 11: floating point register, 12: mantissa register, 13: exponent register, 14: counter, 15: flip-flop, 16: logic circuit, 22: inverter.

Claims (1)

[Claims] 1. The first half of an exponent part consisting of a string of "1"s or a string of "0"s with a number of bits determined depending on the value of the exponent, and a bit number determined by the number of bits in the first half of the exponent part. Floating point representation data consisting of a variable-length exponent part and a mantissa part with a second half of the exponent part specifying the value of the exponent is input, and the "1" in the first half of the exponent part of the data is input. means for dividing the second half of the exponent part and the mantissa part of the data depending on the length of the column or the string of "0"; and processing for the divided second half of the exponent part and the mantissa part. a floating point data processing apparatus having means for executing. 2. The dividing means converts the second half of the exponent part and the mantissa part into fixed-length exponent part data and fixed-length mantissa part data having a predetermined relationship with respect to the respective values, and executes the processing. 2. A floating point data processing device according to claim 1, comprising means for outputting data to a floating point data processor. 3. The input data has a sign bit representing the sign of the numerical value corresponding to the input data, and the predetermined relationship depends on the combination of the value of the sign bit of the numerical value and the value of each bit in the first half of the exponent part. and the first part of the exponent part data consists of a string of bits representing the sign of the exponent part data, the number of bits depending on the number of bits in the second half of the exponent part,
The mantissa data has a value equal to the sign bit of the numerical value, and is determined depending on the sign bit added to the beginning of the divided mantissa and the number of bits of the divided mantissa. 3. The floating point data processing device according to claim 2, wherein the floating point data processing device has a value "0" bit string added to the end of the divided mantissa part of the number.