JPH0241297U - - Google Patents
Info
- Publication number
- JPH0241297U JPH0241297U JP11945588U JP11945588U JPH0241297U JP H0241297 U JPH0241297 U JP H0241297U JP 11945588 U JP11945588 U JP 11945588U JP 11945588 U JP11945588 U JP 11945588U JP H0241297 U JPH0241297 U JP H0241297U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- order
- frame memory
- display
- graphics
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Description
第１図はこの考案の一実施例を示す表示装置の
構成図、第２図はこの考案の一実施例を示す座標
変換回路の構成図、第３図はフレームメモリの読
み出し動作及び表示状態を示す図、第４図は従来
の表示装置の構成図である。
図において、１はマイクロコンピユータ、２は
フレームメモリ、３はスキヤン信号発生回路、４
は表示部、５は座標変換回路である。なお、図中
同一符号は同一または相当部分を示す。
Fig. 1 is a block diagram of a display device showing an embodiment of this invention, Fig. 2 is a block diagram of a coordinate conversion circuit showing an embodiment of this invention, and Fig. 3 shows the frame memory read operation and display state. The figure shown in FIG. 4 is a configuration diagram of a conventional display device. In the figure, 1 is a microcomputer, 2 is a frame memory, 3 is a scan signal generation circuit, and 4
5 is a display unit, and 5 is a coordinate conversion circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
を発生するために、文字や図形を構成する輝度信
号を発生するマイクロコンピユータと、このマイ
クロコンピユータにより発生した輝度信号を、表
示画面全体にわたり保持するフレームメモリと、
上記フレームメモリ上の輝度信号により表示を行
うため、フレームメモリの読み出し信号を発生す
るスキヤン信号発生回路と、前記読み出し信号を
表示画面の回転表示のため、フレームメモリ上の
読み出すメモリのアドレスを変換する座標変換回
路とを備えた表示装置。 In order to generate display signals for characters and graphics through digital processing, a microcomputer generates luminance signals that make up the characters and graphics, and a frame that holds the luminance signals generated by this microcomputer over the entire display screen. memory and
In order to perform display using the luminance signal on the frame memory, a scan signal generation circuit generates a frame memory read signal, and the read signal converts the address of the read memory on the frame memory in order to rotate the display screen. A display device equipped with a coordinate conversion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11945588U JPH0241297U (en) | 1988-09-12 | 1988-09-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11945588U JPH0241297U (en) | 1988-09-12 | 1988-09-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0241297U true JPH0241297U (en) | 1990-03-22 |
Family
ID=31364699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11945588U Pending JPH0241297U (en) | 1988-09-12 | 1988-09-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0241297U (en) |
-
1988
- 1988-09-12 JP JP11945588U patent/JPH0241297U/ja active Pending
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