JPH0281590U - - Google Patents
Info
- Publication number
- JPH0281590U JPH0281590U JP16064588U JP16064588U JPH0281590U JP H0281590 U JPH0281590 U JP H0281590U JP 16064588 U JP16064588 U JP 16064588U JP 16064588 U JP16064588 U JP 16064588U JP H0281590 U JPH0281590 U JP H0281590U
- Authority
- JP
- Japan
- Prior art keywords
- frame memory
- generates
- luminance
- display
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Image Processing (AREA)
- Digital Computer Display Output (AREA)
Description
第１図は、この考案の一実施例を示す表示装置
の構成図、第２図はこの考案の一実施例を示す座
標変換回路の構成図、第３図はフレームメモリの
読み出し動作及び表示状態を示す図、第４図は従
来の表示装置の構成図である。
図において、１はマイクロコンピユータ、２は
フレームメモリ、３はスキヤン信号発生回路、４
は表示部、５は座標変換回路である。なお、図中
同一符号は同一または相当部分を示す。
Fig. 1 is a block diagram of a display device showing an embodiment of this invention, Fig. 2 is a block diagram of a coordinate conversion circuit showing an embodiment of this invention, and Fig. 3 is a frame memory read operation and display state. FIG. 4 is a block diagram of a conventional display device. In the figure, 1 is a microcomputer, 2 is a frame memory, 3 is a scan signal generation circuit, and 4
5 is a display unit, and 5 is a coordinate conversion circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
を発生するために、文字や図形を構成する輝度信
号を発生するマイクロコンピユータと、このマイ
クロコンピユータにより発生した輝度信号を、表
示画面全体にわたり保持するフレームメモリ、上
記フレームメモリ上の輝度信号により表示を行う
ため、フレームメモリの読み出し信号を発生する
スキヤン信号発生回路、この読み出し信号を表示
画面の回転及び平行移動表示のため、フレームメ
モリ上の読み出すメモリのアドレスを変換する座
標変換回路を備えた表示装置。 In order to generate display signals for characters and graphics through digital processing, a microcomputer generates luminance signals that make up the characters and graphics, and a frame that holds the luminance signals generated by this microcomputer over the entire display screen. memory, a scan signal generation circuit that generates a frame memory readout signal to perform display using the luminance signal on the frame memory, and a scan signal generation circuit that generates a readout signal of the frame memory to perform display using the luminance signal on the frame memory; A display device equipped with a coordinate conversion circuit that converts addresses.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16064588U JPH0281590U (en) | 1988-12-10 | 1988-12-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16064588U JPH0281590U (en) | 1988-12-10 | 1988-12-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0281590U true JPH0281590U (en) | 1990-06-22 |
Family
ID=31442893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16064588U Pending JPH0281590U (en) | 1988-12-10 | 1988-12-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0281590U (en) |
-
1988
- 1988-12-10 JP JP16064588U patent/JPH0281590U/ja active Pending
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