JPH0241476U - - Google Patents

Info

Publication number
JPH0241476U
JPH0241476U JP1988120757U JP12075788U JPH0241476U JP H0241476 U JPH0241476 U JP H0241476U JP 1988120757 U JP1988120757 U JP 1988120757U JP 12075788 U JP12075788 U JP 12075788U JP H0241476 U JPH0241476 U JP H0241476U
Authority
JP
Japan
Prior art keywords
bumps
recess
electronic component
bump portion
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988120757U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988120757U priority Critical patent/JPH0241476U/ja
Publication of JPH0241476U publication Critical patent/JPH0241476U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は、本考案の原理説明図、第２図及び第
３図は、本考案の実施例を示す図、第４図及び第
５図は、本考案の他の実施例を示す図、第６図は
、従来の技術例を示す図である。 図において、１はプリント基板、２は位置ずれ
防止のための基板のパツド上のくぼみ、３はバン
プ、４は電子部品。

Claims (1)

  1. 【実用新案登録請求の範囲】 バンプ付き電子部品４のバンプ部３に対向する
    プリント基板１のパツド部にくぼみ２を設け、 該バンプ付き電子部品４のバンプ部３が該くぼ
    み２の位置にて接合されてなるバンプ付き電子部
    品の実装構造。
JP1988120757U 1988-09-14 1988-09-14 Pending JPH0241476U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988120757U JPH0241476U (ja) 1988-09-14 1988-09-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988120757U JPH0241476U (ja) 1988-09-14 1988-09-14

Publications (1)

Publication Number Publication Date
JPH0241476U true JPH0241476U (ja) 1990-03-22

Family

ID=31367151

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988120757U Pending JPH0241476U (ja) 1988-09-14 1988-09-14

Country Status (1)

Country Link
JP (1) JPH0241476U (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05275841A (ja) * 1992-03-30 1993-10-22 Nec Corp 多層印刷配線板
WO2018042846A1 (ja) * 2016-08-30 2018-03-08 株式会社村田製作所 電子デバイス及び多層セラミック基板

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05275841A (ja) * 1992-03-30 1993-10-22 Nec Corp 多層印刷配線板
WO2018042846A1 (ja) * 2016-08-30 2018-03-08 株式会社村田製作所 電子デバイス及び多層セラミック基板
CN109644559A (zh) * 2016-08-30 2019-04-16 株式会社村田制作所 电子器件以及多层陶瓷基板
JPWO2018042846A1 (ja) * 2016-08-30 2019-06-24 株式会社村田製作所 電子デバイス及び多層セラミック基板

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