JPH024184B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a demodulation device that demodulates a composite PSK-PSK modulated wave in which a PSK-modulated signal using a main data signal is further two-phase PSK-modulated using a sub-data signal. In recent years, the development of carrier wave digital transmission systems has been remarkable, and various lines have already been put into practical use. However, recently, the required transmission systems have tended to be diversified, and it is important to find a transmission system that is versatile and has high operational efficiency. Consideration has begun. One of these is the ``carrier wave digital transmission system'' described in Japanese Patent Application No. 1983-37004 filed by the inventors of the present application on March 29, 1973. This method involves adding two-phase PSK modulation to the main data line using PSK modulation to perform composite transmission of sub data signals. According to this method, the code transmission speed of the sub data signal is compared to that of the main data signal. If the ratio is below a certain level, the sub data signal can be efficiently transmitted without affecting the error rate of the main data signal. However, in this system, a demodulator that can adapt to polyphase PSK waves such as 4PSK and 8PSK as the main data signal has not yet been established. Therefore, an object of the present invention is to
It is an object of the present invention to provide a demodulator that adopts the PSK-PSK system and can be adapted to polyphase PSK waves including 4PSK and more as a main data signal. According to the present invention, a signal subjected to 8-phase PSK modulation by a sender data signal having a code transmission rate f ₁ is further modulated into 2-phase PSK by a sending sub-data signal having a code transmission rate f ₂ (f ₁ > f ₂ ). In order to demodulate a modulated wave, a demodulation device including an orthogonal demodulator that obtains at least two demodulated signals having an orthogonal relationship from an input signal receives the two demodulated signals and compares them to one of the demodulated signals. (2 four first multipliers that receive and multiply outputs from the first multipliers, two second multipliers that receive mutually orthogonal outputs from the first multiplier outputs and multiply them; and the second multipliers. The third multiplier output is multiplied by the
a multiplier, a discriminator that identifies the output of the third multiplier at a certain discrimination level and obtains a reproduced sub-data signal with a code transmission rate of f ₂ ; a second phase shifter that obtains eight columns of outputs whose phases are shifted by mπ/8 radians (m=0, 1, 2, . . . 7); four selection circuits each receiving one pair having a phase difference of 8 radians and selecting and outputting one of the pairs according to the reproduced sub-data signal having the code transmission rate f ₂ to obtain a reproduced main data signal having the code transmission rate f ₁ ; There is obtained a demodulator characterized by comprising: Next, embodiments of a demodulator according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the structure of a first embodiment of a demodulator according to the present invention. Note that this example shows a case where 4PSK waves are applied as the main data signal, as seen in the coordinate system of FIG. 2. In Fig. 1, 1 is a quadrature demodulator, 2 to 5 are resistors, 6 to 7, 15 are adders, and 8
~9, 16 are subtractors, 10 to 12 are multipliers, 13
is a low-pass filter, 14 is a discriminator, 17 and 18 are analog switches, and 19 is a negative circuit. In such a configuration, an input signal enters the orthogonal demodulator 1, undergoes delayed detection or synchronous detection, and is converted into two demodulated signals P and Q that are orthogonal to each other. These signals are supplied to the sub data reproducing section and the main data reproducing section. First, to explain the sub data reproducing section, P and Q signals are connected to resistors 2 to 5,
The signals enter a phase shifter consisting of adders 6 and 7 and subtracters 8 and 9, where they are converted into output signals 101 to 104 having the phase relationships shown in Table 1.

[Table] Of these, signals 101 and 102 enter the multiplier 10 and are multiplied to become 105, and 103 and 1
04 is multiplied by the multiplier 11 and becomes a signal 106. Further, 105 and 106 are multiplied by multiplier 12 to obtain signal 107. This 107 signal is the input signal multiplied by 4, so that the main data signal is removed and only the sub data signal is left.
A low-pass filter 13 removes noise components from this signal.
If the data is discriminated by the discriminator 14 via the discriminator 14, the sub data signal CH3 is obtained via the NOT circuit 19 on its output side. Next, the main data reproducing section will be explained. The demodulated signals P and Q pass through an adder 15 and a subtracter 16 and become signals 108 and 109 delayed by π/4 radians from the P and Q signals, respectively. Furthermore,
The signals P and 108 enter the analog switch 17, where the output of the sub data signal CH3 becomes "0".
When , signal P is selected, and when it is "1", signal 10 is selected.
8 is selected to derive the signal 110 at its output. Similarly, the signals Q and 109 enter the analog switch 18, where when the output of the sub data signal CH3 is "0", the signal Q is selected, and when it is "1", the signal Q is selected.
Signal 109 is selected and signal 11 is applied to its output.
Derive 1. FIG. 3 shows signal waveforms at various parts in the embodiment of FIG. 1. In this figure, the horizontal axis θ
represents the phase relationship between the input signal and the demodulated reference signal, and when the modulated wave shown in FIG. 2 is input, the demodulated signals P and Q are a ₁ to a ₈ and
The signal has values from a ₁ ′ to _{a 8} ′. As can be seen by focusing on the operating waveforms (G) and (H), the main signal CH1 in (H)' and CH2 in (G)' have θ equivalent to lπ/2 (l=1 , 2, 3, ...) The phase is detected in terms of radians, resulting in 4
This means that an output equivalent to phase detection is obtained. FIG. 4 is a block diagram showing the configuration of a second embodiment of the demodulator according to the present invention.
This example shows a case where the main data signal is an 8PSK wave, and 30 in the figure is a quadrature demodulator, 31 to 38,
56-59 are resistors, 39-42, 60-62 are adders, 43-46, 63-65 are subtracters, 47
53 is a multiplier, 54 is a low-pass filter, 55 is a discriminator, 66 to 69 are analog switches, and 70 is a negative circuit. First, to explain the sub data reproducing section, the P and Q signals enter a phase shifter composed of resistors 31 to 38, adders 39 to 42, and subtracters 43 to 46, and the P and Q signals enter the phase shifter as shown in Table 2. Output signals 201-208 having relationships are obtained. The contents of this second table are as follows: X=1, 2, 3...
8, expressed in (2X-1)π/16 radians.

[Table] Of these, signals 201 and 202, 203 and 20
4, 205 and 206, 207 and 208 are multiplier 4
7 to 50 respectively to obtain signals 209 to 212 at the respective outputs. Among these, the signals 209 and 210, 211 and 212 are multiplied by the next multipliers 51 and 52, respectively, and the signal 2
Outputs 13,214. These are further multiplied by a multiplier 53 and become an output signal 215. The signal 215 is, after all, the input signal multiplied by 8, and the main data of the 8PSK waves are removed, leaving only the sub data signal. Thus, by passing this signal through the low-pass filter 54 for noise removal and identifying it with the discriminator 55, the sub data signal CH5 can be obtained. Next, to explain the main data reproducing section, the demodulated signals P and Q are connected to resistors 56 to 59 and adders 60 to 60.
62, the output signal 21 enters the phase shifter constituted by subtractors 63 to 65 and has the phase relationship shown in Table 3.
6 to 221, respectively. The contents of this third table are m=0, 1, 2,...
...7, expressed in mπ/8 radians.

[Table] These output signals 216 to 221, P and Q
is input to the analog switches 66 to 69, and is selected as shown in Table 4 depending on the output state of the reproduced sub data signal CH5.

[Table] FIG. 5 shows signal waveforms of various parts in the embodiment of FIG. 4. In this figure, the horizontal axis θ represents the phase relationship between the input signal and the demodulated reference signal. Regenerated main data signals 222-22
5, as can be seen by referring to f to i in Fig. 5, θ is equivalently phase-detected at a point of lπ/4 (l = 1, 2, 3, . . . ) radians. This is obtained as an output equivalent to 8-phase phase detection. Although the above first and second embodiments have been described in the case where the modulation by the main data signal is 4-phase and 8-phase, respectively, the present invention can be similarly applied to the case where the main data signal is 8 or more phases. The applicability is clear. Further, in both the first and second embodiments, the sub data reproducing section includes a first phase shifter group,
Although the second phase shifter group is used in the main data reproducing section, the phase relationship between them is not limited to the values shown, and is different from the first embodiment in FIG. If the waveforms G and H in FIG. 3 are obtained, and the waveforms f to i in FIG. 4 are obtained for the second embodiment in FIG. 4, the first phase shifter group and the second phase shifter group The phase relationship with the phase shifter group can be freely selected. As is clear from the above explanation, according to the present invention, in the carrier wave digital transmission system in which two-phase PSK modulation is added to the main data line using PSK modulation as described in the prior art and sub data signals are compositely transmitted, Even if polyphase PSK waves including 4PSK or more are applied as the main data signal, it becomes possible to correctly reproduce the main and sub data signals from these modulated waves on the receiving side, which improves system operation. The efficiency can be improved and the effects obtained are significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of a demodulator according to the present invention, FIG. 2 is a diagram showing a coordinate system when 4PSK waves are applied as main data to the embodiment in FIG. 3 is a diagram showing signal waveforms of each part in the embodiment of FIG. 1, FIG. 4 is a block diagram showing the configuration of a second embodiment of the demodulator according to the present invention, and FIG. It is a figure which shows the signal waveform of each part in Example. In the figure, 1, 30 are orthogonal demodulators, 6, 7,
15, 39-42, 60-62 are adders; 8,
9, 16, 43-46, 63-65 are subtractors, 1
0-12, 47-53 are multipliers, 13, 54 are low-pass filters, 14, 55 are discriminators, 17, 18, 6
6 to 69 are analog switches, and 19 and 70 are inverting circuits.

Claims (1)

[Claims] 1 A signal subjected to 8-phase PSK modulation by a sender data signal with a code transmission rate f ₁ is further transmitted at a code transmission rate f ₂
2-phase SPK by sending sub data signal of (f ₁ > f ₂ )
In a demodulation device equipped with an orthogonal demodulator that obtains at least two demodulated signals having an orthogonal relationship from an input signal in order to demodulate a modulated wave modulated into (2X−1)π/16 radians (X=1, 2
...8) A first phase shifter that obtains eight columns of phase-shifted outputs, and four first multipliers that receive mutually orthogonal outputs among the outputs of the first phase shifter and multiply them. , two second multipliers that receive mutually orthogonal outputs among the outputs of the first multipliers and multiply them;
a third multiplier that multiplies the multiplier output of the second multiplier; a discriminator that identifies the output of the third multiplier at a certain discrimination level and obtains a reproduced sub-data signal having a code transmission rate _f2 ; mπ/8 radians (m=0, 1, 2,
...7) A second phase shifter that obtains eight phase-shifted outputs, and a pair of outputs of the second phase shifter that have a phase difference of π/8 radians from each other and transmit the code. Either one is selected and output by the reproduced sub data signal with a speed of f ₂ , and the code transmission speed is f _1.
1. A demodulation device comprising four selection circuits for obtaining reproduced main data signals.