JPS59196651A - Demodulator - Google Patents

Abstract

PURPOSE:To improve the system operating efficiency by forming a main data signal into a polyphase PSK wave being >=4 PSK in the transmission system where a sub-data signal is transmitted compositely to a main data line using PSK modulation. CONSTITUTION:An input signal enters an orthogonal demodulator 1, where the signal is detected with delay or detected synchronizingly and the signal is converted into two demodulating signals P, Q being mutually in orthogonal relation. The P, Q signls enter a phase shifter comprising resistors 2-5 adders 6, 7, and subtractors 8, 9 and converted into output signals 101-104 having four phase relations. These signals are multiplied by multipliers 10-12 by 4-multiple to the input signal. Then, the main data signal is eliminated and only the sub- data signal remains. Further, the signals P, Q are formed into signals 108, 109 delayed respectively by pi/4 radian through multipliers 15, 16 and selected by the sub-data signal at analog switches 17, 18.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a demodulator that demodulates a composite PSK-PSK modulated wave whose signal is further two-phase PSK-modulated using a sub-data signal.

In recent years, the development of carrier wave digital transmission systems has been remarkable.
Various commercial lines already exist.

Recently, the required transmission methods have tended to become more diverse.
Studies have begun to consider transmission methods that are versatile and have high operational efficiency. One of them is that the inventors of the present application
There is a ``carrier wave dinotal transmission system'' described in Japanese Patent Application No. 1983-37004 filed on March 29, 1983. This is 2-phase PSK on the main data line using PSK modulation.
By applying modulation, the sub data signal is transmitted in a composite manner. According to this method, if the code transmission rate of the sub data signal is kept below a certain ratio compared to that of the main data signal, the error rate of the main data signal will be reduced. without affecting the
Sub data signals can be efficiently transmitted. However, in this method, 4PSK is used as the main data signal.
, 8PSR, etc., has not yet been established for a demodulator that can adapt to polyphase PSK waves.

Therefore, one object of the present invention is to
It is an object of the present invention to provide a demodulator which employs the K system and can be adapted to a polyphase PSK wave including 4PSK and higher polyphase PSK waves as a main data signal.

According to the present invention, a signal subjected to 2° (n = 2.3, 4.-1 phase PSK modulation) by a sender data signal having a code transmission rate f1 is further modulated by a transmitter data signal having a code transmission rate f2 (f+>fz). In order to demodulate a modulated wave that has been subjected to two-phase PSK modulation using a data signal, a demodulation device that is equipped with an orthogonal demodulator that obtains at least two modulated signals that are orthogonal to each other from an input signal is configured to convert the demodulated signal into a predetermined signal. a first phase shifter group that shifts the phase amount; and a multiplier that multiplies the output of the first phase shifter group by 211.

a first reproducing means for reproducing a data signal having a code transmission rate f2 in response to the output of the multiplier; a second phase shifter group for shifting the demodulated signal by seven steps to a predetermined phase amount; a removing means for removing a modulated component due to a data signal having a transmission rate of t-1i f 2 from the output of the second phase shifter group in response to the output of the reproducing means; There is obtained a demodulator characterized in that it comprises a second reproducing means for reproducing a data signal having a transmission rate f1.

Next, an embodiment of a demodulating device according to the present invention will be described with reference to one drawing.

FIG. 1 is a block diagram showing the configuration of a first embodiment of a demodulator according to the present invention. Note 2: In this example,
As seen in the coordinate system in Figure 2.

4. As the main data signal. This shows the case where PSK waves are applied. In FIG. 1, ■ is a quadrature demodulator, 2 to 5 are resistors, 6 to 7, 15 are W adders, 8 to 9, 16 are subtractors,
10 to 12 are multipliers, 13 is a low-pass filter, 14 is a discriminator, 17 and 1.8 are analog switches, and 19 is a negative circuit. In such a configuration, an input signal is input to the quadrature demodulator 1 and subjected to delayed detection.

Alternatively, it is synchronously detected and converted into two demodulated signals P and Q that are orthogonal to each other. These signals are supplied to the sub-data←reproducing section and the main data reference->reproducing section. First, to explain the sub data reproducing section, P and Q signals are connected to resistors 2 to 5. Adder 6.7. and a phase shifter composed of subtractors 8 and 9, where they are converted into output signals 101 to 104 having the phase relationships shown in Table 1.

Table 1 Among these, signals 101 and 102 enter the multiplier 10 and are multiplied to become 105, and 103 and 104 are the signals that are multiplied by the multiplier 10.
Multiplying by 1 results in a signal of 106.

Furthermore, the river signals are removed from ], 05, and 106 by the multiplier 12, leaving only the sub data signals. If this signal is discriminated by a discriminator 14 via a low-pass filter 13 that removes noise components, a sub data signal (CH3) is obtained via a negative circuit 19 on the output side.

Next, to explain the main data reproducing section, the demodulated signal P
, Q pass through an adder 15 and a subtracter 16 to become signals 108 and 109 delayed by five Noans from the P and Q signals, respectively. Additionally, signals P and 108 enter analog switch 17.

Here, when the output of the sub data signal CHp is 0'', the signal P is selected, and when it is 1, the signal 10.8 is selected, and the signals ], ], 0 are derived on the output side. The signals Q and 109 enter the analog switch 18, where when the output of the sub data signal CH,3 is o''', the signal Q is selected, and when it is "t", the signal +09 is selected, A signal 111 is derived at its output.

FIG. 3 shows signal waveforms at various parts in the embodiment of FIG. 1. In this figure, the horizontal axis θ represents the phase relationship between the input signal and the demodulated reference signal, when the modulated wave shown in FIG. 2 is input.

Demodulated signals P and Q are a1 to a8 and a, respectively.
The signal has a value of L to a8'. In addition, as you can see by paying attention to (G) and (H) of the operating waveform, (H
The main signal CHI at )' and CH2 at (G)' are phase-detected at a point of 7 (t-1, 2, 3, -.) radians with the constraint that θ is equal, and as a result, This means that an output equivalent to four-phase phase detection has been obtained.

FIG. 4 is a block diagram showing the configuration of a second embodiment of the demodulator according to the present invention.

This example shows the case where the main data signal is 8PSK waves, and 30 in Figure 1 is a quadrature demodulator, 31-38° 56-59
are resistors, 39-42.60-62 are adders, 43-4
6.63-65 are subtracters, 47-53 are multipliers, 54 is a low-pass filter, 55 is a discriminator, 66-69 are analog switches, and 70 is a negative circuit. To briefly explain the sub data reproducing section, P and Q signals are connected to resistors 31 to 38 . Adders 39-42. The signal enters a phase shifter constituted by subtractors 43-46, and output signals 201-208 having the phase relationships shown in Table 2 are obtained.

Table 2 Among these, signals 201, 202, 203 and 204°20
5 and 206, 207 and 208 are multiplied by multipliers 47 to 50, respectively, and signals 209 to 2 are output to the respective output sides.
Get 12. Of these, signals 209 and 210, 211 and 212 are multiplied by the next multipliers 51 and 52, respectively, to output signals 21, 3 and 214. these are,
The signal is further multiplied by a multiplier 53 and an output signal 215 is obtained.

The signal 215 is, after all, the input signal multiplied by 8, and the main data of 8PSK eC is removed, leaving only the sub data signal. Thus, by passing this signal through the low-pass filter 54 for noise removal and identifying it with the discriminator 55, the sub data signal CH5 can be obtained.

Next, to explain the main data reproducing section, the demodulated signal P
, Q are resistors 56-59. Adders 60 to 62, subtracter 6
The signals enter a phase shifter having a configuration of 3 to 65 degrees, and are converted into output signals 216 to 221 having the phase relationships shown in Table 3, respectively.

Below is a blank space in Table 3. These output signals 216-221, P and Q enter analog switches 66-69 and are selected as shown in Table 4 depending on the output state of the reproduced sub-data signal CH5.

Table 4, FIG. 5 shows signal waveforms at various parts in the embodiment shown in FIG. In this figure, the horizontal axis θ represents the phase relationship between the input signal and the demodulated reference signal. The reproduced main data signals 222 to 225 are shown in (f) to (i) in FIG.
), it can be seen that θ is isometrically equal to 1 (
This means that phase detection is performed at points in radians (t-1, 2, 3, . . . ), and an output equivalent to 8-phase phase detection is obtained.

The first and second embodiments described above are explained for cases in which the modulation by the main data signal is 4-phase and 8-phase, respectively.However, the present invention can also be applied to cases in which the main data signal has 8 or more phases. It is clear that the same applies. However, both the first and second embodiments include the first phase shifter group in the sub data reproducing section.

A second phase shifter group is used in the main data reproducing section.

The phase relationship between these is not limited to the values shown; for the first embodiment in FIG. 1, the waveforms in FIGS. For the second embodiment in the figure, the phase relationship between the first phase shifter group and the second phase shifter group is free as long as the waveforms in FIGS. 4(f) to (i) are obtained. You can make a fortune telling by choosing.

As is clear from the above description, according to the present invention, in a carrier dinotal transmission system in which a sub data signal is compositely transmitted by adding two-phase PSK modulation to a main data line using PSK modulation as described in the prior art, Polyphase PSK and higher including 4 PSK as main data signal
Even if waves are applied, it is possible to correctly reproduce the main and sub data signals from these modulated waves on the receiving side, thereby increasing the operational efficiency of the system, which has a significant effect.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a first embodiment of a demodulator according to the present invention, and FIG. 2 shows a coordinate system when 4 PSK waves are applied as main data to the embodiment in FIG. 3 is a diagram showing the signal waveform of each part in the embodiment of FIG. 1, and FIG. 4 is a diagram showing the configuration of the second embodiment of the demodulator according to the present invention. The figure is a diagram showing signal waveforms of each part in the embodiment of Fig. 4. In the figure, 1.30 is a quadrature demodulator, 6,7° 15.3
9-4.2, 60-62 are adders, 8°9.16.
43-46. 63-65 are subtractors. 1, 0-12. 47-53 are multipliers, 13.54 are low-pass filters, 14.55 are discriminators, 17, 18° 66-69
is an analog switch, and 19.70 is a negative circuit. Figure 2 Convex To To Heku COo ○

Claims (1)

[Claims] ■, 2 due to the sender data signal with code transmission rate f1
In order to demodulate the modulated wave in which the (n=2, 3, 4, -) phase PSK modulated signal is further 2-phase PSK modulated by the sending sub data signal at the code transmission rate f2 (fl>fz), In a demodulation device including an orthogonal demodulator that obtains at least two demodulated signals having an orthogonal relationship between input signals, a first shifter that shifts the demodulated signal to a predetermined phase amount;
a phase shifter group, a multiplier for multiplying the output of the first phase shifter group by 2n, and a code transmission rate f which receives the output of the multiplier.
a first reproducing means for reproducing two data signals; a second phase shifter group for shifting the demodulated signal to a predetermined phase amount; a removing means for removing a modulated component due to a data signal having a code transmission rate f2 from the output of the phase shifter group; and a second reproducing means for reproducing data (g) at a code transmission rate f + from the output of the removing means. A demodulator comprising: