JPH024192B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a memory switch control system, and in particular to a data buffer memory for temporarily storing line data and an address for holding an address for accessing the data buffer memory. This invention relates to a switching control system in a time division exchange having a one-stage time switch that converts time slots using a control memory.

[Prior Art] FIG. 1 is a diagram showing a conventional switch control system. For example, a multiplex transmission line with a speed of 1544 Mb/s is used as the transmission line, and a data buffer memory that stores data signals sent from subscribers and addresses on this data buffer memory are accessed and input. A time slot conversion memory for shifting the data signal on the multiplex transmission path to an arbitrary time position on the output multiplex transmission path is provided corresponding to the time slot, and the data D of terminal A sent at time slot number t _i is A case is shown in which a data signal D _j from terminal _B sent with time slot number t _j is converted. In FIG. 1, 11 is an input multiplex transmission line, 12 is an output multiplex transmission line, 13 is a data buffer memory that stores data signals sent from subscribers for a certain period of time, 14 is a time slot counter, and 15 is a data buffer memory. A holding memory 16 performs time slot conversion of the buffer memory 13, and a selector 16 selects the output of either the time slot counter 14 or the time slot conversion holding memory 15. Note that the time slot conversion holding memory 15 is sequentially and periodically accessed by the same clock source as the time slot counter 14.
17 is a communication path switch for performing switching.

The data signals on the input multiplex transmission line 11 and the output multiplex transmission line 12 are time-division multiplexed into N time slots, and the addresses of the data buffer memory 13 correspond to each of the N time slot numbers. It is attached. Data buffer memory 13
The signals stored in the time slot conversion and holding memory 15 are read out at an arbitrary time by the designated address stored in the time slot conversion holding memory 15, and the write operation is periodically performed by the output of the time slot counter 14. For this reason, the data buffer memory 13
The address access time is divided into two phases: write time and read time.

Next, the operation of this conventional example will be explained using the time chart shown in FIG. Figure 2a shows the input multiplex transmission path, Figures 2b and c show the data buffer memory, and the second
Figure d shows the outgoing multiplex transmission path. By writing t _j at address t _i and t _i at address t j of the time slot conversion holding memory 15, the data signal _{D i of} the input multiplex transmission line 11 is written to address t _i of the data buffer memory. , reading is performed at time slot number t _j and sent to the outgoing multiplex transmission line 12. As a result of this operation, terminal B receives the transmission signal D _i from terminal A sent at time slot number t _i . On the other hand, the data signal D _j on the input multiplex transmission line 11 sent from terminal B to terminal A is written to address t _j of the data buffer memory, and read out at time slot number t _i . It is sent out to the outgoing multiplex transmission path 12 and received by terminal A. Through this series of operations, data signals between terminal A and terminal B are exchanged.

The above operation describes the exchange operation when communicating between low-speed terminals that uses only one time slot in one data frame to send and receive one data signal. A high-speed exchange operation between terminals using multiple time slots within a frame can be similarly explained.

The conventional method described above has the following three drawbacks. First, by making the time slot exchange holding memory 15 and the data buffer memory 13 into separate functional blocks, the number of peripheral interface hardware and interface lines increases. Second, since the addresses of the time slot conversion holding memory 15 and the data buffer memory 13 are assigned corresponding to the time slots on the multiplex transmission path 11 on the input side, storage of all time slots on the multiplex transmission path is possible. It is necessary to always have the necessary amount of buffer memory available. That is, this buffer memory 13 can actually only be used for the number of simultaneous connections (corresponding to calls), and the memory is not used effectively.

Thirdly, the data signal on the input multiplex transmission line 11 is
Not all of the signals are circuit-switched signals, but packet-switched signals are mixed, and each terminal cannot adapt to a communication format in which either circuit switching or packet switching can be selected at the time of call setup.

[Purpose of the invention]

The purpose of the present invention is to eliminate the above-mentioned conventional drawbacks, to make it possible to efficiently utilize the communication path memory, to simplify the hardware configuration, and to enable a new communication form, that is, line switching or packet switching, to be arbitrarily selected. The object of the present invention is to provide a memory switch control method that can be applied to various types of devices.

[Summary of the invention]

The memory switch control method of the present invention is a one-stage time slot conversion system that performs time slot conversion using a data buffer memory that temporarily stores line data and an address control holding memory that holds addresses for accessing the data buffer memory. In a time division exchange equipped with a switch, a buffer memory is provided which integrates the above-mentioned holding memory and the above-mentioned buffer memory, and the buffer memory is divided into an address control holding memory storage area and a buffer area for line data storage, and the above address control holding memory is stored. The feature is that writing and reading of line data is controlled based on the information contents for write control and read control read from the area for use.

[Embodiments of the invention]

FIG. 3 is a diagram showing the basic principle of the present invention.

In FIG. 3, 31 is a time slot counter that operates in synchronization with the phase of the data signal on the input multiplex transmission line 11, and 32 is a time slot counter that operates in synchronization with the phase of the data signal on the output multiplex transmission line 12. , 34 is a communication path switch that can realize time slot conversion within a unified buffer; 3
3 is read information from the communication path switch 34 (for controlling writing of data on the input multiplex transmission line 11 and for controlling reading of data onto the output multiplex transmission line 12)
and a selector circuit for switching the instruction information of the time slot counters 31 and 32. The operating principle of the present invention will be explained below.
This will be explained using the conversion of t _i ←→t _j as an example.

First, the write operation will be explained. Immediately before the data signal D _i carried by the time slot t _i on the input multiplex transmission path 11 arrives at the communication path switch 34, the time slot counter 31 is incremented in synchronization with the phase of the input multiplex transmission path 11. indicates the t _i address, and this information is selected by the selector 33 and the communication path switch 34 is accessed. The communication path switch 34 provides information for controlling the writing of data on the input multiplex transmission path 11 and output multiplex transmission path 12.
The memory area is divided into three memory areas 34A, 34B, and 34C for storing data read control information to and input multiplex transmission line data D _i , D _j , and when accessing address t _i , write control information α is read out, and the selector 33 performs switching control so that the information α is selected, thereby storing the data D _i carried in the time slot t _i at the address α of the communication path switch 34.

Next, the read operation will be explained. When the time slot counter 32, which operates in synchronization with the clock phase of the output multiplex transmission line 12, indicates address _tj , and the selector 33 is switched to access the readout control information, the t of the communication path switch 34 is Read control information α at address _j is read. This information α
is selected by the selector 33, data D _i of the input multiplex transmission path stored at address α of the communication path switch 34 is transferred onto the output multiplex transmission path 12 through the time slot. It is read using t _j .

Through the above series of operations, time slot conversion from t _i to t _j is performed. Similarly, the time slot conversion from t _j to t _i can be performed, and through the above series of operations, it is possible to realize communication path control to enable bidirectional communication between t _i and t _j . As is clear from the above description, these operations can be easily applied to one-way communication control (when only one of the time slot conversions of t _i →t _j or t _j →t _i is performed).

FIG. 4 shows an example of the operation cycle of the communication path switch 34. The A cycle is a cycle for reading write control information based on the counter information indicated by the time slot counter 31, and the C cycle is a cycle for reading out write control information based on counter information indicated by the time slot counter 31.
Based on this read information, the input/multiplex transmission path data 11 is written into the data buffer memory 34B in the communication path switch 34. In cycle B, the read control information is written based on the counter information indicated by the time slot counter 32. The read cycle, the D cycle, is a cycle for reading the data signal stored in the data buffer unit 34B in the communication path switch 34 to the output multiplex transmission line 12 based on the information read in the B cycle, and the E cycle is a software cycle. This is a cycle for writing to or reading from a holding memory unit (used to store write/read control information) when an order for channel control is sent out by a call processing program.

FIG. 5 shows the application of the principle of the present invention to a parallel switching system. Assume that the speed of the input multiplex transmission line 11 is, for example, 128 Mb/s, and the data signal sent from the terminal is octet multiplexed in units of 8 bits. 51 spreads this octet multiplexed data over 8 data frames.
This is a circuit that stores 64 bits of data and performs serial/parallel conversion as 64-bit parallel data.
This is a circuit for converting bit parallel data to the original serial octet multiplex data. in this way
By performing 64-bit serial-to-parallel conversion,
128Mb/s octet multiplex data is 128/64
The speed is reduced to Mb/s=2 Mb/s and time slot conversion is performed within the channel switch 34. When the channel switch 34 operates according to the operation cycle shown in FIG. 4, the cycle time of the memory used in the channel switch 34 is 1/5 x 1/2 (Mb/s) = 100 (nsec). Note that the communication path switch 34 controls the holding memories 34A and 34C for read control and write control.
The number of bits required for each address is 2.times.[[log ₂ n]] (bits), where n is the number of time slots in one data frame on the multiplex transmission path, and the number of required addresses is n words. However, [[ ]] shall be defined as follows.

[[G]]△ = When G is an integer, [[G]] = G When G is not an integer, [[G]] = [G+1] ([ ] indicates a Gauss symbol) In Figure 6, An example of a method for allocating addresses in a communication path switch when the present invention is used as a line concentration switch will be shown.

Figure 6 shows t ₂ ←→t ₄ (bidirectional communication), t ₀ ←→t ₂₄₈ (bidirectional communication), t ₇ ←→t ₁₀₂₂ (bidirectional communication), t ₁ →t ₃ (unidirectional communication). ) shows a method for allocating data buffers when time slot conversion is performed. In this example, when the time slot multiplicity (the number of time slots in one data frame) on the multiplex transmission path is 1024, areas for use are secured in order from the oldest numbers.

One write/read control area 34A, 3
4C is randomly assigned during call setup. If only such communication is performed at a certain point, the data buffer section 34B at this point is
The areas corresponding to addresses t ₀ to t ₁₀₁₆ are unused (indicated by diagonal lines) and can be effectively used for other purposes.

The method of allocating the data buffer area 34B will be described in more detail below. FIG. 7a shows an example of the structure of a management table when the data buffer area 34B shown in FIG. 6 is divided into units of 32 bytes (=256 bits) to create 256 modules. Each module 71 is composed of four consecutive blocks on the buffer area in FIG. In addition, as shown in FIG. 7b, a management table 72 is prepared for each module that shows which blocks are currently in use, and if only 1 block, 2 blocks, 3 blocks, or 4 blocks are used in each module. When in the state, the codes in the left half of the management table are 001, 010, 011,
Manage by setting it to 100. If no block is used, it is coded as 000, and this buffer area is used for other purposes on the buffer memory, as will be described later. The right half of the management table has a one-to-one correspondence with the buffer area allocation method, and is "1" when in use and "0" when not in use.
Store. In the example shown in Figure 7, the
This shows a case where there are 1024 time slots and a 64-bit wide buffer area can be allocated to each time slot, and the use/unuse status of this buffer area in 64-bit units corresponds to the right part of the management table. ing. Since one module is configured for every four time slots, the management table is
It has 256 entry addresses.

FIG. 8 shows an algorithm for allocating buffer areas when a request to search for an empty buffer area is input from the exchange control system during call setup using the above-mentioned management table.

It is checked whether there is a request to search for an empty buffer area from the exchange control system, and if there is no request, the presence or absence of a request is checked repeatedly until there is a request to release the used buffer area (steps 81 and 87). If there is a request to release the buffer area, the code in the management table 72 is subtracted by -1 and the table 72 is updated (step 88, (A)). Additionally, when there is a request to search for a vacant buffer area, all codes for each module in the management table 72 are set to "000".
If so, allocate the buffer area at the lowest address within the arbitrary module (steps 82 and 89). When the code for each module is “011”,
Since 3 out of 4 blocks are used, allocate the remaining free blocks (step
83, 90). When the code for each module is “010” or the code for each module is “001”
If there is, only two or one of the four blocks are used, so the lowest numbered unused buffer area within the arbitrary module is allocated (steps 84, 85, 91). When the allocation is completed, the code of the module is incremented by one and the usage/unusage status table is updated (step 92).

If NO in any of steps 82 to 85, all buffers are used, so a busy display is displayed (step 86).

FIG. 9 is a diagram showing, as another embodiment of the present invention, how to use a communication path switch when circuit switching data and packet switching data are mixed and multiplexed on a multiplex transmission path. It is. 91 is a control section, and 92 is a main storage section. 34 is a communication path switch section, which includes a data buffer section 342 for packet switching and a data buffer section 3 for line switching.
41.

As mentioned above, the line switching data buffer unit 34
1, the area other than the buffer area required for the number of simultaneous line-switched connections is vacant, so this area can be dynamically allocated as the packet-switched buffer area 342.
The control unit 91 has the above-mentioned management table 72 regarding buffer area allocation, and by using this information, it is possible to effectively utilize the buffer area of the communication path switch 34. Note that some of the packet data accumulated in the communication path switch 34 is mapped to the main storage section 92, and when the packet exchange buffer area 342 becomes vacant,
One example is a method in which the packet data is taken into the channel switch 34 again and processed by the control section 91. Regarding the above-mentioned free buffer area, it is also possible to map the program in the main storage section 92 to the channel switch 34 and use it by the control section 91, for example, by managing the free/occupied state in units of 32 bytes. It is.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to realize a communication path configuration that integrates the holding memory and buffer memory in a one-stage time switch, which simplifies the hardware configuration and facilitates configuration using LSI technology. becomes. In addition, even when packet-switched data signals and circuit-switched data signals coexist on multiple transmission paths, it is possible to use channel memory efficiently, making it economically effective when applied to new communication formats. It has the advantage of being able to demonstrate

[Brief explanation of drawings]

FIG. 1 is a block diagram of a memory switch type time-division conversion channel using the prior art, FIG. 2 is a time chart of FIG. 1, and FIG. 3 is a block diagram of a memory switch type channel according to the present invention. 4 is an operation cycle chart of the channel switch according to the present invention, FIG. 5 is a configuration diagram when the present invention is applied to a parallel switching system, and FIG. 6 is an example of address assignment within the channel switch. Example diagram, Figure 7 is an example of the configuration of the management table when allocating addresses in Figure 6, Figure 8 is a flowchart of the algorithm when allocating a free buffer area using the management table, and Figure 9 is FIG. 2 is a configuration diagram of an embodiment of an exchange in which the communication path switch according to the present invention is applied to a case where circuit switching data and packet switching data are mixed and multiplex transmitted on a multiplex transmission path. 11: Input multiplex transmission line, 12: Output multiplex transmission line, 1
3: Data buffer memory, 14: Time slot counter, 15: Holding memory, 16: Selector, 7: Channel switch, 31: Time slot count (synchronized with input multiplex transmission line), 32: Time slot counter (output multiplex transmission line). synchronized with the transmission line), 3
3: Selector, 34: Communication path switch using unified buffer, 51: Series/parallel switching circuit, 52: Parallel/serial conversion circuit, 71: Buffer area in communication path switch, 72: Communication path buffer management table, 91:
Control unit, 92: Main storage unit.

Claims (1)

[Claims] 1. A time division converter equipped with a one-stage time switch that converts time slots using a data buffer memory that temporarily stores line data and an address control holding memory that holds addresses for accessing the data buffer memory. A buffer memory is provided in which the holding memory and the buffer memory are integrated, the buffer memory is divided into an address control holding memory storage area and a line data storage buffer area, and the write data read from the address control holding memory storage area is provided. A memory switch control method characterized by controlling the writing and reading of line data based on the information content for control and readout control.